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microblaze: Prepare work for optimization in exception code
[deliverable/linux.git] / arch / microblaze / kernel / hw_exception_handler.S
CommitLineData
c4df4bc1
MS		 1/*
2 * Exception handling for Microblaze
3 *
4 * Rewriten interrupt handling
5 *
6 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
7 * Copyright (C) 2008-2009 PetaLogix
8 *
9 * uClinux customisation (C) 2005 John Williams
10 *
11 * MMU code derived from arch/ppc/kernel/head_4xx.S:
12 * Copyright (C) 1995-1996 Gary Thomas <gdt@linuxppc.org>
13 * Initial PowerPC version.
14 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
15 * Rewritten for PReP
16 * Copyright (C) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
17 * Low-level exception handers, MMU support, and rewrite.
18 * Copyright (C) 1997 Dan Malek <dmalek@jlc.net>
19 * PowerPC 8xx modifications.
20 * Copyright (C) 1998-1999 TiVo, Inc.
21 * PowerPC 403GCX modifications.
22 * Copyright (C) 1999 Grant Erickson <grant@lcse.umn.edu>
23 * PowerPC 403GCX/405GP modifications.
24 * Copyright 2000 MontaVista Software Inc.
25 * PPC405 modifications
26 * PowerPC 403GCX/405GP modifications.
27 * Author: MontaVista Software, Inc.
28 * frank_rowand@mvista.com or source@mvista.com
29 * debbie_chu@mvista.com
30 *
31 * Original code
32 * Copyright (C) 2004 Xilinx, Inc.
33 *
34 * This program is free software; you can redistribute it and/or modify it
35 * under the terms of the GNU General Public License version 2 as published
36 * by the Free Software Foundation.
37 */
38
39/*
40 * Here are the handlers which don't require enabling translation
41 * and calling other kernel code thus we can keep their design very simple
42 * and do all processing in real mode. All what they need is a valid current
43 * (that is an issue for the CONFIG_REGISTER_TASK_PTR case)
44 * This handlers use r3,r4,r5,r6 and optionally r[current] to work therefore
45 * these registers are saved/restored
46 * The handlers which require translation are in entry.S --KAA
47 *
48 * Microblaze HW Exception Handler
49 * - Non self-modifying exception handler for the following exception conditions
50 * - Unalignment
51 * - Instruction bus error
52 * - Data bus error
53 * - Illegal instruction opcode
54 * - Divide-by-zero
55 *
7db29dde
MS		 56 * - Privileged instruction exception (MMU)
57 * - Data storage exception (MMU)
58 * - Instruction storage exception (MMU)
59 * - Data TLB miss exception (MMU)
60 * - Instruction TLB miss exception (MMU)
61 *
c4df4bc1
MS		 62 * Note we disable interrupts during exception handling, otherwise we will
63 * possibly get multiple re-entrancy if interrupt handles themselves cause
64 * exceptions. JW
65 */
66
67#include <asm/exceptions.h>
68#include <asm/unistd.h>
69#include <asm/page.h>
70
71#include <asm/entry.h>
72#include <asm/current.h>
73#include <linux/linkage.h>
74
75#include <asm/mmu.h>
76#include <asm/pgtable.h>
3863dbce 77#include <asm/signal.h>
c4df4bc1
MS		 78#include <asm/asm-offsets.h>
79
80/* Helpful Macros */
7db29dde 81#ifndef CONFIG_MMU
c4df4bc1 82#define EX_HANDLER_STACK_SIZ (4*19)
7db29dde 83#endif
c4df4bc1
MS		 84#define NUM_TO_REG(num) r ## num
85
7db29dde 86#ifdef CONFIG_MMU
7db29dde 87 #define RESTORE_STATE \
ac854ff1
MS		 88 lwi r5, r1, 0; \
89 mts rmsr, r5; \
90 nop; \
7db29dde
MS		 91 lwi r3, r1, PT_R3; \
92 lwi r4, r1, PT_R4; \
93 lwi r5, r1, PT_R5; \
94 lwi r6, r1, PT_R6; \
95 lwi r11, r1, PT_R11; \
96 lwi r31, r1, PT_R31; \
97 lwi r1, r0, TOPHYS(r0_ram + 0);
98#endif /* CONFIG_MMU */
99
c4df4bc1
MS		 100#define LWREG_NOP \
101 bri ex_handler_unhandled; \
102 nop;
103
104#define SWREG_NOP \
105 bri ex_handler_unhandled; \
106 nop;
107
108/* FIXME this is weird - for noMMU kernel is not possible to use brid
109 * instruction which can shorten executed time
110 */
111
112/* r3 is the source */
113#define R3_TO_LWREG_V(regnum) \
114 swi r3, r1, 4 * regnum; \
115 bri ex_handler_done;
116
117/* r3 is the source */
118#define R3_TO_LWREG(regnum) \
119 or NUM_TO_REG (regnum), r0, r3; \
120 bri ex_handler_done;
121
122/* r3 is the target */
123#define SWREG_TO_R3_V(regnum) \
124 lwi r3, r1, 4 * regnum; \
125 bri ex_sw_tail;
126
127/* r3 is the target */
128#define SWREG_TO_R3(regnum) \
129 or r3, r0, NUM_TO_REG (regnum); \
130 bri ex_sw_tail;
131
7db29dde
MS		 132#ifdef CONFIG_MMU
133 #define R3_TO_LWREG_VM_V(regnum) \
134 brid ex_lw_end_vm; \
135 swi r3, r7, 4 * regnum;
136
137 #define R3_TO_LWREG_VM(regnum) \
138 brid ex_lw_end_vm; \
139 or NUM_TO_REG (regnum), r0, r3;
140
141 #define SWREG_TO_R3_VM_V(regnum) \
142 brid ex_sw_tail_vm; \
143 lwi r3, r7, 4 * regnum;
144
145 #define SWREG_TO_R3_VM(regnum) \
146 brid ex_sw_tail_vm; \
147 or r3, r0, NUM_TO_REG (regnum);
148
149 /* Shift right instruction depending on available configuration */
150 #if CONFIG_XILINX_MICROBLAZE0_USE_BARREL > 0
151 #define BSRLI(rD, rA, imm) \
152 bsrli rD, rA, imm
153 #elif CONFIG_XILINX_MICROBLAZE0_USE_DIV > 0
154 #define BSRLI(rD, rA, imm) \
155 ori rD, r0, (1 << imm); \
156 idivu rD, rD, rA
157 #else
158 #define BSRLI(rD, rA, imm) BSRLI ## imm (rD, rA)
159 /* Only the used shift constants defined here - add more if needed */
160 #define BSRLI2(rD, rA) \
161 srl rD, rA; /* << 1 */ \
162 srl rD, rD; /* << 2 */
163 #define BSRLI10(rD, rA) \
164 srl rD, rA; /* << 1 */ \
165 srl rD, rD; /* << 2 */ \
166 srl rD, rD; /* << 3 */ \
167 srl rD, rD; /* << 4 */ \
168 srl rD, rD; /* << 5 */ \
169 srl rD, rD; /* << 6 */ \
170 srl rD, rD; /* << 7 */ \
171 srl rD, rD; /* << 8 */ \
172 srl rD, rD; /* << 9 */ \
173 srl rD, rD /* << 10 */
174 #define BSRLI20(rD, rA) \
175 BSRLI10(rD, rA); \
176 BSRLI10(rD, rD)
177 #endif
178#endif /* CONFIG_MMU */
179
c4df4bc1
MS		 180.extern other_exception_handler /* Defined in exception.c */
181
182/*
183 * hw_exception_handler - Handler for exceptions
184 *
185 * Exception handler notes:
186 * - Handles all exceptions
187 * - Does not handle unaligned exceptions during load into r17, r1, r0.
188 * - Does not handle unaligned exceptions during store from r17 (cannot be
189 * done) and r1 (slows down common case)
190 *
191 * Relevant register structures
192 *
193 * EAR - |----|----|----|----|----|----|----|----|
194 * - < ## 32 bit faulting address ## >
195 *
196 * ESR - |----|----|----|----|----| - | - |-----|-----|
197 * - W S REG EXC
198 *
199 *
200 * STACK FRAME STRUCTURE (for NO_MMU)
201 * ---------------------------------
202 *
203 * +-------------+ + 0
204 * | MSR |
205 * +-------------+ + 4
206 * | r1 |
207 * | . |
208 * | . |
209 * | . |
210 * | . |
211 * | r18 |
212 * +-------------+ + 76
213 * | . |
214 * | . |
215 *
216 * NO_MMU kernel use the same r0_ram pointed space - look to vmlinux.lds.S
217 * which is used for storing register values - old style was, that value were
218 * stored in stack but in case of failure you lost information about register.
219 * Currently you can see register value in memory in specific place.
220 * In compare to with previous solution the speed should be the same.
221 *
222 * MMU exception handler has different handling compare to no MMU kernel.
223 * Exception handler use jump table for directing of what happen. For MMU kernel
224 * is this approach better because MMU relate exception are handled by asm code
225 * in this file. In compare to with MMU expect of unaligned exception
226 * is everything handled by C code.
227 */
228
229/*
230 * every of these handlers is entered having R3/4/5/6/11/current saved on stack
231 * and clobbered so care should be taken to restore them if someone is going to
232 * return from exception
233 */
234
235/* wrappers to restore state before coming to entry.S */
236
7db29dde
MS		 237#ifdef CONFIG_MMU
238.section .rodata
239.align 4
240_MB_HW_ExceptionVectorTable:
241/* 0 - Undefined */
242 .long TOPHYS(ex_handler_unhandled)
243/* 1 - Unaligned data access exception */
244 .long TOPHYS(handle_unaligned_ex)
245/* 2 - Illegal op-code exception */
246 .long TOPHYS(full_exception_trapw)
247/* 3 - Instruction bus error exception */
248 .long TOPHYS(full_exception_trapw)
249/* 4 - Data bus error exception */
250 .long TOPHYS(full_exception_trapw)
251/* 5 - Divide by zero exception */
252 .long TOPHYS(full_exception_trapw)
253/* 6 - Floating point unit exception */
254 .long TOPHYS(full_exception_trapw)
255/* 7 - Privileged instruction exception */
256 .long TOPHYS(full_exception_trapw)
257/* 8 - 15 - Undefined */
258 .long TOPHYS(ex_handler_unhandled)
259 .long TOPHYS(ex_handler_unhandled)
260 .long TOPHYS(ex_handler_unhandled)
261 .long TOPHYS(ex_handler_unhandled)
262 .long TOPHYS(ex_handler_unhandled)
263 .long TOPHYS(ex_handler_unhandled)
264 .long TOPHYS(ex_handler_unhandled)
265 .long TOPHYS(ex_handler_unhandled)
266/* 16 - Data storage exception */
267 .long TOPHYS(handle_data_storage_exception)
268/* 17 - Instruction storage exception */
269 .long TOPHYS(handle_instruction_storage_exception)
270/* 18 - Data TLB miss exception */
271 .long TOPHYS(handle_data_tlb_miss_exception)
272/* 19 - Instruction TLB miss exception */
273 .long TOPHYS(handle_instruction_tlb_miss_exception)
274/* 20 - 31 - Undefined */
275 .long TOPHYS(ex_handler_unhandled)
276 .long TOPHYS(ex_handler_unhandled)
277 .long TOPHYS(ex_handler_unhandled)
278 .long TOPHYS(ex_handler_unhandled)
279 .long TOPHYS(ex_handler_unhandled)
280 .long TOPHYS(ex_handler_unhandled)
281 .long TOPHYS(ex_handler_unhandled)
282 .long TOPHYS(ex_handler_unhandled)
283 .long TOPHYS(ex_handler_unhandled)
284 .long TOPHYS(ex_handler_unhandled)
285 .long TOPHYS(ex_handler_unhandled)
286 .long TOPHYS(ex_handler_unhandled)
287#endif
288
c4df4bc1
MS		 289.global _hw_exception_handler
290.section .text
291.align 4
292.ent _hw_exception_handler
293_hw_exception_handler:
7db29dde 294#ifndef CONFIG_MMU
c4df4bc1 295 addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */
7db29dde
MS		 296#else
297 swi r1, r0, TOPHYS(r0_ram + 0); /* GET_SP */
298 /* Save date to kernel memory. Here is the problem
299 * when you came from user space */
300 ori r1, r0, TOPHYS(r0_ram + 28);
301#endif
c4df4bc1
MS		 302 swi r3, r1, PT_R3
303 swi r4, r1, PT_R4
304 swi r5, r1, PT_R5
305 swi r6, r1, PT_R6
306
7db29dde
MS		 307#ifdef CONFIG_MMU
308 swi r11, r1, PT_R11
309 swi r31, r1, PT_R31
310 lwi r31, r0, TOPHYS(PER_CPU(CURRENT_SAVE)) /* get saved current */
311#endif
312
ac854ff1
MS		 313 mfs r5, rmsr;
314 nop
315 swi r5, r1, 0;
c4df4bc1
MS		 316 mfs r3, resr
317 nop
7db29dde
MS		 318 mfs r4, rear;
319 nop
c4df4bc1 320
7db29dde 321#ifndef CONFIG_MMU
c4df4bc1
MS		 322 andi r5, r3, 0x1000; /* Check ESR[DS] */
323 beqi r5, not_in_delay_slot; /* Branch if ESR[DS] not set */
324 mfs r17, rbtr; /* ESR[DS] set - return address in BTR */
325 nop
326not_in_delay_slot:
327 swi r17, r1, PT_R17
7db29dde 328#endif
c4df4bc1
MS		 329
330 andi r5, r3, 0x1F; /* Extract ESR[EXC] */
331
7db29dde
MS		 332#ifdef CONFIG_MMU
333 /* Calculate exception vector offset = r5 << 2 */
334 addk r6, r5, r5; /* << 1 */
335 addk r6, r6, r6; /* << 2 */
336
708e7153 337#ifdef DEBUG
7db29dde
MS		 338/* counting which exception happen */
339 lwi r5, r0, 0x200 + TOPHYS(r0_ram)
340 addi r5, r5, 1
341 swi r5, r0, 0x200 + TOPHYS(r0_ram)
342 lwi r5, r6, 0x200 + TOPHYS(r0_ram)
343 addi r5, r5, 1
344 swi r5, r6, 0x200 + TOPHYS(r0_ram)
708e7153 345#endif
7db29dde
MS		 346/* end */
347 /* Load the HW Exception vector */
348 lwi r6, r6, TOPHYS(_MB_HW_ExceptionVectorTable)
349 bra r6
350
351full_exception_trapw:
352 RESTORE_STATE
353 bri full_exception_trap
354#else
c4df4bc1
MS		 355 /* Exceptions enabled here. This will allow nested exceptions */
356 mfs r6, rmsr;
357 nop
358 swi r6, r1, 0; /* RMSR_OFFSET */
359 ori r6, r6, 0x100; /* Turn ON the EE bit */
360 andi r6, r6, ~2; /* Disable interrupts */
361 mts rmsr, r6;
362 nop
363
364 xori r6, r5, 1; /* 00001 = Unaligned Exception */
365 /* Jump to unalignment exception handler */
366 beqi r6, handle_unaligned_ex;
367
368handle_other_ex: /* Handle Other exceptions here */
369 /* Save other volatiles before we make procedure calls below */
370 swi r7, r1, PT_R7
371 swi r8, r1, PT_R8
372 swi r9, r1, PT_R9
373 swi r10, r1, PT_R10
374 swi r11, r1, PT_R11
375 swi r12, r1, PT_R12
376 swi r14, r1, PT_R14
377 swi r15, r1, PT_R15
378 swi r18, r1, PT_R18
379
380 or r5, r1, r0
381 andi r6, r3, 0x1F; /* Load ESR[EC] */
382 lwi r7, r0, PER_CPU(KM) /* MS: saving current kernel mode to regs */
383 swi r7, r1, PT_MODE
384 mfs r7, rfsr
385 nop
386 addk r8, r17, r0; /* Load exception address */
387 bralid r15, full_exception; /* Branch to the handler */
388 nop;
131e4e97 389 mts rfsr, r0; /* Clear sticky fsr */
71b23d54 390 nop
c4df4bc1
MS		 391
392 /*
393 * Trigger execution of the signal handler by enabling
394 * interrupts and calling an invalid syscall.
395 */
396 mfs r5, rmsr;
397 nop
398 ori r5, r5, 2;
399 mts rmsr, r5; /* enable interrupt */
400 nop
401 addi r12, r0, __NR_syscalls;
402 brki r14, 0x08;
403 mfs r5, rmsr; /* disable interrupt */
404 nop
405 andi r5, r5, ~2;
406 mts rmsr, r5;
407 nop
408
409 lwi r7, r1, PT_R7
410 lwi r8, r1, PT_R8
411 lwi r9, r1, PT_R9
412 lwi r10, r1, PT_R10
413 lwi r11, r1, PT_R11
414 lwi r12, r1, PT_R12
415 lwi r14, r1, PT_R14
416 lwi r15, r1, PT_R15
417 lwi r18, r1, PT_R18
418
419 bri ex_handler_done; /* Complete exception handling */
7db29dde 420#endif
c4df4bc1
MS		 421
422/* 0x01 - Unaligned data access exception
423 * This occurs when a word access is not aligned on a word boundary,
424 * or when a 16-bit access is not aligned on a 16-bit boundary.
425 * This handler perform the access, and returns, except for MMU when
426 * the unaligned address is last on a 4k page or the physical address is
427 * not found in the page table, in which case unaligned_data_trap is called.
428 */
429handle_unaligned_ex:
430 /* Working registers already saved: R3, R4, R5, R6
431 * R3 = ESR
7db29dde 432 * R4 = EAR
c4df4bc1 433 */
7db29dde
MS		 434#ifdef CONFIG_MMU
435 andi r6, r3, 0x1000 /* Check ESR[DS] */
436 beqi r6, _no_delayslot /* Branch if ESR[DS] not set */
437 mfs r17, rbtr; /* ESR[DS] set - return address in BTR */
c4df4bc1 438 nop
7db29dde 439_no_delayslot:
3863dbce
MS		 440 /* jump to high level unaligned handler */
441 RESTORE_STATE;
442 bri unaligned_data_trap
7db29dde 443#endif
c4df4bc1
MS		 444 andi r6, r3, 0x3E0; /* Mask and extract the register operand */
445 srl r6, r6; /* r6 >> 5 */
446 srl r6, r6;
447 srl r6, r6;
448 srl r6, r6;
449 srl r6, r6;
450 /* Store the register operand in a temporary location */
451 sbi r6, r0, TOPHYS(ex_reg_op);
452
453 andi r6, r3, 0x400; /* Extract ESR[S] */
454 bnei r6, ex_sw;
455ex_lw:
456 andi r6, r3, 0x800; /* Extract ESR[W] */
457 beqi r6, ex_lhw;
458 lbui r5, r4, 0; /* Exception address in r4 */
459 /* Load a word, byte-by-byte from destination address
460 and save it in tmp space */
461 sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
462 lbui r5, r4, 1;
463 sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
464 lbui r5, r4, 2;
465 sbi r5, r0, TOPHYS(ex_tmp_data_loc_2);
466 lbui r5, r4, 3;
467 sbi r5, r0, TOPHYS(ex_tmp_data_loc_3);
468 /* Get the destination register value into r3 */
469 lwi r3, r0, TOPHYS(ex_tmp_data_loc_0);
470 bri ex_lw_tail;
471ex_lhw:
472 lbui r5, r4, 0; /* Exception address in r4 */
473 /* Load a half-word, byte-by-byte from destination
474 address and save it in tmp space */
475 sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
476 lbui r5, r4, 1;
477 sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
478 /* Get the destination register value into r3 */
479 lhui r3, r0, TOPHYS(ex_tmp_data_loc_0);
480ex_lw_tail:
481 /* Get the destination register number into r5 */
482 lbui r5, r0, TOPHYS(ex_reg_op);
483 /* Form load_word jump table offset (lw_table + (8 * regnum)) */
484 la r6, r0, TOPHYS(lw_table);
485 addk r5, r5, r5;
486 addk r5, r5, r5;
487 addk r5, r5, r5;
488 addk r5, r5, r6;
489 bra r5;
490ex_lw_end: /* Exception handling of load word, ends */
491ex_sw:
492 /* Get the destination register number into r5 */
493 lbui r5, r0, TOPHYS(ex_reg_op);
494 /* Form store_word jump table offset (sw_table + (8 * regnum)) */
495 la r6, r0, TOPHYS(sw_table);
496 add r5, r5, r5;
497 add r5, r5, r5;
498 add r5, r5, r5;
499 add r5, r5, r6;
500 bra r5;
501ex_sw_tail:
502 mfs r6, resr;
503 nop
504 andi r6, r6, 0x800; /* Extract ESR[W] */
505 beqi r6, ex_shw;
506 /* Get the word - delay slot */
507 swi r3, r0, TOPHYS(ex_tmp_data_loc_0);
508 /* Store the word, byte-by-byte into destination address */
509 lbui r3, r0, TOPHYS(ex_tmp_data_loc_0);
510 sbi r3, r4, 0;
511 lbui r3, r0, TOPHYS(ex_tmp_data_loc_1);
512 sbi r3, r4, 1;
513 lbui r3, r0, TOPHYS(ex_tmp_data_loc_2);
514 sbi r3, r4, 2;
515 lbui r3, r0, TOPHYS(ex_tmp_data_loc_3);
516 sbi r3, r4, 3;
517 bri ex_handler_done;
518
519ex_shw:
520 /* Store the lower half-word, byte-by-byte into destination address */
521 swi r3, r0, TOPHYS(ex_tmp_data_loc_0);
522 lbui r3, r0, TOPHYS(ex_tmp_data_loc_2);
523 sbi r3, r4, 0;
524 lbui r3, r0, TOPHYS(ex_tmp_data_loc_3);
525 sbi r3, r4, 1;
526ex_sw_end: /* Exception handling of store word, ends. */
527
528ex_handler_done:
7db29dde 529#ifndef CONFIG_MMU
c4df4bc1
MS		 530 lwi r5, r1, 0 /* RMSR */
531 mts rmsr, r5
532 nop
533 lwi r3, r1, PT_R3
534 lwi r4, r1, PT_R4
535 lwi r5, r1, PT_R5
536 lwi r6, r1, PT_R6
537 lwi r17, r1, PT_R17
538
539 rted r17, 0
540 addik r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */
7db29dde
MS		 541#else
542 RESTORE_STATE;
543 rted r17, 0
544 nop
545#endif
546
547#ifdef CONFIG_MMU
548 /* Exception vector entry code. This code runs with address translation
549 * turned off (i.e. using physical addresses). */
550
551 /* Exception vectors. */
552
553 /* 0x10 - Data Storage Exception
554 * This happens for just a few reasons. U0 set (but we don't do that),
555 * or zone protection fault (user violation, write to protected page).
556 * If this is just an update of modified status, we do that quickly
557 * and exit. Otherwise, we call heavyweight functions to do the work.
558 */
559 handle_data_storage_exception:
560 /* Working registers already saved: R3, R4, R5, R6
561 * R3 = ESR
562 */
563 mfs r11, rpid
564 nop
7db29dde
MS		 565 mfs r3, rear /* Get faulting address */
566 nop
567 /* If we are faulting a kernel address, we have to use the
568 * kernel page tables.
569 */
570 ori r4, r0, CONFIG_KERNEL_START
571 cmpu r4, r3, r4
572 bgti r4, ex3
573 /* First, check if it was a zone fault (which means a user
574 * tried to access a kernel or read-protected page - always
575 * a SEGV). All other faults here must be stores, so no
576 * need to check ESR_S as well. */
577 mfs r4, resr
578 nop
579 andi r4, r4, 0x800 /* ESR_Z - zone protection */
580 bnei r4, ex2
581
582 ori r4, r0, swapper_pg_dir
583 mts rpid, r0 /* TLB will have 0 TID */
584 nop
585 bri ex4
586
587 /* Get the PGD for the current thread. */
588 ex3:
589 /* First, check if it was a zone fault (which means a user
590 * tried to access a kernel or read-protected page - always
591 * a SEGV). All other faults here must be stores, so no
592 * need to check ESR_S as well. */
593 mfs r4, resr
594 nop
595 andi r4, r4, 0x800 /* ESR_Z */
596 bnei r4, ex2
597 /* get current task address */
598 addi r4 ,CURRENT_TASK, TOPHYS(0);
599 lwi r4, r4, TASK_THREAD+PGDIR
600 ex4:
601 tophys(r4,r4)
602 BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */
603 andi r5, r5, 0xffc
604/* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
605 or r4, r4, r5
606 lwi r4, r4, 0 /* Get L1 entry */
607 andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
608 beqi r5, ex2 /* Bail if no table */
609
610 tophys(r5,r5)
611 BSRLI(r6,r3,10) /* Compute PTE address */
612 andi r6, r6, 0xffc
613 andi r5, r5, 0xfffff003
614 or r5, r5, r6
615 lwi r4, r5, 0 /* Get Linux PTE */
616
617 andi r6, r4, _PAGE_RW /* Is it writeable? */
618 beqi r6, ex2 /* Bail if not */
619
620 /* Update 'changed' */
621 ori r4, r4, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
622 swi r4, r5, 0 /* Update Linux page table */
623
624 /* Most of the Linux PTE is ready to load into the TLB LO.
625 * We set ZSEL, where only the LS-bit determines user access.
626 * We set execute, because we don't have the granularity to
627 * properly set this at the page level (Linux problem).
628 * If shared is set, we cause a zero PID->TID load.
629 * Many of these bits are software only. Bits we don't set
630 * here we (properly should) assume have the appropriate value.
631 */
632 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */
633 ori r4, r4, _PAGE_HWEXEC /* make it executable */
634
635 /* find the TLB index that caused the fault. It has to be here*/
636 mts rtlbsx, r3
637 nop
638 mfs r5, rtlbx /* DEBUG: TBD */
639 nop
640 mts rtlblo, r4 /* Load TLB LO */
641 nop
642 /* Will sync shadow TLBs */
643
644 /* Done...restore registers and get out of here. */
645 mts rpid, r11
646 nop
647 bri 4
648
649 RESTORE_STATE;
650 rted r17, 0
651 nop
652 ex2:
653 /* The bailout. Restore registers to pre-exception conditions
654 * and call the heavyweights to help us out. */
655 mts rpid, r11
656 nop
657 bri 4
658 RESTORE_STATE;
659 bri page_fault_data_trap
660
661
662 /* 0x11 - Instruction Storage Exception
663 * This is caused by a fetch from non-execute or guarded pages. */
664 handle_instruction_storage_exception:
665 /* Working registers already saved: R3, R4, R5, R6
666 * R3 = ESR
667 */
668
669 mfs r3, rear /* Get faulting address */
670 nop
671 RESTORE_STATE;
672 bri page_fault_instr_trap
673
674 /* 0x12 - Data TLB Miss Exception
675 * As the name implies, translation is not in the MMU, so search the
676 * page tables and fix it. The only purpose of this function is to
677 * load TLB entries from the page table if they exist.
678 */
679 handle_data_tlb_miss_exception:
680 /* Working registers already saved: R3, R4, R5, R6
7a6bbdc9 681 * R3 = EAR, R4 = ESR
7db29dde
MS		 682 */
683 mfs r11, rpid
684 nop
7db29dde
MS		 685 mfs r3, rear /* Get faulting address */
686 nop
687
688 /* If we are faulting a kernel address, we have to use the
689 * kernel page tables. */
7a6bbdc9
MS		 690 ori r6, r0, CONFIG_KERNEL_START
691 cmpu r4, r3, r6
7db29dde
MS		 692 bgti r4, ex5
693 ori r4, r0, swapper_pg_dir
694 mts rpid, r0 /* TLB will have 0 TID */
695 nop
696 bri ex6
c4df4bc1 697
7db29dde
MS		 698 /* Get the PGD for the current thread. */
699 ex5:
700 /* get current task address */
701 addi r4 ,CURRENT_TASK, TOPHYS(0);
702 lwi r4, r4, TASK_THREAD+PGDIR
703 ex6:
704 tophys(r4,r4)
705 BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */
706 andi r5, r5, 0xffc
707/* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
708 or r4, r4, r5
709 lwi r4, r4, 0 /* Get L1 entry */
710 andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
711 beqi r5, ex7 /* Bail if no table */
712
713 tophys(r5,r5)
714 BSRLI(r6,r3,10) /* Compute PTE address */
715 andi r6, r6, 0xffc
716 andi r5, r5, 0xfffff003
717 or r5, r5, r6
718 lwi r4, r5, 0 /* Get Linux PTE */
719
720 andi r6, r4, _PAGE_PRESENT
721 beqi r6, ex7
722
723 ori r4, r4, _PAGE_ACCESSED
724 swi r4, r5, 0
725
726 /* Most of the Linux PTE is ready to load into the TLB LO.
727 * We set ZSEL, where only the LS-bit determines user access.
728 * We set execute, because we don't have the granularity to
729 * properly set this at the page level (Linux problem).
730 * If shared is set, we cause a zero PID->TID load.
731 * Many of these bits are software only. Bits we don't set
732 * here we (properly should) assume have the appropriate value.
733 */
734 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */
735
736 bri finish_tlb_load
737 ex7:
738 /* The bailout. Restore registers to pre-exception conditions
739 * and call the heavyweights to help us out.
740 */
741 mts rpid, r11
742 nop
743 bri 4
744 RESTORE_STATE;
745 bri page_fault_data_trap
746
747 /* 0x13 - Instruction TLB Miss Exception
748 * Nearly the same as above, except we get our information from
749 * different registers and bailout to a different point.
750 */
751 handle_instruction_tlb_miss_exception:
752 /* Working registers already saved: R3, R4, R5, R6
753 * R3 = ESR
754 */
755 mfs r11, rpid
756 nop
7db29dde
MS		 757 mfs r3, rear /* Get faulting address */
758 nop
759
760 /* If we are faulting a kernel address, we have to use the
761 * kernel page tables.
762 */
763 ori r4, r0, CONFIG_KERNEL_START
764 cmpu r4, r3, r4
765 bgti r4, ex8
766 ori r4, r0, swapper_pg_dir
767 mts rpid, r0 /* TLB will have 0 TID */
768 nop
769 bri ex9
770
771 /* Get the PGD for the current thread. */
772 ex8:
773 /* get current task address */
774 addi r4 ,CURRENT_TASK, TOPHYS(0);
775 lwi r4, r4, TASK_THREAD+PGDIR
776 ex9:
777 tophys(r4,r4)
778 BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */
779 andi r5, r5, 0xffc
780/* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
781 or r4, r4, r5
782 lwi r4, r4, 0 /* Get L1 entry */
783 andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
784 beqi r5, ex10 /* Bail if no table */
785
786 tophys(r5,r5)
787 BSRLI(r6,r3,10) /* Compute PTE address */
788 andi r6, r6, 0xffc
789 andi r5, r5, 0xfffff003
790 or r5, r5, r6
791 lwi r4, r5, 0 /* Get Linux PTE */
792
793 andi r6, r4, _PAGE_PRESENT
794 beqi r6, ex7
795
796 ori r4, r4, _PAGE_ACCESSED
797 swi r4, r5, 0
798
799 /* Most of the Linux PTE is ready to load into the TLB LO.
800 * We set ZSEL, where only the LS-bit determines user access.
801 * We set execute, because we don't have the granularity to
802 * properly set this at the page level (Linux problem).
803 * If shared is set, we cause a zero PID->TID load.
804 * Many of these bits are software only. Bits we don't set
805 * here we (properly should) assume have the appropriate value.
806 */
807 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */
808
809 bri finish_tlb_load
810 ex10:
811 /* The bailout. Restore registers to pre-exception conditions
812 * and call the heavyweights to help us out.
813 */
814 mts rpid, r11
815 nop
816 bri 4
817 RESTORE_STATE;
818 bri page_fault_instr_trap
819
820/* Both the instruction and data TLB miss get to this point to load the TLB.
821 * r3 - EA of fault
822 * r4 - TLB LO (info from Linux PTE)
823 * r5, r6 - available to use
824 * PID - loaded with proper value when we get here
825 * Upon exit, we reload everything and RFI.
826 * A common place to load the TLB.
827 */
828 tlb_index:
829 .long 1 /* MS: storing last used tlb index */
830 finish_tlb_load:
831 /* MS: load the last used TLB index. */
832 lwi r5, r0, TOPHYS(tlb_index)
833 addik r5, r5, 1 /* MS: inc tlb_index -> use next one */
834
835/* MS: FIXME this is potential fault, because this is mask not count */
836 andi r5, r5, (MICROBLAZE_TLB_SIZE-1)
837 ori r6, r0, 1
838 cmp r31, r5, r6
839 blti r31, sem
840 addik r5, r6, 1
841 sem:
842 /* MS: save back current TLB index */
843 swi r5, r0, TOPHYS(tlb_index)
844
845 ori r4, r4, _PAGE_HWEXEC /* make it executable */
846 mts rtlbx, r5 /* MS: save current TLB */
847 nop
848 mts rtlblo, r4 /* MS: save to TLB LO */
849 nop
850
851 /* Create EPN. This is the faulting address plus a static
852 * set of bits. These are size, valid, E, U0, and ensure
853 * bits 20 and 21 are zero.
854 */
855 andi r3, r3, 0xfffff000
856 ori r3, r3, 0x0c0
857 mts rtlbhi, r3 /* Load TLB HI */
858 nop
859
860 /* Done...restore registers and get out of here. */
861 ex12:
862 mts rpid, r11
863 nop
864 bri 4
865 RESTORE_STATE;
866 rted r17, 0
867 nop
868
869 /* extern void giveup_fpu(struct task_struct *prev)
870 *
871 * The MicroBlaze processor may have an FPU, so this should not just
872 * return: TBD.
873 */
874 .globl giveup_fpu;
875 .align 4;
876 giveup_fpu:
877 bralid r15,0 /* TBD */
878 nop
879
880 /* At present, this routine just hangs. - extern void abort(void) */
881 .globl abort;
882 .align 4;
883 abort:
884 br r0
885
886 .globl set_context;
887 .align 4;
888 set_context:
889 mts rpid, r5 /* Shadow TLBs are automatically */
890 nop
891 bri 4 /* flushed by changing PID */
892 rtsd r15,8
893 nop
894
895#endif
c4df4bc1
MS		 896.end _hw_exception_handler
897
7db29dde
MS		 898#ifdef CONFIG_MMU
899/* Unaligned data access exception last on a 4k page for MMU.
900 * When this is called, we are in virtual mode with exceptions enabled
901 * and registers 1-13,15,17,18 saved.
902 *
903 * R3 = ESR
904 * R4 = EAR
905 * R7 = pointer to saved registers (struct pt_regs *regs)
906 *
907 * This handler perform the access, and returns via ret_from_exc.
908 */
909.global _unaligned_data_exception
910.ent _unaligned_data_exception
911_unaligned_data_exception:
912 andi r8, r3, 0x3E0; /* Mask and extract the register operand */
913 BSRLI(r8,r8,2); /* r8 >> 2 = register operand * 8 */
914 andi r6, r3, 0x400; /* Extract ESR[S] */
915 bneid r6, ex_sw_vm;
916 andi r6, r3, 0x800; /* Extract ESR[W] - delay slot */
917ex_lw_vm:
918 beqid r6, ex_lhw_vm;
3863dbce 919load1: lbui r5, r4, 0; /* Exception address in r4 - delay slot */
7db29dde
MS		 920/* Load a word, byte-by-byte from destination address and save it in tmp space*/
921 la r6, r0, ex_tmp_data_loc_0;
922 sbi r5, r6, 0;
3863dbce 923load2: lbui r5, r4, 1;
7db29dde 924 sbi r5, r6, 1;
3863dbce 925load3: lbui r5, r4, 2;
7db29dde 926 sbi r5, r6, 2;
3863dbce 927load4: lbui r5, r4, 3;
7db29dde
MS		 928 sbi r5, r6, 3;
929 brid ex_lw_tail_vm;
930/* Get the destination register value into r3 - delay slot */
931 lwi r3, r6, 0;
932ex_lhw_vm:
933 /* Load a half-word, byte-by-byte from destination address and
934 * save it in tmp space */
935 la r6, r0, ex_tmp_data_loc_0;
936 sbi r5, r6, 0;
3863dbce 937load5: lbui r5, r4, 1;
7db29dde
MS		 938 sbi r5, r6, 1;
939 lhui r3, r6, 0; /* Get the destination register value into r3 */
940ex_lw_tail_vm:
941 /* Form load_word jump table offset (lw_table_vm + (8 * regnum)) */
942 addik r5, r8, lw_table_vm;
943 bra r5;
944ex_lw_end_vm: /* Exception handling of load word, ends */
945 brai ret_from_exc;
946ex_sw_vm:
947/* Form store_word jump table offset (sw_table_vm + (8 * regnum)) */
948 addik r5, r8, sw_table_vm;
949 bra r5;
950ex_sw_tail_vm:
951 la r5, r0, ex_tmp_data_loc_0;
952 beqid r6, ex_shw_vm;
953 swi r3, r5, 0; /* Get the word - delay slot */
954 /* Store the word, byte-by-byte into destination address */
955 lbui r3, r5, 0;
3863dbce 956store1: sbi r3, r4, 0;
7db29dde 957 lbui r3, r5, 1;
3863dbce 958store2: sbi r3, r4, 1;
7db29dde 959 lbui r3, r5, 2;
3863dbce 960store3: sbi r3, r4, 2;
7db29dde
MS		 961 lbui r3, r5, 3;
962 brid ret_from_exc;
3863dbce 963store4: sbi r3, r4, 3; /* Delay slot */
7db29dde
MS		 964ex_shw_vm:
965 /* Store the lower half-word, byte-by-byte into destination address */
966 lbui r3, r5, 2;
3863dbce 967store5: sbi r3, r4, 0;
7db29dde
MS		 968 lbui r3, r5, 3;
969 brid ret_from_exc;
3863dbce 970store6: sbi r3, r4, 1; /* Delay slot */
7db29dde 971ex_sw_end_vm: /* Exception handling of store word, ends. */
3863dbce
MS		 972
973/* We have to prevent cases that get/put_user macros get unaligned pointer
974 * to bad page area. We have to find out which origin instruction caused it
975 * and called fixup for that origin instruction not instruction in unaligned
976 * handler */
977ex_unaligned_fixup:
978 ori r5, r7, 0 /* setup pointer to pt_regs */
979 lwi r6, r7, PT_PC; /* faulting address is one instruction above */
980 addik r6, r6, -4 /* for finding proper fixup */
981 swi r6, r7, PT_PC; /* a save back it to PT_PC */
982 addik r7, r0, SIGSEGV
983 /* call bad_page_fault for finding aligned fixup, fixup address is saved
984 * in PT_PC which is used as return address from exception */
985 la r15, r0, ret_from_exc-8 /* setup return address */
986 brid bad_page_fault
987 nop
988
989/* We prevent all load/store because it could failed any attempt to access */
990.section __ex_table,"a";
991 .word load1,ex_unaligned_fixup;
992 .word load2,ex_unaligned_fixup;
993 .word load3,ex_unaligned_fixup;
994 .word load4,ex_unaligned_fixup;
995 .word load5,ex_unaligned_fixup;
996 .word store1,ex_unaligned_fixup;
997 .word store2,ex_unaligned_fixup;
998 .word store3,ex_unaligned_fixup;
999 .word store4,ex_unaligned_fixup;
1000 .word store5,ex_unaligned_fixup;
1001 .word store6,ex_unaligned_fixup;
1002.previous;
7db29dde
MS		 1003.end _unaligned_data_exception
1004#endif /* CONFIG_MMU */
1005
c4df4bc1
MS		 1006ex_handler_unhandled:
1007/* FIXME add handle function for unhandled exception - dump register */
1008 bri 0
1009
7db29dde
MS		 1010/*
1011 * hw_exception_handler Jump Table
1012 * - Contains code snippets for each register that caused the unalign exception
1013 * - Hence exception handler is NOT self-modifying
1014 * - Separate table for load exceptions and store exceptions.
1015 * - Each table is of size: (8 * 32) = 256 bytes
1016 */
1017
c4df4bc1
MS		 1018.section .text
1019.align 4
1020lw_table:
1021lw_r0: R3_TO_LWREG (0);
1022lw_r1: LWREG_NOP;
1023lw_r2: R3_TO_LWREG (2);
1024lw_r3: R3_TO_LWREG_V (3);
1025lw_r4: R3_TO_LWREG_V (4);
1026lw_r5: R3_TO_LWREG_V (5);
1027lw_r6: R3_TO_LWREG_V (6);
1028lw_r7: R3_TO_LWREG (7);
1029lw_r8: R3_TO_LWREG (8);
1030lw_r9: R3_TO_LWREG (9);
1031lw_r10: R3_TO_LWREG (10);
1032lw_r11: R3_TO_LWREG (11);
1033lw_r12: R3_TO_LWREG (12);
1034lw_r13: R3_TO_LWREG (13);
1035lw_r14: R3_TO_LWREG (14);
1036lw_r15: R3_TO_LWREG (15);
1037lw_r16: R3_TO_LWREG (16);
1038lw_r17: LWREG_NOP;
1039lw_r18: R3_TO_LWREG (18);
1040lw_r19: R3_TO_LWREG (19);
1041lw_r20: R3_TO_LWREG (20);
1042lw_r21: R3_TO_LWREG (21);
1043lw_r22: R3_TO_LWREG (22);
1044lw_r23: R3_TO_LWREG (23);
1045lw_r24: R3_TO_LWREG (24);
1046lw_r25: R3_TO_LWREG (25);
1047lw_r26: R3_TO_LWREG (26);
1048lw_r27: R3_TO_LWREG (27);
1049lw_r28: R3_TO_LWREG (28);
1050lw_r29: R3_TO_LWREG (29);
1051lw_r30: R3_TO_LWREG (30);
7db29dde
MS		 1052#ifdef CONFIG_MMU
1053lw_r31: R3_TO_LWREG_V (31);
1054#else
c4df4bc1 1055lw_r31: R3_TO_LWREG (31);
7db29dde 1056#endif
c4df4bc1
MS		 1057
1058sw_table:
1059sw_r0: SWREG_TO_R3 (0);
1060sw_r1: SWREG_NOP;
1061sw_r2: SWREG_TO_R3 (2);
1062sw_r3: SWREG_TO_R3_V (3);
1063sw_r4: SWREG_TO_R3_V (4);
1064sw_r5: SWREG_TO_R3_V (5);
1065sw_r6: SWREG_TO_R3_V (6);
1066sw_r7: SWREG_TO_R3 (7);
1067sw_r8: SWREG_TO_R3 (8);
1068sw_r9: SWREG_TO_R3 (9);
1069sw_r10: SWREG_TO_R3 (10);
1070sw_r11: SWREG_TO_R3 (11);
1071sw_r12: SWREG_TO_R3 (12);
1072sw_r13: SWREG_TO_R3 (13);
1073sw_r14: SWREG_TO_R3 (14);
1074sw_r15: SWREG_TO_R3 (15);
1075sw_r16: SWREG_TO_R3 (16);
1076sw_r17: SWREG_NOP;
1077sw_r18: SWREG_TO_R3 (18);
1078sw_r19: SWREG_TO_R3 (19);
1079sw_r20: SWREG_TO_R3 (20);
1080sw_r21: SWREG_TO_R3 (21);
1081sw_r22: SWREG_TO_R3 (22);
1082sw_r23: SWREG_TO_R3 (23);
1083sw_r24: SWREG_TO_R3 (24);
1084sw_r25: SWREG_TO_R3 (25);
1085sw_r26: SWREG_TO_R3 (26);
1086sw_r27: SWREG_TO_R3 (27);
1087sw_r28: SWREG_TO_R3 (28);
1088sw_r29: SWREG_TO_R3 (29);
1089sw_r30: SWREG_TO_R3 (30);
7db29dde
MS		 1090#ifdef CONFIG_MMU
1091sw_r31: SWREG_TO_R3_V (31);
1092#else
c4df4bc1 1093sw_r31: SWREG_TO_R3 (31);
7db29dde
MS		 1094#endif
1095
1096#ifdef CONFIG_MMU
1097lw_table_vm:
1098lw_r0_vm: R3_TO_LWREG_VM (0);
1099lw_r1_vm: R3_TO_LWREG_VM_V (1);
1100lw_r2_vm: R3_TO_LWREG_VM_V (2);
1101lw_r3_vm: R3_TO_LWREG_VM_V (3);
1102lw_r4_vm: R3_TO_LWREG_VM_V (4);
1103lw_r5_vm: R3_TO_LWREG_VM_V (5);
1104lw_r6_vm: R3_TO_LWREG_VM_V (6);
1105lw_r7_vm: R3_TO_LWREG_VM_V (7);
1106lw_r8_vm: R3_TO_LWREG_VM_V (8);
1107lw_r9_vm: R3_TO_LWREG_VM_V (9);
1108lw_r10_vm: R3_TO_LWREG_VM_V (10);
1109lw_r11_vm: R3_TO_LWREG_VM_V (11);
1110lw_r12_vm: R3_TO_LWREG_VM_V (12);
1111lw_r13_vm: R3_TO_LWREG_VM_V (13);
1112lw_r14_vm: R3_TO_LWREG_VM (14);
1113lw_r15_vm: R3_TO_LWREG_VM_V (15);
1114lw_r16_vm: R3_TO_LWREG_VM (16);
1115lw_r17_vm: R3_TO_LWREG_VM_V (17);
1116lw_r18_vm: R3_TO_LWREG_VM_V (18);
1117lw_r19_vm: R3_TO_LWREG_VM (19);
1118lw_r20_vm: R3_TO_LWREG_VM (20);
1119lw_r21_vm: R3_TO_LWREG_VM (21);
1120lw_r22_vm: R3_TO_LWREG_VM (22);
1121lw_r23_vm: R3_TO_LWREG_VM (23);
1122lw_r24_vm: R3_TO_LWREG_VM (24);
1123lw_r25_vm: R3_TO_LWREG_VM (25);
1124lw_r26_vm: R3_TO_LWREG_VM (26);
1125lw_r27_vm: R3_TO_LWREG_VM (27);
1126lw_r28_vm: R3_TO_LWREG_VM (28);
1127lw_r29_vm: R3_TO_LWREG_VM (29);
1128lw_r30_vm: R3_TO_LWREG_VM (30);
1129lw_r31_vm: R3_TO_LWREG_VM_V (31);
1130
1131sw_table_vm:
1132sw_r0_vm: SWREG_TO_R3_VM (0);
1133sw_r1_vm: SWREG_TO_R3_VM_V (1);
1134sw_r2_vm: SWREG_TO_R3_VM_V (2);
1135sw_r3_vm: SWREG_TO_R3_VM_V (3);
1136sw_r4_vm: SWREG_TO_R3_VM_V (4);
1137sw_r5_vm: SWREG_TO_R3_VM_V (5);
1138sw_r6_vm: SWREG_TO_R3_VM_V (6);
1139sw_r7_vm: SWREG_TO_R3_VM_V (7);
1140sw_r8_vm: SWREG_TO_R3_VM_V (8);
1141sw_r9_vm: SWREG_TO_R3_VM_V (9);
1142sw_r10_vm: SWREG_TO_R3_VM_V (10);
1143sw_r11_vm: SWREG_TO_R3_VM_V (11);
1144sw_r12_vm: SWREG_TO_R3_VM_V (12);
1145sw_r13_vm: SWREG_TO_R3_VM_V (13);
1146sw_r14_vm: SWREG_TO_R3_VM (14);
1147sw_r15_vm: SWREG_TO_R3_VM_V (15);
1148sw_r16_vm: SWREG_TO_R3_VM (16);
1149sw_r17_vm: SWREG_TO_R3_VM_V (17);
1150sw_r18_vm: SWREG_TO_R3_VM_V (18);
1151sw_r19_vm: SWREG_TO_R3_VM (19);
1152sw_r20_vm: SWREG_TO_R3_VM (20);
1153sw_r21_vm: SWREG_TO_R3_VM (21);
1154sw_r22_vm: SWREG_TO_R3_VM (22);
1155sw_r23_vm: SWREG_TO_R3_VM (23);
1156sw_r24_vm: SWREG_TO_R3_VM (24);
1157sw_r25_vm: SWREG_TO_R3_VM (25);
1158sw_r26_vm: SWREG_TO_R3_VM (26);
1159sw_r27_vm: SWREG_TO_R3_VM (27);
1160sw_r28_vm: SWREG_TO_R3_VM (28);
1161sw_r29_vm: SWREG_TO_R3_VM (29);
1162sw_r30_vm: SWREG_TO_R3_VM (30);
1163sw_r31_vm: SWREG_TO_R3_VM_V (31);
1164#endif /* CONFIG_MMU */
c4df4bc1
MS		 1165
1166/* Temporary data structures used in the handler */
1167.section .data
1168.align 4
1169ex_tmp_data_loc_0:
1170 .byte 0
1171ex_tmp_data_loc_1:
1172 .byte 0
1173ex_tmp_data_loc_2:
1174 .byte 0
1175ex_tmp_data_loc_3:
1176 .byte 0
1177ex_reg_op:
1178 .byte 0
Linux kernel - Deliverables
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