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733cc218 MS |
1 | /* |
2 | * PCI support for Xilinx plbv46_pci soft-core which can be used on | |
3 | * Xilinx Virtex ML410 / ML510 boards. | |
4 | * | |
5 | * Copyright 2009 Roderick Colenbrander | |
6 | * Copyright 2009 Secret Lab Technologies Ltd. | |
7 | * | |
8 | * The pci bridge fixup code was copied from ppc4xx_pci.c and was written | |
9 | * by Benjamin Herrenschmidt. | |
10 | * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp. | |
11 | * | |
12 | * This file is licensed under the terms of the GNU General Public License | |
13 | * version 2. This program is licensed "as is" without any warranty of any | |
14 | * kind, whether express or implied. | |
15 | */ | |
16 | ||
17 | #include <linux/ioport.h> | |
18 | #include <linux/of.h> | |
19 | #include <linux/pci.h> | |
20 | #include <asm/io.h> | |
21 | ||
22 | #define XPLB_PCI_ADDR 0x10c | |
23 | #define XPLB_PCI_DATA 0x110 | |
24 | #define XPLB_PCI_BUS 0x114 | |
25 | ||
26 | #define PCI_HOST_ENABLE_CMD (PCI_COMMAND_SERR | PCI_COMMAND_PARITY | \ | |
27 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY) | |
28 | ||
29 | static struct of_device_id xilinx_pci_match[] = { | |
30 | { .compatible = "xlnx,plbv46-pci-1.03.a", }, | |
31 | {} | |
32 | }; | |
33 | ||
34 | /** | |
35 | * xilinx_pci_fixup_bridge - Block Xilinx PHB configuration. | |
36 | */ | |
37 | static void xilinx_pci_fixup_bridge(struct pci_dev *dev) | |
38 | { | |
39 | struct pci_controller *hose; | |
40 | int i; | |
41 | ||
42 | if (dev->devfn || dev->bus->self) | |
43 | return; | |
44 | ||
45 | hose = pci_bus_to_host(dev->bus); | |
46 | if (!hose) | |
47 | return; | |
48 | ||
49 | if (!of_match_node(xilinx_pci_match, hose->dn)) | |
50 | return; | |
51 | ||
52 | /* Hide the PCI host BARs from the kernel as their content doesn't | |
53 | * fit well in the resource management | |
54 | */ | |
55 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
56 | dev->resource[i].start = 0; | |
57 | dev->resource[i].end = 0; | |
58 | dev->resource[i].flags = 0; | |
59 | } | |
60 | ||
61 | dev_info(&dev->dev, "Hiding Xilinx plb-pci host bridge resources %s\n", | |
62 | pci_name(dev)); | |
63 | } | |
64 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, xilinx_pci_fixup_bridge); | |
65 | ||
66 | #ifdef DEBUG | |
67 | /** | |
68 | * xilinx_pci_exclude_device - Don't do config access for non-root bus | |
69 | * | |
70 | * This is a hack. Config access to any bus other than bus 0 does not | |
71 | * currently work on the ML510 so we prevent it here. | |
72 | */ | |
73 | static int | |
74 | xilinx_pci_exclude_device(struct pci_controller *hose, u_char bus, u8 devfn) | |
75 | { | |
76 | return (bus != 0); | |
77 | } | |
78 | ||
79 | /** | |
80 | * xilinx_early_pci_scan - List pci config space for available devices | |
81 | * | |
82 | * List pci devices in very early phase. | |
83 | */ | |
84 | void __init xilinx_early_pci_scan(struct pci_controller *hose) | |
85 | { | |
86 | u32 bus = 0; | |
87 | u32 val, dev, func, offset; | |
88 | ||
89 | /* Currently we have only 2 device connected - up-to 32 devices */ | |
90 | for (dev = 0; dev < 2; dev++) { | |
91 | /* List only first function number - up-to 8 functions */ | |
92 | for (func = 0; func < 1; func++) { | |
93 | printk(KERN_INFO "%02x:%02x:%02x", bus, dev, func); | |
94 | /* read the first 64 standardized bytes */ | |
95 | /* Up-to 192 bytes can be list of capabilities */ | |
96 | for (offset = 0; offset < 64; offset += 4) { | |
97 | early_read_config_dword(hose, bus, | |
98 | PCI_DEVFN(dev, func), offset, &val); | |
99 | if (offset == 0 && val == 0xFFFFFFFF) { | |
100 | printk(KERN_CONT "\nABSENT"); | |
101 | break; | |
102 | } | |
103 | if (!(offset % 0x10)) | |
104 | printk(KERN_CONT "\n%04x: ", offset); | |
105 | ||
106 | printk(KERN_CONT "%08x ", val); | |
107 | } | |
108 | printk(KERN_INFO "\n"); | |
109 | } | |
110 | } | |
111 | } | |
112 | #else | |
113 | void __init xilinx_early_pci_scan(struct pci_controller *hose) | |
114 | { | |
115 | } | |
116 | #endif | |
117 | ||
118 | /** | |
119 | * xilinx_pci_init - Find and register a Xilinx PCI host bridge | |
120 | */ | |
121 | void __init xilinx_pci_init(void) | |
122 | { | |
123 | struct pci_controller *hose; | |
124 | struct resource r; | |
125 | void __iomem *pci_reg; | |
126 | struct device_node *pci_node; | |
127 | ||
128 | pci_node = of_find_matching_node(NULL, xilinx_pci_match); | |
129 | if (!pci_node) | |
130 | return; | |
131 | ||
132 | if (of_address_to_resource(pci_node, 0, &r)) { | |
133 | pr_err("xilinx-pci: cannot resolve base address\n"); | |
134 | return; | |
135 | } | |
136 | ||
137 | hose = pcibios_alloc_controller(pci_node); | |
138 | if (!hose) { | |
139 | pr_err("xilinx-pci: pcibios_alloc_controller() failed\n"); | |
140 | return; | |
141 | } | |
142 | ||
143 | /* Setup config space */ | |
144 | setup_indirect_pci(hose, r.start + XPLB_PCI_ADDR, | |
145 | r.start + XPLB_PCI_DATA, | |
146 | INDIRECT_TYPE_SET_CFG_TYPE); | |
147 | ||
148 | /* According to the xilinx plbv46_pci documentation the soft-core starts | |
149 | * a self-init when the bus master enable bit is set. Without this bit | |
150 | * set the pci bus can't be scanned. | |
151 | */ | |
152 | early_write_config_word(hose, 0, 0, PCI_COMMAND, PCI_HOST_ENABLE_CMD); | |
153 | ||
154 | /* Set the max latency timer to 255 */ | |
155 | early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0xff); | |
156 | ||
157 | /* Set the max bus number to 255, and bus/subbus no's to 0 */ | |
158 | pci_reg = of_iomap(pci_node, 0); | |
159 | out_be32(pci_reg + XPLB_PCI_BUS, 0x000000ff); | |
160 | iounmap(pci_reg); | |
161 | ||
162 | /* Register the host bridge with the linux kernel! */ | |
163 | pci_process_bridge_OF_ranges(hose, pci_node, | |
164 | INDIRECT_TYPE_SET_CFG_TYPE); | |
165 | ||
166 | pr_info("xilinx-pci: Registered PCI host bridge\n"); | |
167 | xilinx_early_pci_scan(hose); | |
168 | } |