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MIPS: Alchemy: clock framework integration of onchip clocks
[deliverable/linux.git] / arch / mips / alchemy / common / clock.c
CommitLineData
47440229
ML		 1/*
2 * Alchemy clocks.
3 *
4 * Exposes all configurable internal clock sources to the clk framework.
5 *
6 * We have:
7 * - Root source, usually 12MHz supplied by an external crystal
8 * - 3 PLLs which generate multiples of root rate [AUX, CPU, AUX2]
9 *
10 * Dividers:
11 * - 6 clock dividers with:
12 * * selectable source [one of the PLLs],
13 * * output divided between [2 .. 512 in steps of 2] (!Au1300)
14 * or [1 .. 256 in steps of 1] (Au1300),
15 * * can be enabled individually.
16 *
17 * - up to 6 "internal" (fixed) consumers which:
18 * * take either AUXPLL or one of the above 6 dividers as input,
19 * * divide this input by 1, 2, or 4 (and 3 on Au1300).
20 * * can be disabled separately.
21 *
22 * Misc clocks:
23 * - sysbus clock: CPU core clock (CPUPLL) divided by 2, 3 or 4.
24 * depends on board design and should be set by bootloader, read-only.
25 * - peripheral clock: half the rate of sysbus clock, source for a lot
26 * of peripheral blocks, read-only.
27 * - memory clock: clk rate to main memory chips, depends on board
28 * design and is read-only,
29 * - lrclk: the static bus clock signal for synchronous operation.
30 * depends on board design, must be set by bootloader,
31 * but may be required to correctly configure devices attached to
32 * the static bus. The Au1000/1500/1100 manuals call it LCLK, on
33 * later models it's called RCLK.
34 */
35
36#include <linux/init.h>
37#include <linux/io.h>
38#include <linux/clk-provider.h>
39#include <linux/clkdev.h>
40#include <linux/clk-private.h>
41#include <linux/slab.h>
42#include <linux/spinlock.h>
43#include <linux/types.h>
44#include <asm/mach-au1x00/au1000.h>
45
46/* Base clock: 12MHz is the default in all databooks, and I haven't
47 * found any board yet which uses a different rate.
48 */
49#define ALCHEMY_ROOTCLK_RATE 12000000
50
51/*
52 * the internal sources which can be driven by the PLLs and dividers.
53 * Names taken from the databooks, refer to them for more information,
54 * especially which ones are share a clock line.
55 */
56static const char * const alchemy_au1300_intclknames[] = {
57 "lcd_intclk", "gpemgp_clk", "maempe_clk", "maebsa_clk",
58 "EXTCLK0", "EXTCLK1"
59};
60
61static const char * const alchemy_au1200_intclknames[] = {
62 "lcd_intclk", NULL, NULL, NULL, "EXTCLK0", "EXTCLK1"
63};
64
65static const char * const alchemy_au1550_intclknames[] = {
66 "usb_clk", "psc0_intclk", "psc1_intclk", "pci_clko",
67 "EXTCLK0", "EXTCLK1"
68};
69
70static const char * const alchemy_au1100_intclknames[] = {
71 "usb_clk", "lcd_intclk", NULL, "i2s_clk", "EXTCLK0", "EXTCLK1"
72};
73
74static const char * const alchemy_au1500_intclknames[] = {
75 NULL, "usbd_clk", "usbh_clk", "pci_clko", "EXTCLK0", "EXTCLK1"
76};
77
78static const char * const alchemy_au1000_intclknames[] = {
79 "irda_clk", "usbd_clk", "usbh_clk", "i2s_clk", "EXTCLK0",
80 "EXTCLK1"
81};
82
83/* aliases for a few on-chip sources which are either shared
84 * or have gone through name changes.
85 */
86static struct clk_aliastable {
87 char *alias;
88 char *base;
89 int cputype;
90} alchemy_clk_aliases[] __initdata = {
91 { "usbh_clk", "usb_clk", ALCHEMY_CPU_AU1100 },
92 { "usbd_clk", "usb_clk", ALCHEMY_CPU_AU1100 },
93 { "irda_clk", "usb_clk", ALCHEMY_CPU_AU1100 },
94 { "usbh_clk", "usb_clk", ALCHEMY_CPU_AU1550 },
95 { "usbd_clk", "usb_clk", ALCHEMY_CPU_AU1550 },
96 { "psc2_intclk", "usb_clk", ALCHEMY_CPU_AU1550 },
97 { "psc3_intclk", "EXTCLK0", ALCHEMY_CPU_AU1550 },
98 { "psc0_intclk", "EXTCLK0", ALCHEMY_CPU_AU1200 },
99 { "psc1_intclk", "EXTCLK1", ALCHEMY_CPU_AU1200 },
100 { "psc0_intclk", "EXTCLK0", ALCHEMY_CPU_AU1300 },
101 { "psc2_intclk", "EXTCLK0", ALCHEMY_CPU_AU1300 },
102 { "psc1_intclk", "EXTCLK1", ALCHEMY_CPU_AU1300 },
103 { "psc3_intclk", "EXTCLK1", ALCHEMY_CPU_AU1300 },
104
105 { NULL, NULL, 0 },
106};
107
108#define IOMEM(x) ((void __iomem *)(KSEG1ADDR(CPHYSADDR(x))))
109
110/* access locks to SYS_FREQCTRL0/1 and SYS_CLKSRC registers */
111static spinlock_t alchemy_clk_fg0_lock;
112static spinlock_t alchemy_clk_fg1_lock;
113static spinlock_t alchemy_clk_csrc_lock;
114
115/* CPU Core clock *****************************************************/
116
117static unsigned long alchemy_clk_cpu_recalc(struct clk_hw *hw,
118 unsigned long parent_rate)
119{
120 unsigned long t;
121
122 /*
123 * On early Au1000, sys_cpupll was write-only. Since these
124 * silicon versions of Au1000 are not sold, we don't bend
125 * over backwards trying to determine the frequency.
126 */
127 if (unlikely(au1xxx_cpu_has_pll_wo()))
128 t = 396000000;
129 else {
130 t = alchemy_rdsys(AU1000_SYS_CPUPLL) & 0x7f;
131 t *= parent_rate;
132 }
133
134 return t;
135}
136
137static struct clk_ops alchemy_clkops_cpu = {
138 .recalc_rate = alchemy_clk_cpu_recalc,
139};
140
141static struct clk __init *alchemy_clk_setup_cpu(const char *parent_name,
142 int ctype)
143{
144 struct clk_init_data id;
145 struct clk_hw *h;
146
147 h = kzalloc(sizeof(*h), GFP_KERNEL);
148 if (!h)
149 return ERR_PTR(-ENOMEM);
150
151 id.name = ALCHEMY_CPU_CLK;
152 id.parent_names = &parent_name;
153 id.num_parents = 1;
154 id.flags = CLK_IS_BASIC | CLK_IGNORE_UNUSED;
155 id.ops = &alchemy_clkops_cpu;
156 h->init = &id;
157
158 return clk_register(NULL, h);
159}
160
161/* AUXPLLs ************************************************************/
162
163struct alchemy_auxpll_clk {
164 struct clk_hw hw;
165 unsigned long reg; /* au1300 has also AUXPLL2 */
166 int maxmult; /* max multiplier */
167};
168#define to_auxpll_clk(x) container_of(x, struct alchemy_auxpll_clk, hw)
169
170static unsigned long alchemy_clk_aux_recalc(struct clk_hw *hw,
171 unsigned long parent_rate)
172{
173 struct alchemy_auxpll_clk *a = to_auxpll_clk(hw);
174
175 return (alchemy_rdsys(a->reg) & 0xff) * parent_rate;
176}
177
178static int alchemy_clk_aux_setr(struct clk_hw *hw,
179 unsigned long rate,
180 unsigned long parent_rate)
181{
182 struct alchemy_auxpll_clk *a = to_auxpll_clk(hw);
183 unsigned long d = rate;
184
185 if (rate)
186 d /= parent_rate;
187 else
188 d = 0;
189
190 /* minimum is 84MHz, max is 756-1032 depending on variant */
191 if (((d < 7) && (d != 0)) || (d > a->maxmult))
192 return -EINVAL;
193
194 alchemy_wrsys(d, a->reg);
195 return 0;
196}
197
198static long alchemy_clk_aux_roundr(struct clk_hw *hw,
199 unsigned long rate,
200 unsigned long *parent_rate)
201{
202 struct alchemy_auxpll_clk *a = to_auxpll_clk(hw);
203 unsigned long mult;
204
205 if (!rate || !*parent_rate)
206 return 0;
207
208 mult = rate / (*parent_rate);
209
210 if (mult && (mult < 7))
211 mult = 7;
212 if (mult > a->maxmult)
213 mult = a->maxmult;
214
215 return (*parent_rate) * mult;
216}
217
218static struct clk_ops alchemy_clkops_aux = {
219 .recalc_rate = alchemy_clk_aux_recalc,
220 .set_rate = alchemy_clk_aux_setr,
221 .round_rate = alchemy_clk_aux_roundr,
222};
223
224static struct clk __init *alchemy_clk_setup_aux(const char *parent_name,
225 char *name, int maxmult,
226 unsigned long reg)
227{
228 struct clk_init_data id;
229 struct clk *c;
230 struct alchemy_auxpll_clk *a;
231
232 a = kzalloc(sizeof(*a), GFP_KERNEL);
233 if (!a)
234 return ERR_PTR(-ENOMEM);
235
236 id.name = name;
237 id.parent_names = &parent_name;
238 id.num_parents = 1;
239 id.flags = CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED;
240 id.ops = &alchemy_clkops_aux;
241
242 a->reg = reg;
243 a->maxmult = maxmult;
244 a->hw.init = &id;
245
246 c = clk_register(NULL, &a->hw);
247 if (!IS_ERR(c))
248 clk_register_clkdev(c, name, NULL);
249 else
250 kfree(a);
251
252 return c;
253}
254
255/* sysbus_clk *********************************************************/
256
257static struct clk __init *alchemy_clk_setup_sysbus(const char *pn)
258{
259 unsigned long v = (alchemy_rdsys(AU1000_SYS_POWERCTRL) & 3) + 2;
260 struct clk *c;
261
262 c = clk_register_fixed_factor(NULL, ALCHEMY_SYSBUS_CLK,
263 pn, 0, 1, v);
264 if (!IS_ERR(c))
265 clk_register_clkdev(c, ALCHEMY_SYSBUS_CLK, NULL);
266 return c;
267}
268
269/* Peripheral Clock ***************************************************/
270
271static struct clk __init *alchemy_clk_setup_periph(const char *pn)
272{
273 /* Peripheral clock runs at half the rate of sysbus clk */
274 struct clk *c;
275
276 c = clk_register_fixed_factor(NULL, ALCHEMY_PERIPH_CLK,
277 pn, 0, 1, 2);
278 if (!IS_ERR(c))
279 clk_register_clkdev(c, ALCHEMY_PERIPH_CLK, NULL);
280 return c;
281}
282
283/* mem clock **********************************************************/
284
285static struct clk __init *alchemy_clk_setup_mem(const char *pn, int ct)
286{
287 void __iomem *addr = IOMEM(AU1000_MEM_PHYS_ADDR);
288 unsigned long v;
289 struct clk *c;
290 int div;
291
292 switch (ct) {
293 case ALCHEMY_CPU_AU1550:
294 case ALCHEMY_CPU_AU1200:
295 v = __raw_readl(addr + AU1550_MEM_SDCONFIGB);
296 div = (v & (1 << 15)) ? 1 : 2;
297 break;
298 case ALCHEMY_CPU_AU1300:
299 v = __raw_readl(addr + AU1550_MEM_SDCONFIGB);
300 div = (v & (1 << 31)) ? 1 : 2;
301 break;
302 case ALCHEMY_CPU_AU1000:
303 case ALCHEMY_CPU_AU1500:
304 case ALCHEMY_CPU_AU1100:
305 default:
306 div = 2;
307 break;
308 }
309
310 c = clk_register_fixed_factor(NULL, ALCHEMY_MEM_CLK, pn,
311 0, 1, div);
312 if (!IS_ERR(c))
313 clk_register_clkdev(c, ALCHEMY_MEM_CLK, NULL);
314 return c;
315}
316
317/* lrclk: external synchronous static bus clock ***********************/
318
319static struct clk __init *alchemy_clk_setup_lrclk(const char *pn)
320{
321 /* MEM_STCFG0[15:13] = divisor.
322 * L/RCLK = periph_clk / (divisor + 1)
323 * On Au1000, Au1500, Au1100 it's called LCLK,
324 * on later models it's called RCLK, but it's the same thing.
325 */
326 struct clk *c;
327 unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0) >> 13;
328
329 v = (v & 7) + 1;
330 c = clk_register_fixed_factor(NULL, ALCHEMY_LR_CLK,
331 pn, 0, 1, v);
332 if (!IS_ERR(c))
333 clk_register_clkdev(c, ALCHEMY_LR_CLK, NULL);
334 return c;
335}
336
337/* Clock dividers and muxes *******************************************/
338
339/* data for fgen and csrc mux-dividers */
340struct alchemy_fgcs_clk {
341 struct clk_hw hw;
342 spinlock_t *reglock; /* register lock */
343 unsigned long reg; /* SYS_FREQCTRL0/1 */
344 int shift; /* offset in register */
345 int parent; /* parent before disable [Au1300] */
346 int isen; /* is it enabled? */
347 int *dt; /* dividertable for csrc */
348};
349#define to_fgcs_clk(x) container_of(x, struct alchemy_fgcs_clk, hw)
350
351static long alchemy_calc_div(unsigned long rate, unsigned long prate,
352 int scale, int maxdiv, unsigned long *rv)
353{
354 long div1, div2;
355
356 div1 = prate / rate;
357 if ((prate / div1) > rate)
358 div1++;
359
360 if (scale == 2) { /* only div-by-multiple-of-2 possible */
361 if (div1 & 1)
362 div1++; /* stay <=prate */
363 }
364
365 div2 = (div1 / scale) - 1; /* value to write to register */
366
367 if (div2 > maxdiv)
368 div2 = maxdiv;
369 if (rv)
370 *rv = div2;
371
372 div1 = ((div2 + 1) * scale);
373 return div1;
374}
375
376static long alchemy_clk_fgcs_detr(struct clk_hw *hw, unsigned long rate,
377 unsigned long *best_parent_rate,
378 struct clk **best_parent_clk,
379 int scale, int maxdiv)
380{
381 struct clk *pc, *bpc, *free;
382 long tdv, tpr, pr, nr, br, bpr, diff, lastdiff;
383 int j;
384
385 lastdiff = INT_MAX;
386 bpr = 0;
387 bpc = NULL;
388 br = -EINVAL;
389 free = NULL;
390
391 /* look at the rates each enabled parent supplies and select
392 * the one that gets closest to but not over the requested rate.
393 */
394 for (j = 0; j < 7; j++) {
395 pc = clk_get_parent_by_index(hw->clk, j);
396 if (!pc)
397 break;
398
399 /* if this parent is currently unused, remember it.
400 * XXX: I know it's a layering violation, but it works
401 * so well.. (if (!clk_has_active_children(pc)) )
402 */
403 if (pc->prepare_count == 0) {
404 if (!free)
405 free = pc;
406 }
407
408 pr = clk_get_rate(pc);
409 if (pr < rate)
410 continue;
411
412 /* what can hardware actually provide */
413 tdv = alchemy_calc_div(rate, pr, scale, maxdiv, NULL);
414 nr = pr / tdv;
415 diff = rate - nr;
416 if (nr > rate)
417 continue;
418
419 if (diff < lastdiff) {
420 lastdiff = diff;
421 bpr = pr;
422 bpc = pc;
423 br = nr;
424 }
425 if (diff == 0)
426 break;
427 }
428
429 /* if we couldn't get the exact rate we wanted from the enabled
430 * parents, maybe we can tell an available disabled/inactive one
431 * to give us a rate we can divide down to the requested rate.
432 */
433 if (lastdiff && free) {
434 for (j = (maxdiv == 4) ? 1 : scale; j <= maxdiv; j += scale) {
435 tpr = rate * j;
436 if (tpr < 0)
437 break;
438 pr = clk_round_rate(free, tpr);
439
440 tdv = alchemy_calc_div(rate, pr, scale, maxdiv, NULL);
441 nr = pr / tdv;
442 diff = rate - nr;
443 if (nr > rate)
444 continue;
445 if (diff < lastdiff) {
446 lastdiff = diff;
447 bpr = pr;
448 bpc = free;
449 br = nr;
450 }
451 if (diff == 0)
452 break;
453 }
454 }
455
456 *best_parent_rate = bpr;
457 *best_parent_clk = bpc;
458 return br;
459}
460
461static int alchemy_clk_fgv1_en(struct clk_hw *hw)
462{
463 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
464 unsigned long v, flags;
465
466 spin_lock_irqsave(c->reglock, flags);
467 v = alchemy_rdsys(c->reg);
468 v |= (1 << 1) << c->shift;
469 alchemy_wrsys(v, c->reg);
470 spin_unlock_irqrestore(c->reglock, flags);
471
472 return 0;
473}
474
475static int alchemy_clk_fgv1_isen(struct clk_hw *hw)
476{
477 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
478 unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 1);
479
480 return v & 1;
481}
482
483static void alchemy_clk_fgv1_dis(struct clk_hw *hw)
484{
485 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
486 unsigned long v, flags;
487
488 spin_lock_irqsave(c->reglock, flags);
489 v = alchemy_rdsys(c->reg);
490 v &= ~((1 << 1) << c->shift);
491 alchemy_wrsys(v, c->reg);
492 spin_unlock_irqrestore(c->reglock, flags);
493}
494
495static int alchemy_clk_fgv1_setp(struct clk_hw *hw, u8 index)
496{
497 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
498 unsigned long v, flags;
499
500 spin_lock_irqsave(c->reglock, flags);
501 v = alchemy_rdsys(c->reg);
502 if (index)
503 v |= (1 << c->shift);
504 else
505 v &= ~(1 << c->shift);
506 alchemy_wrsys(v, c->reg);
507 spin_unlock_irqrestore(c->reglock, flags);
508
509 return 0;
510}
511
512static u8 alchemy_clk_fgv1_getp(struct clk_hw *hw)
513{
514 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
515
516 return (alchemy_rdsys(c->reg) >> c->shift) & 1;
517}
518
519static int alchemy_clk_fgv1_setr(struct clk_hw *hw, unsigned long rate,
520 unsigned long parent_rate)
521{
522 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
523 unsigned long div, v, flags, ret;
524 int sh = c->shift + 2;
525
526 if (!rate || !parent_rate || rate > (parent_rate / 2))
527 return -EINVAL;
528 ret = alchemy_calc_div(rate, parent_rate, 2, 512, &div);
529 spin_lock_irqsave(c->reglock, flags);
530 v = alchemy_rdsys(c->reg);
531 v &= ~(0xff << sh);
532 v |= div << sh;
533 alchemy_wrsys(v, c->reg);
534 spin_unlock_irqrestore(c->reglock, flags);
535
536 return 0;
537}
538
539static unsigned long alchemy_clk_fgv1_recalc(struct clk_hw *hw,
540 unsigned long parent_rate)
541{
542 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
543 unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 2);
544
545 v = ((v & 0xff) + 1) * 2;
546 return parent_rate / v;
547}
548
549static long alchemy_clk_fgv1_detr(struct clk_hw *hw, unsigned long rate,
550 unsigned long *best_parent_rate,
551 struct clk **best_parent_clk)
552{
553 return alchemy_clk_fgcs_detr(hw, rate, best_parent_rate,
554 best_parent_clk, 2, 512);
555}
556
557/* Au1000, Au1100, Au15x0, Au12x0 */
558static struct clk_ops alchemy_clkops_fgenv1 = {
559 .recalc_rate = alchemy_clk_fgv1_recalc,
560 .determine_rate = alchemy_clk_fgv1_detr,
561 .set_rate = alchemy_clk_fgv1_setr,
562 .set_parent = alchemy_clk_fgv1_setp,
563 .get_parent = alchemy_clk_fgv1_getp,
564 .enable = alchemy_clk_fgv1_en,
565 .disable = alchemy_clk_fgv1_dis,
566 .is_enabled = alchemy_clk_fgv1_isen,
567};
568
569static void __alchemy_clk_fgv2_en(struct alchemy_fgcs_clk *c)
570{
571 unsigned long v = alchemy_rdsys(c->reg);
572
573 v &= ~(3 << c->shift);
574 v |= (c->parent & 3) << c->shift;
575 alchemy_wrsys(v, c->reg);
576 c->isen = 1;
577}
578
579static int alchemy_clk_fgv2_en(struct clk_hw *hw)
580{
581 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
582 unsigned long flags;
583
584 /* enable by setting the previous parent clock */
585 spin_lock_irqsave(c->reglock, flags);
586 __alchemy_clk_fgv2_en(c);
587 spin_unlock_irqrestore(c->reglock, flags);
588
589 return 0;
590}
591
592static int alchemy_clk_fgv2_isen(struct clk_hw *hw)
593{
594 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
595
596 return ((alchemy_rdsys(c->reg) >> c->shift) & 3) != 0;
597}
598
599static void alchemy_clk_fgv2_dis(struct clk_hw *hw)
600{
601 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
602 unsigned long v, flags;
603
604 spin_lock_irqsave(c->reglock, flags);
605 v = alchemy_rdsys(c->reg);
606 v &= ~(3 << c->shift); /* set input mux to "disabled" state */
607 alchemy_wrsys(v, c->reg);
608 c->isen = 0;
609 spin_unlock_irqrestore(c->reglock, flags);
610}
611
612static int alchemy_clk_fgv2_setp(struct clk_hw *hw, u8 index)
613{
614 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
615 unsigned long flags;
616
617 spin_lock_irqsave(c->reglock, flags);
618 c->parent = index + 1; /* value to write to register */
619 if (c->isen)
620 __alchemy_clk_fgv2_en(c);
621 spin_unlock_irqrestore(c->reglock, flags);
622
623 return 0;
624}
625
626static u8 alchemy_clk_fgv2_getp(struct clk_hw *hw)
627{
628 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
629 unsigned long flags, v;
630
631 spin_lock_irqsave(c->reglock, flags);
632 v = c->parent - 1;
633 spin_unlock_irqrestore(c->reglock, flags);
634 return v;
635}
636
637/* fg0-2 and fg4-6 share a "scale"-bit. With this bit cleared, the
638 * dividers behave exactly as on previous models (dividers are multiples
639 * of 2); with the bit set, dividers are multiples of 1, halving their
640 * range, but making them also much more flexible.
641 */
642static int alchemy_clk_fgv2_setr(struct clk_hw *hw, unsigned long rate,
643 unsigned long parent_rate)
644{
645 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
646 int sh = c->shift + 2;
647 unsigned long div, v, flags, ret;
648
649 if (!rate || !parent_rate || rate > parent_rate)
650 return -EINVAL;
651
652 v = alchemy_rdsys(c->reg) & (1 << 30); /* test "scale" bit */
653 ret = alchemy_calc_div(rate, parent_rate, v ? 1 : 2,
654 v ? 256 : 512, &div);
655
656 spin_lock_irqsave(c->reglock, flags);
657 v = alchemy_rdsys(c->reg);
658 v &= ~(0xff << sh);
659 v |= (div & 0xff) << sh;
660 alchemy_wrsys(v, c->reg);
661 spin_unlock_irqrestore(c->reglock, flags);
662
663 return 0;
664}
665
666static unsigned long alchemy_clk_fgv2_recalc(struct clk_hw *hw,
667 unsigned long parent_rate)
668{
669 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
670 int sh = c->shift + 2;
671 unsigned long v, t;
672
673 v = alchemy_rdsys(c->reg);
674 t = parent_rate / (((v >> sh) & 0xff) + 1);
675 if ((v & (1 << 30)) == 0) /* test scale bit */
676 t /= 2;
677
678 return t;
679}
680
681static long alchemy_clk_fgv2_detr(struct clk_hw *hw, unsigned long rate,
682 unsigned long *best_parent_rate,
683 struct clk **best_parent_clk)
684{
685 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
686 int scale, maxdiv;
687
688 if (alchemy_rdsys(c->reg) & (1 << 30)) {
689 scale = 1;
690 maxdiv = 256;
691 } else {
692 scale = 2;
693 maxdiv = 512;
694 }
695
696 return alchemy_clk_fgcs_detr(hw, rate, best_parent_rate,
697 best_parent_clk, scale, maxdiv);
698}
699
700/* Au1300 larger input mux, no separate disable bit, flexible divider */
701static struct clk_ops alchemy_clkops_fgenv2 = {
702 .recalc_rate = alchemy_clk_fgv2_recalc,
703 .determine_rate = alchemy_clk_fgv2_detr,
704 .set_rate = alchemy_clk_fgv2_setr,
705 .set_parent = alchemy_clk_fgv2_setp,
706 .get_parent = alchemy_clk_fgv2_getp,
707 .enable = alchemy_clk_fgv2_en,
708 .disable = alchemy_clk_fgv2_dis,
709 .is_enabled = alchemy_clk_fgv2_isen,
710};
711
712static const char * const alchemy_clk_fgv1_parents[] = {
713 ALCHEMY_CPU_CLK, ALCHEMY_AUXPLL_CLK
714};
715
716static const char * const alchemy_clk_fgv2_parents[] = {
717 ALCHEMY_AUXPLL2_CLK, ALCHEMY_CPU_CLK, ALCHEMY_AUXPLL_CLK
718};
719
720static const char * const alchemy_clk_fgen_names[] = {
721 ALCHEMY_FG0_CLK, ALCHEMY_FG1_CLK, ALCHEMY_FG2_CLK,
722 ALCHEMY_FG3_CLK, ALCHEMY_FG4_CLK, ALCHEMY_FG5_CLK };
723
724static int __init alchemy_clk_init_fgens(int ctype)
725{
726 struct clk *c;
727 struct clk_init_data id;
728 struct alchemy_fgcs_clk *a;
729 unsigned long v;
730 int i, ret;
731
732 switch (ctype) {
733 case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200:
734 id.ops = &alchemy_clkops_fgenv1;
735 id.parent_names = (const char **)alchemy_clk_fgv1_parents;
736 id.num_parents = 2;
737 break;
738 case ALCHEMY_CPU_AU1300:
739 id.ops = &alchemy_clkops_fgenv2;
740 id.parent_names = (const char **)alchemy_clk_fgv2_parents;
741 id.num_parents = 3;
742 break;
743 default:
744 return -ENODEV;
745 }
746 id.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE |
747 CLK_IGNORE_UNUSED;
748
749 a = kzalloc((sizeof(*a)) * 6, GFP_KERNEL);
750 if (!a)
751 return -ENOMEM;
752
753 spin_lock_init(&alchemy_clk_fg0_lock);
754 spin_lock_init(&alchemy_clk_fg1_lock);
755 ret = 0;
756 for (i = 0; i < 6; i++) {
757 id.name = alchemy_clk_fgen_names[i];
758 a->shift = 10 * (i < 3 ? i : i - 3);
759 if (i > 2) {
760 a->reg = AU1000_SYS_FREQCTRL1;
761 a->reglock = &alchemy_clk_fg1_lock;
762 } else {
763 a->reg = AU1000_SYS_FREQCTRL0;
764 a->reglock = &alchemy_clk_fg0_lock;
765 }
766
767 /* default to first parent if bootloader has set
768 * the mux to disabled state.
769 */
770 if (ctype == ALCHEMY_CPU_AU1300) {
771 v = alchemy_rdsys(a->reg);
772 a->parent = (v >> a->shift) & 3;
773 if (!a->parent) {
774 a->parent = 1;
775 a->isen = 0;
776 } else
777 a->isen = 1;
778 }
779
780 a->hw.init = &id;
781 c = clk_register(NULL, &a->hw);
782 if (IS_ERR(c))
783 ret++;
784 else
785 clk_register_clkdev(c, id.name, NULL);
786 a++;
787 }
788
789 return ret;
790}
791
792/* internal sources muxes *********************************************/
793
794static int alchemy_clk_csrc_isen(struct clk_hw *hw)
795{
796 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
797 unsigned long v = alchemy_rdsys(c->reg);
798
799 return (((v >> c->shift) >> 2) & 7) != 0;
800}
801
802static void __alchemy_clk_csrc_en(struct alchemy_fgcs_clk *c)
803{
804 unsigned long v = alchemy_rdsys(c->reg);
805
806 v &= ~((7 << 2) << c->shift);
807 v |= ((c->parent & 7) << 2) << c->shift;
808 alchemy_wrsys(v, c->reg);
809 c->isen = 1;
810}
811
812static int alchemy_clk_csrc_en(struct clk_hw *hw)
813{
814 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
815 unsigned long flags;
816
817 /* enable by setting the previous parent clock */
818 spin_lock_irqsave(c->reglock, flags);
819 __alchemy_clk_csrc_en(c);
820 spin_unlock_irqrestore(c->reglock, flags);
821
822 return 0;
823}
824
825static void alchemy_clk_csrc_dis(struct clk_hw *hw)
826{
827 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
828 unsigned long v, flags;
829
830 spin_lock_irqsave(c->reglock, flags);
831 v = alchemy_rdsys(c->reg);
832 v &= ~((3 << 2) << c->shift); /* mux to "disabled" state */
833 alchemy_wrsys(v, c->reg);
834 c->isen = 0;
835 spin_unlock_irqrestore(c->reglock, flags);
836}
837
838static int alchemy_clk_csrc_setp(struct clk_hw *hw, u8 index)
839{
840 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
841 unsigned long flags;
842
843 spin_lock_irqsave(c->reglock, flags);
844 c->parent = index + 1; /* value to write to register */
845 if (c->isen)
846 __alchemy_clk_csrc_en(c);
847 spin_unlock_irqrestore(c->reglock, flags);
848
849 return 0;
850}
851
852static u8 alchemy_clk_csrc_getp(struct clk_hw *hw)
853{
854 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
855
856 return c->parent - 1;
857}
858
859static unsigned long alchemy_clk_csrc_recalc(struct clk_hw *hw,
860 unsigned long parent_rate)
861{
862 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
863 unsigned long v = (alchemy_rdsys(c->reg) >> c->shift) & 3;
864
865 return parent_rate / c->dt[v];
866}
867
868static int alchemy_clk_csrc_setr(struct clk_hw *hw, unsigned long rate,
869 unsigned long parent_rate)
870{
871 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
872 unsigned long d, v, flags;
873 int i;
874
875 if (!rate || !parent_rate || rate > parent_rate)
876 return -EINVAL;
877
878 d = (parent_rate + (rate / 2)) / rate;
879 if (d > 4)
880 return -EINVAL;
881 if ((d == 3) && (c->dt[2] != 3))
882 d = 4;
883
884 for (i = 0; i < 4; i++)
885 if (c->dt[i] == d)
886 break;
887
888 if (i >= 4)
889 return -EINVAL; /* oops */
890
891 spin_lock_irqsave(c->reglock, flags);
892 v = alchemy_rdsys(c->reg);
893 v &= ~(3 << c->shift);
894 v |= (i & 3) << c->shift;
895 alchemy_wrsys(v, c->reg);
896 spin_unlock_irqrestore(c->reglock, flags);
897
898 return 0;
899}
900
901static long alchemy_clk_csrc_detr(struct clk_hw *hw, unsigned long rate,
902 unsigned long *best_parent_rate,
903 struct clk **best_parent_clk)
904{
905 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
906 int scale = c->dt[2] == 3 ? 1 : 2; /* au1300 check */
907
908 return alchemy_clk_fgcs_detr(hw, rate, best_parent_rate,
909 best_parent_clk, scale, 4);
910}
911
912static struct clk_ops alchemy_clkops_csrc = {
913 .recalc_rate = alchemy_clk_csrc_recalc,
914 .determine_rate = alchemy_clk_csrc_detr,
915 .set_rate = alchemy_clk_csrc_setr,
916 .set_parent = alchemy_clk_csrc_setp,
917 .get_parent = alchemy_clk_csrc_getp,
918 .enable = alchemy_clk_csrc_en,
919 .disable = alchemy_clk_csrc_dis,
920 .is_enabled = alchemy_clk_csrc_isen,
921};
922
923static const char * const alchemy_clk_csrc_parents[] = {
924 /* disabled at index 0 */ ALCHEMY_AUXPLL_CLK,
925 ALCHEMY_FG0_CLK, ALCHEMY_FG1_CLK, ALCHEMY_FG2_CLK,
926 ALCHEMY_FG3_CLK, ALCHEMY_FG4_CLK, ALCHEMY_FG5_CLK
927};
928
929/* divider tables */
930static int alchemy_csrc_dt1[] = { 1, 4, 1, 2 }; /* rest */
931static int alchemy_csrc_dt2[] = { 1, 4, 3, 2 }; /* Au1300 */
932
933static int __init alchemy_clk_setup_imux(int ctype)
934{
935 struct alchemy_fgcs_clk *a;
936 const char * const *names;
937 struct clk_init_data id;
938 unsigned long v;
939 int i, ret, *dt;
940 struct clk *c;
941
942 id.ops = &alchemy_clkops_csrc;
943 id.parent_names = (const char **)alchemy_clk_csrc_parents;
944 id.num_parents = 7;
945 id.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE |
946 CLK_IGNORE_UNUSED;
947
948 dt = alchemy_csrc_dt1;
949 switch (ctype) {
950 case ALCHEMY_CPU_AU1000:
951 names = alchemy_au1000_intclknames;
952 break;
953 case ALCHEMY_CPU_AU1500:
954 names = alchemy_au1500_intclknames;
955 break;
956 case ALCHEMY_CPU_AU1100:
957 names = alchemy_au1100_intclknames;
958 break;
959 case ALCHEMY_CPU_AU1550:
960 names = alchemy_au1550_intclknames;
961 break;
962 case ALCHEMY_CPU_AU1200:
963 names = alchemy_au1200_intclknames;
964 break;
965 case ALCHEMY_CPU_AU1300:
966 dt = alchemy_csrc_dt2;
967 names = alchemy_au1300_intclknames;
968 break;
969 default:
970 return -ENODEV;
971 }
972
973 a = kzalloc((sizeof(*a)) * 6, GFP_KERNEL);
974 if (!a)
975 return -ENOMEM;
976
977 spin_lock_init(&alchemy_clk_csrc_lock);
978 ret = 0;
979
980 for (i = 0; i < 6; i++) {
981 id.name = names[i];
982 if (!id.name)
983 goto next;
984
985 a->shift = i * 5;
986 a->reg = AU1000_SYS_CLKSRC;
987 a->reglock = &alchemy_clk_csrc_lock;
988 a->dt = dt;
989
990 /* default to first parent clock if mux is initially
991 * set to disabled state.
992 */
993 v = alchemy_rdsys(a->reg);
994 a->parent = ((v >> a->shift) >> 2) & 7;
995 if (!a->parent) {
996 a->parent = 1;
997 a->isen = 0;
998 } else
999 a->isen = 1;
1000
1001 a->hw.init = &id;
1002 c = clk_register(NULL, &a->hw);
1003 if (IS_ERR(c))
1004 ret++;
1005 else
1006 clk_register_clkdev(c, id.name, NULL);
1007next:
1008 a++;
1009 }
1010
1011 return ret;
1012}
1013
1014
1015/**********************************************************************/
1016
1017
1018#define ERRCK(x) \
1019 if (IS_ERR(x)) { \
1020 ret = PTR_ERR(x); \
1021 goto out; \
1022 }
1023
1024static int __init alchemy_clk_init(void)
1025{
1026 int ctype = alchemy_get_cputype(), ret, i;
1027 struct clk_aliastable *t = alchemy_clk_aliases;
1028 struct clk *c;
1029
1030 /* Root of the Alchemy clock tree: external 12MHz crystal osc */
1031 c = clk_register_fixed_rate(NULL, ALCHEMY_ROOT_CLK, NULL,
1032 CLK_IS_ROOT,
1033 ALCHEMY_ROOTCLK_RATE);
1034 ERRCK(c)
1035
1036 /* CPU core clock */
1037 c = alchemy_clk_setup_cpu(ALCHEMY_ROOT_CLK, ctype);
1038 ERRCK(c)
1039
1040 /* AUXPLLs: max 1GHz on Au1300, 748MHz on older models */
1041 i = (ctype == ALCHEMY_CPU_AU1300) ? 84 : 63;
1042 c = alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK, ALCHEMY_AUXPLL_CLK,
1043 i, AU1000_SYS_AUXPLL);
1044 ERRCK(c)
1045
1046 if (ctype == ALCHEMY_CPU_AU1300) {
1047 c = alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK,
1048 ALCHEMY_AUXPLL2_CLK, i,
1049 AU1300_SYS_AUXPLL2);
1050 ERRCK(c)
1051 }
1052
1053 /* sysbus clock: cpu core clock divided by 2, 3 or 4 */
1054 c = alchemy_clk_setup_sysbus(ALCHEMY_CPU_CLK);
1055 ERRCK(c)
1056
1057 /* peripheral clock: runs at half rate of sysbus clk */
1058 c = alchemy_clk_setup_periph(ALCHEMY_SYSBUS_CLK);
1059 ERRCK(c)
1060
1061 /* SDR/DDR memory clock */
1062 c = alchemy_clk_setup_mem(ALCHEMY_SYSBUS_CLK, ctype);
1063 ERRCK(c)
1064
1065 /* L/RCLK: external static bus clock for synchronous mode */
1066 c = alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK);
1067 ERRCK(c)
1068
1069 /* Frequency dividers 0-5 */
1070 ret = alchemy_clk_init_fgens(ctype);
1071 if (ret) {
1072 ret = -ENODEV;
1073 goto out;
1074 }
1075
1076 /* diving muxes for internal sources */
1077 ret = alchemy_clk_setup_imux(ctype);
1078 if (ret) {
1079 ret = -ENODEV;
1080 goto out;
1081 }
1082
1083 /* set up aliases drivers might look for */
1084 while (t->base) {
1085 if (t->cputype == ctype)
1086 clk_add_alias(t->alias, NULL, t->base, NULL);
1087 t++;
1088 }
1089
1090 pr_info("Alchemy clocktree installed\n");
1091 return 0;
1092
1093out:
1094 return ret;
1095}
1096postcore_initcall(alchemy_clk_init);
Linux kernel - Deliverables
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