Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * BRIEF MODULE DESCRIPTION | |
c1dcb14e | 3 | * Au1xx0 Power Management routines. |
1da177e4 | 4 | * |
c1dcb14e SS |
5 | * Copyright 2001, 2008 MontaVista Software Inc. |
6 | * Author: MontaVista Software, Inc. <source@mvista.com> | |
1da177e4 LT |
7 | * |
8 | * Some of the routines are right out of init/main.c, whose | |
9 | * copyrights apply here. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the | |
13 | * Free Software Foundation; either version 2 of the License, or (at your | |
14 | * option) any later version. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
18 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
19 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
20 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
21 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
22 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
23 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
25 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License along | |
28 | * with this program; if not, write to the Free Software Foundation, Inc., | |
29 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
30 | */ | |
ce28f94c | 31 | |
1da177e4 | 32 | #include <linux/pm.h> |
1da177e4 | 33 | #include <linux/sysctl.h> |
3ce86ee1 | 34 | #include <linux/jiffies.h> |
1da177e4 | 35 | |
1da177e4 | 36 | #include <asm/uaccess.h> |
1da177e4 LT |
37 | #include <asm/mach-au1x00/au1000.h> |
38 | ||
c1dcb14e SS |
39 | /* |
40 | * We need to save/restore a bunch of core registers that are | |
1da177e4 LT |
41 | * either volatile or reset to some state across a processor sleep. |
42 | * If reading a register doesn't provide a proper result for a | |
43 | * later restore, we have to provide a function for loading that | |
44 | * register and save a copy. | |
45 | * | |
46 | * We only have to save/restore registers that aren't otherwise | |
47 | * done as part of a driver pm_* function. | |
48 | */ | |
564365b0 ML |
49 | static unsigned int sleep_sys_clocks[5]; |
50 | static unsigned int sleep_sys_pinfunc; | |
51 | static unsigned int sleep_static_memctlr[4][3]; | |
1da177e4 | 52 | |
1da177e4 | 53 | |
c1dcb14e | 54 | static void save_core_regs(void) |
1da177e4 | 55 | { |
c1dcb14e | 56 | /* Clocks and PLLs. */ |
1d09de7d ML |
57 | sleep_sys_clocks[0] = alchemy_rdsys(AU1000_SYS_FREQCTRL0); |
58 | sleep_sys_clocks[1] = alchemy_rdsys(AU1000_SYS_FREQCTRL1); | |
59 | sleep_sys_clocks[2] = alchemy_rdsys(AU1000_SYS_CLKSRC); | |
60 | sleep_sys_clocks[3] = alchemy_rdsys(AU1000_SYS_CPUPLL); | |
61 | sleep_sys_clocks[4] = alchemy_rdsys(AU1000_SYS_AUXPLL); | |
1da177e4 | 62 | |
564365b0 | 63 | /* pin mux config */ |
1d09de7d | 64 | sleep_sys_pinfunc = alchemy_rdsys(AU1000_SYS_PINFUNC); |
1da177e4 | 65 | |
c1dcb14e | 66 | /* Save the static memory controller configuration. */ |
1da177e4 LT |
67 | sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0); |
68 | sleep_static_memctlr[0][1] = au_readl(MEM_STTIME0); | |
69 | sleep_static_memctlr[0][2] = au_readl(MEM_STADDR0); | |
70 | sleep_static_memctlr[1][0] = au_readl(MEM_STCFG1); | |
71 | sleep_static_memctlr[1][1] = au_readl(MEM_STTIME1); | |
72 | sleep_static_memctlr[1][2] = au_readl(MEM_STADDR1); | |
73 | sleep_static_memctlr[2][0] = au_readl(MEM_STCFG2); | |
74 | sleep_static_memctlr[2][1] = au_readl(MEM_STTIME2); | |
75 | sleep_static_memctlr[2][2] = au_readl(MEM_STADDR2); | |
76 | sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3); | |
77 | sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3); | |
78 | sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3); | |
79 | } | |
80 | ||
c1dcb14e | 81 | static void restore_core_regs(void) |
1da177e4 | 82 | { |
564365b0 ML |
83 | /* restore clock configuration. Writing CPUPLL last will |
84 | * stall a bit and stabilize other clocks (unless this is | |
85 | * one of those Au1000 with a write-only PLL, where we dont | |
86 | * have a valid value) | |
87 | */ | |
1d09de7d ML |
88 | alchemy_wrsys(sleep_sys_clocks[0], AU1000_SYS_FREQCTRL0); |
89 | alchemy_wrsys(sleep_sys_clocks[1], AU1000_SYS_FREQCTRL1); | |
90 | alchemy_wrsys(sleep_sys_clocks[2], AU1000_SYS_CLKSRC); | |
91 | alchemy_wrsys(sleep_sys_clocks[4], AU1000_SYS_AUXPLL); | |
564365b0 | 92 | if (!au1xxx_cpu_has_pll_wo()) |
1d09de7d | 93 | alchemy_wrsys(sleep_sys_clocks[3], AU1000_SYS_CPUPLL); |
564365b0 | 94 | |
1d09de7d | 95 | alchemy_wrsys(sleep_sys_pinfunc, AU1000_SYS_PINFUNC); |
564365b0 | 96 | |
c1dcb14e | 97 | /* Restore the static memory controller configuration. */ |
1da177e4 LT |
98 | au_writel(sleep_static_memctlr[0][0], MEM_STCFG0); |
99 | au_writel(sleep_static_memctlr[0][1], MEM_STTIME0); | |
100 | au_writel(sleep_static_memctlr[0][2], MEM_STADDR0); | |
101 | au_writel(sleep_static_memctlr[1][0], MEM_STCFG1); | |
102 | au_writel(sleep_static_memctlr[1][1], MEM_STTIME1); | |
103 | au_writel(sleep_static_memctlr[1][2], MEM_STADDR1); | |
104 | au_writel(sleep_static_memctlr[2][0], MEM_STCFG2); | |
105 | au_writel(sleep_static_memctlr[2][1], MEM_STTIME2); | |
106 | au_writel(sleep_static_memctlr[2][2], MEM_STADDR2); | |
107 | au_writel(sleep_static_memctlr[3][0], MEM_STCFG3); | |
108 | au_writel(sleep_static_memctlr[3][1], MEM_STTIME3); | |
109 | au_writel(sleep_static_memctlr[3][2], MEM_STADDR3); | |
1da177e4 LT |
110 | } |
111 | ||
564365b0 ML |
112 | void au_sleep(void) |
113 | { | |
870168a0 ML |
114 | save_core_regs(); |
115 | ||
116 | switch (alchemy_get_cputype()) { | |
117 | case ALCHEMY_CPU_AU1000: | |
118 | case ALCHEMY_CPU_AU1500: | |
119 | case ALCHEMY_CPU_AU1100: | |
120 | alchemy_sleep_au1000(); | |
121 | break; | |
122 | case ALCHEMY_CPU_AU1550: | |
123 | case ALCHEMY_CPU_AU1200: | |
124 | alchemy_sleep_au1550(); | |
125 | break; | |
809f36c6 ML |
126 | case ALCHEMY_CPU_AU1300: |
127 | alchemy_sleep_au1300(); | |
128 | break; | |
2e93d1ec | 129 | } |
870168a0 ML |
130 | |
131 | restore_core_regs(); | |
564365b0 | 132 | } |