Commit | Line | Data |
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1da177e4 | 1 | /* |
c1dcb14e SS |
2 | * Copyright 2000, 2007-2008 MontaVista Software Inc. |
3 | * Author: MontaVista Software, Inc. <source@mvista.com | |
1da177e4 LT |
4 | * |
5 | * Updates to 2.6, Pete Popov, Embedded Alley Solutions, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | * | |
12 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
13 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
14 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
15 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
16 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
17 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
18 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
19 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
20 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
21 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License along | |
24 | * with this program; if not, write to the Free Software Foundation, Inc., | |
25 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
26 | */ | |
ce28f94c | 27 | |
1da177e4 | 28 | #include <linux/init.h> |
1da177e4 | 29 | #include <linux/ioport.h> |
efe29c0f | 30 | #include <linux/module.h> |
fcdb27ad | 31 | #include <linux/pm.h> |
1da177e4 | 32 | |
1da177e4 LT |
33 | #include <asm/mipsregs.h> |
34 | #include <asm/reboot.h> | |
1da177e4 LT |
35 | #include <asm/time.h> |
36 | ||
25b31cb1 | 37 | #include <au1000.h> |
25b31cb1 | 38 | |
1da177e4 LT |
39 | extern void __init board_setup(void); |
40 | extern void au1000_restart(char *); | |
41 | extern void au1000_halt(void); | |
42 | extern void au1000_power_off(void); | |
1da177e4 LT |
43 | extern void set_cpuspec(void); |
44 | ||
2925aba4 | 45 | void __init plat_mem_setup(void) |
1da177e4 LT |
46 | { |
47 | struct cpu_spec *sp; | |
c1dcb14e | 48 | unsigned long prid, cpufreq, bclk; |
1da177e4 LT |
49 | |
50 | set_cpuspec(); | |
51 | sp = cur_cpu_spec[0]; | |
52 | ||
7179380e ML |
53 | _machine_restart = au1000_restart; |
54 | _machine_halt = au1000_halt; | |
55 | pm_power_off = au1000_power_off; | |
56 | ||
1da177e4 LT |
57 | board_setup(); /* board specific setup */ |
58 | ||
59 | prid = read_c0_prid(); | |
758e285f SS |
60 | if (sp->cpu_pll_wo) |
61 | #ifdef CONFIG_SOC_AU1000_FREQUENCY | |
62 | cpufreq = CONFIG_SOC_AU1000_FREQUENCY / 1000000; | |
63 | #else | |
64 | cpufreq = 396; | |
65 | #endif | |
66 | else | |
67 | cpufreq = (au_readl(SYS_CPUPLL) & 0x3F) * 12; | |
68 | printk(KERN_INFO "(PRID %08lx) @ %ld MHz\n", prid, cpufreq); | |
1da177e4 | 69 | |
c1dcb14e | 70 | if (sp->cpu_bclk) { |
1da177e4 | 71 | /* Enable BCLK switching */ |
c1dcb14e SS |
72 | bclk = au_readl(SYS_POWERCTRL); |
73 | au_writel(bclk | 0x60, SYS_POWERCTRL); | |
74 | printk(KERN_INFO "BCLK switching enabled!\n"); | |
1da177e4 LT |
75 | } |
76 | ||
c1dcb14e SS |
77 | if (sp->cpu_od) |
78 | /* Various early Au1xx0 errata corrected by this */ | |
79 | set_c0_config(1 << 19); /* Set Config[OD] */ | |
80 | else | |
1da177e4 | 81 | /* Clear to obtain best system bus performance */ |
c1dcb14e | 82 | clear_c0_config(1 << 19); /* Clear Config[OD] */ |
1da177e4 | 83 | |
1da177e4 LT |
84 | /* IO/MEM resources. */ |
85 | set_io_port_base(0); | |
86 | ioport_resource.start = IOPORT_RESOURCE_START; | |
87 | ioport_resource.end = IOPORT_RESOURCE_END; | |
88 | iomem_resource.start = IOMEM_RESOURCE_START; | |
89 | iomem_resource.end = IOMEM_RESOURCE_END; | |
90 | ||
91 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S); | |
92 | au_writel(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL); | |
93 | au_sync(); | |
94 | while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S); | |
95 | au_writel(0, SYS_TOYTRIM); | |
1da177e4 LT |
96 | } |
97 | ||
1da177e4 LT |
98 | #if defined(CONFIG_64BIT_PHYS_ADDR) |
99 | /* This routine should be valid for all Au1x based boards */ | |
c3455b0e | 100 | phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) |
1da177e4 | 101 | { |
c1dcb14e | 102 | /* Don't fixup 36-bit addresses */ |
722b05a0 RB |
103 | if ((phys_addr >> 32) != 0) |
104 | return phys_addr; | |
1da177e4 LT |
105 | |
106 | #ifdef CONFIG_PCI | |
722b05a0 | 107 | { |
b87bb40b SS |
108 | u32 start = (u32)Au1500_PCI_MEM_START; |
109 | u32 end = (u32)Au1500_PCI_MEM_END; | |
722b05a0 | 110 | |
b87bb40b SS |
111 | /* Check for PCI memory window */ |
112 | if (phys_addr >= start && (phys_addr + size - 1) <= end) | |
722b05a0 RB |
113 | return (phys_t) |
114 | ((phys_addr - start) + Au1500_PCI_MEM_START); | |
1da177e4 LT |
115 | } |
116 | #endif | |
117 | ||
c1dcb14e SS |
118 | /* |
119 | * All Au1xx0 SOCs have a PCMCIA controller. | |
120 | * We setup our 32-bit pseudo addresses to be equal to the | |
121 | * 36-bit addr >> 4, to make it easier to check the address | |
1da177e4 | 122 | * and fix it. |
c1dcb14e | 123 | * The PCMCIA socket 0 physical attribute address is 0xF 4000 0000. |
1da177e4 | 124 | * The pseudo address we use is 0xF400 0000. Any address over |
c1dcb14e | 125 | * 0xF400 0000 is a PCMCIA pseudo address. |
1da177e4 | 126 | */ |
c1dcb14e | 127 | if ((phys_addr >= 0xF4000000) && (phys_addr < 0xFFFFFFFF)) |
1da177e4 | 128 | return (phys_t)(phys_addr << 4); |
1da177e4 LT |
129 | |
130 | /* default nop */ | |
131 | return phys_addr; | |
132 | } | |
efe29c0f | 133 | EXPORT_SYMBOL(__fixup_bigphys_addr); |
1da177e4 | 134 | #endif |