[deliverable/linux.git] / arch / mips / alchemy / common / time.c

/*
 * Copyright (C) 2008 Manuel Lauss <mano@roarinelk.homelinux.net>
 *
 * Previous incarnations were:
 * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com>
 * Copied and modified Carsten Langgaard's time.c
 *
 * Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
 *
 * ########################################################################
 *
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * ########################################################################
 *
 * Clocksource/event using the 32.768kHz-clocked Counter1 ('RTC' in the
 * databooks).  Firmware/Board init code must enable the counters in the
 * counter control register, otherwise the CP0 counter clocksource/event
 * will be installed instead (and use of 'wait' instruction is prohibited).
 */

#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>

#include <asm/processor.h>
#include <asm/time.h>
#include <asm/mach-au1x00/au1000.h>

/* 32kHz clock enabled and detected */
#define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)

static cycle_t au1x_counter1_read(struct clocksource *cs)
{
	return au_readl(SYS_RTCREAD);
}

static struct clocksource au1x_counter1_clocksource = {
	.name		= "alchemy-counter1",
	.read		= au1x_counter1_read,
	.mask		= CLOCKSOURCE_MASK(32),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
	.rating		= 100,
};

static int au1x_rtcmatch2_set_next_event(unsigned long delta,
					 struct clock_event_device *cd)
{
	delta += au_readl(SYS_RTCREAD);
	/* wait for register access */
	while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M21)
		;
	au_writel(delta, SYS_RTCMATCH2);
	au_sync();

	return 0;
}

static void au1x_rtcmatch2_set_mode(enum clock_event_mode mode,
				    struct clock_event_device *cd)
{
}

static irqreturn_t au1x_rtcmatch2_irq(int irq, void *dev_id)
{
	struct clock_event_device *cd = dev_id;
	cd->event_handler(cd);
	return IRQ_HANDLED;
}

static struct clock_event_device au1x_rtcmatch2_clockdev = {
	.name		= "rtcmatch2",
	.features	= CLOCK_EVT_FEAT_ONESHOT,
	.rating		= 100,
	.irq		= AU1000_RTC_MATCH2_INT,
	.set_next_event	= au1x_rtcmatch2_set_next_event,
	.set_mode	= au1x_rtcmatch2_set_mode,
	.cpumask	= CPU_MASK_ALL_PTR,
};

static struct irqaction au1x_rtcmatch2_irqaction = {
	.handler	= au1x_rtcmatch2_irq,
	.flags		= IRQF_DISABLED | IRQF_TIMER,
	.name		= "timer",
	.dev_id		= &au1x_rtcmatch2_clockdev,
};

void __init plat_time_init(void)
{
	struct clock_event_device *cd = &au1x_rtcmatch2_clockdev;
	unsigned long t;

	/* Check if firmware (YAMON, ...) has enabled 32kHz and clock
	 * has been detected.  If so install the rtcmatch2 clocksource,
	 * otherwise don't bother.  Note that both bits being set is by
	 * no means a definite guarantee that the counters actually work
	 * (the 32S bit seems to be stuck set to 1 once a single clock-
	 * edge is detected, hence the timeouts).
	 */
	if (CNTR_OK != (au_readl(SYS_COUNTER_CNTRL) & CNTR_OK))
		goto cntr_err;

	/*
	 * setup counter 1 (RTC) to tick at full speed
	 */
	t = 0xffffff;
	while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S) && --t)
		asm volatile ("nop");
	if (!t)
		goto cntr_err;

	au_writel(0, SYS_RTCTRIM);	/* 32.768 kHz */
	au_sync();

	t = 0xffffff;
	while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && --t)
		asm volatile ("nop");
	if (!t)
		goto cntr_err;
	au_writel(0, SYS_RTCWRITE);
	au_sync();

	t = 0xffffff;
	while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && --t)
		asm volatile ("nop");
	if (!t)
		goto cntr_err;

	/* register counter1 clocksource and event device */
	clocksource_set_clock(&au1x_counter1_clocksource, 32768);
	clocksource_register(&au1x_counter1_clocksource);

	cd->shift = 32;
	cd->mult = div_sc(32768, NSEC_PER_SEC, cd->shift);
	cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd);
	cd->min_delta_ns = clockevent_delta2ns(8, cd);	/* ~0.25ms */
	clockevents_register_device(cd);
	setup_irq(AU1000_RTC_MATCH2_INT, &au1x_rtcmatch2_irqaction);

	printk(KERN_INFO "Alchemy clocksource installed\n");

	return;

cntr_err:
	/*
	 * MIPS kernel assigns 'au1k_wait' to 'cpu_wait' before this
	 * function is called.  Because the Alchemy counters are unusable
	 * the C0 timekeeping code is installed and use of the 'wait'
	 * instruction must be prohibited, which is done most easily by
	 * assigning NULL to cpu_wait.
	 */
	cpu_wait = NULL;
	r4k_clockevent_init();
	init_r4k_clocksource();
}
Commit	Line	Data
1da177e4	1	/*
0c694de1	2	* Copyright (C) 2008 Manuel Lauss <mano@roarinelk.homelinux.net>
1da177e4	3	*
0c694de1	4	* Previous incarnations were:
01675095	5	* Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com>
1da177e4 LT	6	* Copied and modified Carsten Langgaard's time.c
	7	*
	8	* Carsten Langgaard, carstenl@mips.com
	9	* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
	10	*
	11	* ########################################################################
	12	*
	13	* This program is free software; you can distribute it and/or modify it
	14	* under the terms of the GNU General Public License (Version 2) as
	15	* published by the Free Software Foundation.
	16	*
	17	* This program is distributed in the hope it will be useful, but WITHOUT
	18	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	19	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	20	* for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License along
	23	* with this program; if not, write to the Free Software Foundation, Inc.,
	24	* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
	25	*
	26	* ########################################################################
	27	*
0c694de1 ML	28	* Clocksource/event using the 32.768kHz-clocked Counter1 ('RTC' in the
	29	* databooks). Firmware/Board init code must enable the counters in the
	30	* counter control register, otherwise the CP0 counter clocksource/event
	31	* will be installed instead (and use of 'wait' instruction is prohibited).
1da177e4 LT	32	*/
1da177e4 LT	33
0c694de1 ML	34	#include <linux/clockchips.h>
	35	#include <linux/clocksource.h>
	36	#include <linux/interrupt.h>
1da177e4	37	#include <linux/spinlock.h>
1da177e4	38
2882b0c6	39	#include <asm/processor.h>
1da177e4	40	#include <asm/time.h>
1da177e4 LT	41	#include <asm/mach-au1x00/au1000.h>
1da177e4 LT	42
0c694de1 ML	43	/* 32kHz clock enabled and detected */
0c694de1 ML	44	#define CNTR_OK (SYS_CNTRL_E0 \| SYS_CNTRL_32S)
1da177e4	45
ad058e95	46	static cycle_t au1x_counter1_read(struct clocksource *cs)
0c694de1 ML	47	{
	48	return au_readl(SYS_RTCREAD);
	49	}
	50
	51	static struct clocksource au1x_counter1_clocksource = {
	52	.name = "alchemy-counter1",
	53	.read = au1x_counter1_read,
	54	.mask = CLOCKSOURCE_MASK(32),
	55	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	56	.rating = 100,
	57	};
	58
	59	static int au1x_rtcmatch2_set_next_event(unsigned long delta,
	60	struct clock_event_device *cd)
	61	{
	62	delta += au_readl(SYS_RTCREAD);
	63	/* wait for register access */
	64	while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M21)
	65	;
	66	au_writel(delta, SYS_RTCMATCH2);
	67	au_sync();
	68
	69	return 0;
	70	}
	71
	72	static void au1x_rtcmatch2_set_mode(enum clock_event_mode mode,
	73	struct clock_event_device *cd)
	74	{
	75	}
	76
	77	static irqreturn_t au1x_rtcmatch2_irq(int irq, void *dev_id)
	78	{
	79	struct clock_event_device *cd = dev_id;
	80	cd->event_handler(cd);
	81	return IRQ_HANDLED;
	82	}
	83
	84	static struct clock_event_device au1x_rtcmatch2_clockdev = {
	85	.name = "rtcmatch2",
	86	.features = CLOCK_EVT_FEAT_ONESHOT,
	87	.rating = 100,
	88	.irq = AU1000_RTC_MATCH2_INT,
	89	.set_next_event = au1x_rtcmatch2_set_next_event,
	90	.set_mode = au1x_rtcmatch2_set_mode,
2d2eca4d	91	.cpumask = CPU_MASK_ALL_PTR,
0c694de1 ML	92	};
	93
	94	static struct irqaction au1x_rtcmatch2_irqaction = {
	95	.handler = au1x_rtcmatch2_irq,
	96	.flags = IRQF_DISABLED \| IRQF_TIMER,
	97	.name = "timer",
	98	.dev_id = &au1x_rtcmatch2_clockdev,
	99	};
	100
bc2f2a24	101	void __init plat_time_init(void)
1da177e4	102	{
0c694de1 ML	103	struct clock_event_device *cd = &au1x_rtcmatch2_clockdev;
0c694de1 ML	104	unsigned long t;
1da177e4	105
0c694de1 ML	106	/* Check if firmware (YAMON, ...) has enabled 32kHz and clock
	107	* has been detected. If so install the rtcmatch2 clocksource,
	108	* otherwise don't bother. Note that both bits being set is by
	109	* no means a definite guarantee that the counters actually work
	110	* (the 32S bit seems to be stuck set to 1 once a single clock-
	111	* edge is detected, hence the timeouts).
1da177e4	112	*/
0c694de1 ML	113	if (CNTR_OK != (au_readl(SYS_COUNTER_CNTRL) & CNTR_OK))
0c694de1 ML	114	goto cntr_err;
1da177e4	115
0c694de1 ML	116	/*
	117	* setup counter 1 (RTC) to tick at full speed
	118	*/
	119	t = 0xffffff;
4b0d3f5c	120	while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S) && --t)
0c694de1 ML	121	asm volatile ("nop");
	122	if (!t)
	123	goto cntr_err;
1da177e4	124
0c694de1 ML	125	au_writel(0, SYS_RTCTRIM); /* 32.768 kHz */
0c694de1 ML	126	au_sync();
1da177e4	127
0c694de1	128	t = 0xffffff;
4b0d3f5c	129	while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && --t)
0c694de1 ML	130	asm volatile ("nop");
	131	if (!t)
	132	goto cntr_err;
	133	au_writel(0, SYS_RTCWRITE);
	134	au_sync();
1da177e4	135
0c694de1	136	t = 0xffffff;
4b0d3f5c	137	while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && --t)
0c694de1 ML	138	asm volatile ("nop");
	139	if (!t)
	140	goto cntr_err;
	141
	142	/* register counter1 clocksource and event device */
	143	clocksource_set_clock(&au1x_counter1_clocksource, 32768);
	144	clocksource_register(&au1x_counter1_clocksource);
	145
	146	cd->shift = 32;
	147	cd->mult = div_sc(32768, NSEC_PER_SEC, cd->shift);
	148	cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd);
	149	cd->min_delta_ns = clockevent_delta2ns(8, cd); /* ~0.25ms */
	150	clockevents_register_device(cd);
	151	setup_irq(AU1000_RTC_MATCH2_INT, &au1x_rtcmatch2_irqaction);
	152
	153	printk(KERN_INFO "Alchemy clocksource installed\n");
	154
0c694de1 ML	155	return;
	156
	157	cntr_err:
2882b0c6 ML	158	/*
	159	* MIPS kernel assigns 'au1k_wait' to 'cpu_wait' before this
	160	* function is called. Because the Alchemy counters are unusable
	161	* the C0 timekeeping code is installed and use of the 'wait'
	162	* instruction must be prohibited, which is done most easily by
	163	* assigning NULL to cpu_wait.
	164	*/
	165	cpu_wait = NULL;
0c694de1 ML	166	r4k_clockevent_init();
0c694de1 ML	167	init_r4k_clocksource();
1da177e4	168	}