Commit | Line | Data |
---|---|---|
27dd65ac | 1 | /* |
851d4f5d | 2 | * DBAu1000/1500/1100 PBAu1100/1500 board support |
27dd65ac | 3 | * |
7c4b24da ML |
4 | * Copyright 2000, 2008 MontaVista Software Inc. |
5 | * Author: MontaVista Software, Inc. <source@mvista.com> | |
27dd65ac ML |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
20 | */ | |
21 | ||
6b1889c1 | 22 | #include <linux/clk.h> |
7c4b24da ML |
23 | #include <linux/dma-mapping.h> |
24 | #include <linux/gpio.h> | |
27dd65ac | 25 | #include <linux/init.h> |
b2ce305d | 26 | #include <linux/interrupt.h> |
c9af5144 ML |
27 | #include <linux/leds.h> |
28 | #include <linux/mmc/host.h> | |
29 | #include <linux/module.h> | |
27dd65ac | 30 | #include <linux/platform_device.h> |
7c4b24da | 31 | #include <linux/pm.h> |
2a32daf1 ML |
32 | #include <linux/spi/spi.h> |
33 | #include <linux/spi/spi_gpio.h> | |
34 | #include <linux/spi/ads7846.h> | |
b2ce305d | 35 | #include <asm/mach-au1x00/au1000.h> |
832f5dac | 36 | #include <asm/mach-au1x00/gpio-au1000.h> |
b2ce305d | 37 | #include <asm/mach-au1x00/au1000_dma.h> |
c9af5144 | 38 | #include <asm/mach-au1x00/au1100_mmc.h> |
206aa6cd | 39 | #include <asm/mach-db1x00/bcsr.h> |
7c4b24da ML |
40 | #include <asm/reboot.h> |
41 | #include <prom.h> | |
42 | #include "platform.h" | |
27dd65ac | 43 | |
f59c811f ML |
44 | #define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT) |
45 | ||
970e268d | 46 | const char *get_system_type(void); |
7517de34 | 47 | |
970e268d | 48 | int __init db1000_board_setup(void) |
f59c811f | 49 | { |
970e268d ML |
50 | /* initialize board register space */ |
51 | bcsr_init(DB1000_BCSR_PHYS_ADDR, | |
52 | DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS); | |
53 | ||
f59c811f ML |
54 | switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) { |
55 | case BCSR_WHOAMI_DB1000: | |
f59c811f | 56 | case BCSR_WHOAMI_DB1500: |
f59c811f | 57 | case BCSR_WHOAMI_DB1100: |
851d4f5d ML |
58 | case BCSR_WHOAMI_PB1500: |
59 | case BCSR_WHOAMI_PB1500R2: | |
851d4f5d | 60 | case BCSR_WHOAMI_PB1100: |
970e268d ML |
61 | pr_info("AMD Alchemy %s Board\n", get_system_type()); |
62 | return 0; | |
f59c811f | 63 | } |
970e268d | 64 | return -ENODEV; |
f59c811f ML |
65 | } |
66 | ||
f869d42e | 67 | static int db1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) |
7517de34 ML |
68 | { |
69 | if ((slot < 12) || (slot > 13) || pin == 0) | |
70 | return -1; | |
71 | if (slot == 12) | |
72 | return (pin == 1) ? AU1500_PCI_INTA : 0xff; | |
73 | if (slot == 13) { | |
74 | switch (pin) { | |
75 | case 1: return AU1500_PCI_INTA; | |
76 | case 2: return AU1500_PCI_INTB; | |
77 | case 3: return AU1500_PCI_INTC; | |
78 | case 4: return AU1500_PCI_INTD; | |
79 | } | |
80 | } | |
81 | return -1; | |
82 | } | |
7517de34 | 83 | |
7517de34 ML |
84 | static struct resource alchemy_pci_host_res[] = { |
85 | [0] = { | |
86 | .start = AU1500_PCI_PHYS_ADDR, | |
87 | .end = AU1500_PCI_PHYS_ADDR + 0xfff, | |
88 | .flags = IORESOURCE_MEM, | |
89 | }, | |
90 | }; | |
91 | ||
f869d42e ML |
92 | static struct alchemy_pci_platdata db1500_pci_pd = { |
93 | .board_map_irq = db1500_map_pci_irq, | |
7517de34 ML |
94 | }; |
95 | ||
f869d42e ML |
96 | static struct platform_device db1500_pci_host_dev = { |
97 | .dev.platform_data = &db1500_pci_pd, | |
7517de34 ML |
98 | .name = "alchemy-pci", |
99 | .id = 0, | |
100 | .num_resources = ARRAY_SIZE(alchemy_pci_host_res), | |
101 | .resource = alchemy_pci_host_res, | |
102 | }; | |
103 | ||
970e268d | 104 | int __init db1500_pci_setup(void) |
7517de34 | 105 | { |
970e268d | 106 | return platform_device_register(&db1500_pci_host_dev); |
7517de34 | 107 | } |
f59c811f | 108 | |
37663860 ML |
109 | static struct resource au1100_lcd_resources[] = { |
110 | [0] = { | |
111 | .start = AU1100_LCD_PHYS_ADDR, | |
112 | .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1, | |
113 | .flags = IORESOURCE_MEM, | |
114 | }, | |
115 | [1] = { | |
116 | .start = AU1100_LCD_INT, | |
117 | .end = AU1100_LCD_INT, | |
118 | .flags = IORESOURCE_IRQ, | |
119 | } | |
120 | }; | |
121 | ||
122 | static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32); | |
123 | ||
124 | static struct platform_device au1100_lcd_device = { | |
125 | .name = "au1100-lcd", | |
126 | .id = 0, | |
127 | .dev = { | |
128 | .dma_mask = &au1100_lcd_dmamask, | |
129 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
130 | }, | |
131 | .num_resources = ARRAY_SIZE(au1100_lcd_resources), | |
132 | .resource = au1100_lcd_resources, | |
133 | }; | |
37663860 | 134 | |
b2ce305d ML |
135 | static struct resource alchemy_ac97c_res[] = { |
136 | [0] = { | |
137 | .start = AU1000_AC97_PHYS_ADDR, | |
138 | .end = AU1000_AC97_PHYS_ADDR + 0xfff, | |
139 | .flags = IORESOURCE_MEM, | |
140 | }, | |
141 | [1] = { | |
142 | .start = DMA_ID_AC97C_TX, | |
143 | .end = DMA_ID_AC97C_TX, | |
144 | .flags = IORESOURCE_DMA, | |
145 | }, | |
146 | [2] = { | |
147 | .start = DMA_ID_AC97C_RX, | |
148 | .end = DMA_ID_AC97C_RX, | |
149 | .flags = IORESOURCE_DMA, | |
150 | }, | |
151 | }; | |
152 | ||
153 | static struct platform_device alchemy_ac97c_dev = { | |
154 | .name = "alchemy-ac97c", | |
155 | .id = -1, | |
156 | .resource = alchemy_ac97c_res, | |
157 | .num_resources = ARRAY_SIZE(alchemy_ac97c_res), | |
158 | }; | |
159 | ||
160 | static struct platform_device alchemy_ac97c_dma_dev = { | |
161 | .name = "alchemy-pcm-dma", | |
162 | .id = 0, | |
163 | }; | |
164 | ||
165 | static struct platform_device db1x00_codec_dev = { | |
166 | .name = "ac97-codec", | |
167 | .id = -1, | |
168 | }; | |
169 | ||
170 | static struct platform_device db1x00_audio_dev = { | |
171 | .name = "db1000-audio", | |
172 | }; | |
173 | ||
c9af5144 ML |
174 | /******************************************************************************/ |
175 | ||
176 | static irqreturn_t db1100_mmc_cd(int irq, void *ptr) | |
177 | { | |
178 | void (*mmc_cd)(struct mmc_host *, unsigned long); | |
179 | /* link against CONFIG_MMC=m */ | |
180 | mmc_cd = symbol_get(mmc_detect_change); | |
181 | mmc_cd(ptr, msecs_to_jiffies(500)); | |
182 | symbol_put(mmc_detect_change); | |
183 | ||
184 | return IRQ_HANDLED; | |
185 | } | |
186 | ||
187 | static int db1100_mmc_cd_setup(void *mmc_host, int en) | |
188 | { | |
851d4f5d ML |
189 | int ret = 0, irq; |
190 | ||
191 | if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100) | |
192 | irq = AU1100_GPIO19_INT; | |
193 | else | |
194 | irq = AU1100_GPIO14_INT; /* PB1100 SD0 CD# */ | |
c9af5144 ML |
195 | |
196 | if (en) { | |
851d4f5d ML |
197 | irq_set_irq_type(irq, IRQ_TYPE_EDGE_BOTH); |
198 | ret = request_irq(irq, db1100_mmc_cd, 0, | |
c9af5144 ML |
199 | "sd0_cd", mmc_host); |
200 | } else | |
851d4f5d | 201 | free_irq(irq, mmc_host); |
c9af5144 ML |
202 | return ret; |
203 | } | |
204 | ||
205 | static int db1100_mmc1_cd_setup(void *mmc_host, int en) | |
206 | { | |
851d4f5d ML |
207 | int ret = 0, irq; |
208 | ||
209 | if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100) | |
210 | irq = AU1100_GPIO20_INT; | |
211 | else | |
212 | irq = AU1100_GPIO15_INT; /* PB1100 SD1 CD# */ | |
c9af5144 ML |
213 | |
214 | if (en) { | |
851d4f5d ML |
215 | irq_set_irq_type(irq, IRQ_TYPE_EDGE_BOTH); |
216 | ret = request_irq(irq, db1100_mmc_cd, 0, | |
c9af5144 ML |
217 | "sd1_cd", mmc_host); |
218 | } else | |
851d4f5d | 219 | free_irq(irq, mmc_host); |
c9af5144 ML |
220 | return ret; |
221 | } | |
222 | ||
223 | static int db1100_mmc_card_readonly(void *mmc_host) | |
224 | { | |
225 | /* testing suggests that this bit is inverted */ | |
226 | return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 0 : 1; | |
227 | } | |
228 | ||
229 | static int db1100_mmc_card_inserted(void *mmc_host) | |
230 | { | |
231 | return !alchemy_gpio_get_value(19); | |
232 | } | |
233 | ||
234 | static void db1100_mmc_set_power(void *mmc_host, int state) | |
235 | { | |
851d4f5d ML |
236 | int bit; |
237 | ||
238 | if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100) | |
239 | bit = BCSR_BOARD_SD0PWR; | |
240 | else | |
241 | bit = BCSR_BOARD_PB1100_SD0PWR; | |
242 | ||
c9af5144 | 243 | if (state) { |
851d4f5d | 244 | bcsr_mod(BCSR_BOARD, 0, bit); |
c9af5144 ML |
245 | msleep(400); /* stabilization time */ |
246 | } else | |
851d4f5d | 247 | bcsr_mod(BCSR_BOARD, bit, 0); |
c9af5144 ML |
248 | } |
249 | ||
250 | static void db1100_mmcled_set(struct led_classdev *led, enum led_brightness b) | |
251 | { | |
252 | if (b != LED_OFF) | |
253 | bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0); | |
254 | else | |
255 | bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0); | |
256 | } | |
257 | ||
258 | static struct led_classdev db1100_mmc_led = { | |
70342287 | 259 | .brightness_set = db1100_mmcled_set, |
c9af5144 ML |
260 | }; |
261 | ||
262 | static int db1100_mmc1_card_readonly(void *mmc_host) | |
263 | { | |
264 | return (bcsr_read(BCSR_BOARD) & BCSR_BOARD_SD1WP) ? 1 : 0; | |
265 | } | |
266 | ||
267 | static int db1100_mmc1_card_inserted(void *mmc_host) | |
268 | { | |
269 | return !alchemy_gpio_get_value(20); | |
270 | } | |
271 | ||
272 | static void db1100_mmc1_set_power(void *mmc_host, int state) | |
273 | { | |
851d4f5d ML |
274 | int bit; |
275 | ||
276 | if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100) | |
277 | bit = BCSR_BOARD_SD1PWR; | |
278 | else | |
279 | bit = BCSR_BOARD_PB1100_SD1PWR; | |
280 | ||
c9af5144 | 281 | if (state) { |
851d4f5d | 282 | bcsr_mod(BCSR_BOARD, 0, bit); |
c9af5144 ML |
283 | msleep(400); /* stabilization time */ |
284 | } else | |
851d4f5d | 285 | bcsr_mod(BCSR_BOARD, bit, 0); |
c9af5144 ML |
286 | } |
287 | ||
288 | static void db1100_mmc1led_set(struct led_classdev *led, enum led_brightness b) | |
289 | { | |
290 | if (b != LED_OFF) | |
291 | bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0); | |
292 | else | |
293 | bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1); | |
294 | } | |
295 | ||
296 | static struct led_classdev db1100_mmc1_led = { | |
70342287 | 297 | .brightness_set = db1100_mmc1led_set, |
c9af5144 ML |
298 | }; |
299 | ||
300 | static struct au1xmmc_platform_data db1100_mmc_platdata[2] = { | |
301 | [0] = { | |
302 | .cd_setup = db1100_mmc_cd_setup, | |
303 | .set_power = db1100_mmc_set_power, | |
304 | .card_inserted = db1100_mmc_card_inserted, | |
305 | .card_readonly = db1100_mmc_card_readonly, | |
306 | .led = &db1100_mmc_led, | |
307 | }, | |
308 | [1] = { | |
309 | .cd_setup = db1100_mmc1_cd_setup, | |
310 | .set_power = db1100_mmc1_set_power, | |
311 | .card_inserted = db1100_mmc1_card_inserted, | |
312 | .card_readonly = db1100_mmc1_card_readonly, | |
313 | .led = &db1100_mmc1_led, | |
314 | }, | |
315 | }; | |
316 | ||
317 | static struct resource au1100_mmc0_resources[] = { | |
318 | [0] = { | |
319 | .start = AU1100_SD0_PHYS_ADDR, | |
320 | .end = AU1100_SD0_PHYS_ADDR + 0xfff, | |
321 | .flags = IORESOURCE_MEM, | |
322 | }, | |
323 | [1] = { | |
324 | .start = AU1100_SD_INT, | |
325 | .end = AU1100_SD_INT, | |
326 | .flags = IORESOURCE_IRQ, | |
327 | }, | |
328 | [2] = { | |
329 | .start = DMA_ID_SD0_TX, | |
330 | .end = DMA_ID_SD0_TX, | |
331 | .flags = IORESOURCE_DMA, | |
332 | }, | |
333 | [3] = { | |
334 | .start = DMA_ID_SD0_RX, | |
335 | .end = DMA_ID_SD0_RX, | |
336 | .flags = IORESOURCE_DMA, | |
337 | } | |
338 | }; | |
339 | ||
70342287 | 340 | static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32); |
c9af5144 ML |
341 | |
342 | static struct platform_device db1100_mmc0_dev = { | |
343 | .name = "au1xxx-mmc", | |
344 | .id = 0, | |
345 | .dev = { | |
346 | .dma_mask = &au1xxx_mmc_dmamask, | |
347 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
348 | .platform_data = &db1100_mmc_platdata[0], | |
349 | }, | |
350 | .num_resources = ARRAY_SIZE(au1100_mmc0_resources), | |
351 | .resource = au1100_mmc0_resources, | |
352 | }; | |
353 | ||
354 | static struct resource au1100_mmc1_res[] = { | |
355 | [0] = { | |
356 | .start = AU1100_SD1_PHYS_ADDR, | |
357 | .end = AU1100_SD1_PHYS_ADDR + 0xfff, | |
358 | .flags = IORESOURCE_MEM, | |
359 | }, | |
360 | [1] = { | |
361 | .start = AU1100_SD_INT, | |
362 | .end = AU1100_SD_INT, | |
363 | .flags = IORESOURCE_IRQ, | |
364 | }, | |
365 | [2] = { | |
366 | .start = DMA_ID_SD1_TX, | |
367 | .end = DMA_ID_SD1_TX, | |
368 | .flags = IORESOURCE_DMA, | |
369 | }, | |
370 | [3] = { | |
371 | .start = DMA_ID_SD1_RX, | |
372 | .end = DMA_ID_SD1_RX, | |
373 | .flags = IORESOURCE_DMA, | |
374 | } | |
375 | }; | |
376 | ||
377 | static struct platform_device db1100_mmc1_dev = { | |
378 | .name = "au1xxx-mmc", | |
379 | .id = 1, | |
380 | .dev = { | |
381 | .dma_mask = &au1xxx_mmc_dmamask, | |
382 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
383 | .platform_data = &db1100_mmc_platdata[1], | |
384 | }, | |
385 | .num_resources = ARRAY_SIZE(au1100_mmc1_res), | |
386 | .resource = au1100_mmc1_res, | |
387 | }; | |
388 | ||
e734ae13 ML |
389 | /******************************************************************************/ |
390 | ||
391 | static void db1000_irda_set_phy_mode(int mode) | |
392 | { | |
393 | unsigned short mask = BCSR_RESETS_IRDA_MODE_MASK | BCSR_RESETS_FIR_SEL; | |
394 | ||
395 | switch (mode) { | |
396 | case AU1000_IRDA_PHY_MODE_OFF: | |
397 | bcsr_mod(BCSR_RESETS, mask, BCSR_RESETS_IRDA_MODE_OFF); | |
398 | break; | |
399 | case AU1000_IRDA_PHY_MODE_SIR: | |
400 | bcsr_mod(BCSR_RESETS, mask, BCSR_RESETS_IRDA_MODE_FULL); | |
401 | break; | |
402 | case AU1000_IRDA_PHY_MODE_FIR: | |
403 | bcsr_mod(BCSR_RESETS, mask, BCSR_RESETS_IRDA_MODE_FULL | | |
404 | BCSR_RESETS_FIR_SEL); | |
405 | break; | |
406 | } | |
407 | } | |
408 | ||
409 | static struct au1k_irda_platform_data db1000_irda_platdata = { | |
410 | .set_phy_mode = db1000_irda_set_phy_mode, | |
411 | }; | |
412 | ||
413 | static struct resource au1000_irda_res[] = { | |
414 | [0] = { | |
415 | .start = AU1000_IRDA_PHYS_ADDR, | |
416 | .end = AU1000_IRDA_PHYS_ADDR + 0x0fff, | |
417 | .flags = IORESOURCE_MEM, | |
418 | }, | |
419 | [1] = { | |
420 | .start = AU1000_IRDA_TX_INT, | |
421 | .end = AU1000_IRDA_TX_INT, | |
422 | .flags = IORESOURCE_IRQ, | |
423 | }, | |
424 | [2] = { | |
425 | .start = AU1000_IRDA_RX_INT, | |
426 | .end = AU1000_IRDA_RX_INT, | |
427 | .flags = IORESOURCE_IRQ, | |
428 | }, | |
429 | }; | |
430 | ||
431 | static struct platform_device db1000_irda_dev = { | |
432 | .name = "au1000-irda", | |
433 | .id = -1, | |
434 | .dev = { | |
435 | .platform_data = &db1000_irda_platdata, | |
436 | }, | |
437 | .resource = au1000_irda_res, | |
438 | .num_resources = ARRAY_SIZE(au1000_irda_res), | |
439 | }; | |
c9af5144 | 440 | |
2a32daf1 ML |
441 | /******************************************************************************/ |
442 | ||
443 | static struct ads7846_platform_data db1100_touch_pd = { | |
444 | .model = 7846, | |
445 | .vref_mv = 3300, | |
446 | .gpio_pendown = 21, | |
447 | }; | |
448 | ||
449 | static struct spi_gpio_platform_data db1100_spictl_pd = { | |
450 | .sck = 209, | |
451 | .mosi = 208, | |
452 | .miso = 207, | |
453 | .num_chipselect = 1, | |
454 | }; | |
455 | ||
456 | static struct spi_board_info db1100_spi_info[] __initdata = { | |
457 | [0] = { | |
458 | .modalias = "ads7846", | |
459 | .max_speed_hz = 3250000, | |
460 | .bus_num = 0, | |
461 | .chip_select = 0, | |
462 | .mode = 0, | |
463 | .irq = AU1100_GPIO21_INT, | |
464 | .platform_data = &db1100_touch_pd, | |
70342287 | 465 | .controller_data = (void *)210, /* for spi_gpio: CS# GPIO210 */ |
2a32daf1 ML |
466 | }, |
467 | }; | |
468 | ||
469 | static struct platform_device db1100_spi_dev = { | |
470 | .name = "spi_gpio", | |
471 | .id = 0, | |
472 | .dev = { | |
473 | .platform_data = &db1100_spictl_pd, | |
474 | }, | |
475 | }; | |
476 | ||
477 | ||
f59c811f ML |
478 | static struct platform_device *db1x00_devs[] = { |
479 | &db1x00_codec_dev, | |
480 | &alchemy_ac97c_dma_dev, | |
481 | &alchemy_ac97c_dev, | |
482 | &db1x00_audio_dev, | |
483 | }; | |
484 | ||
e734ae13 ML |
485 | static struct platform_device *db1000_devs[] = { |
486 | &db1000_irda_dev, | |
487 | }; | |
488 | ||
f59c811f ML |
489 | static struct platform_device *db1100_devs[] = { |
490 | &au1100_lcd_device, | |
c9af5144 ML |
491 | &db1100_mmc0_dev, |
492 | &db1100_mmc1_dev, | |
e734ae13 | 493 | &db1000_irda_dev, |
f59c811f ML |
494 | }; |
495 | ||
970e268d | 496 | int __init db1000_dev_setup(void) |
27dd65ac | 497 | { |
f59c811f | 498 | int board = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); |
851d4f5d | 499 | int c0, c1, d0, d1, s0, s1, flashsize = 32, twosocks = 1; |
2a32daf1 | 500 | unsigned long pfc; |
6b1889c1 | 501 | struct clk *c, *p; |
f59c811f ML |
502 | |
503 | if (board == BCSR_WHOAMI_DB1500) { | |
504 | c0 = AU1500_GPIO2_INT; | |
505 | c1 = AU1500_GPIO5_INT; | |
e34b6fcf ML |
506 | d0 = 0; /* GPIO number, NOT irq! */ |
507 | d1 = 3; /* GPIO number, NOT irq! */ | |
f59c811f ML |
508 | s0 = AU1500_GPIO1_INT; |
509 | s1 = AU1500_GPIO4_INT; | |
510 | } else if (board == BCSR_WHOAMI_DB1100) { | |
511 | c0 = AU1100_GPIO2_INT; | |
512 | c1 = AU1100_GPIO5_INT; | |
e34b6fcf ML |
513 | d0 = 0; /* GPIO number, NOT irq! */ |
514 | d1 = 3; /* GPIO number, NOT irq! */ | |
f59c811f ML |
515 | s0 = AU1100_GPIO1_INT; |
516 | s1 = AU1100_GPIO4_INT; | |
c9af5144 | 517 | |
4294ad1c ML |
518 | gpio_request(19, "sd0_cd"); |
519 | gpio_request(20, "sd1_cd"); | |
c9af5144 ML |
520 | gpio_direction_input(19); /* sd0 cd# */ |
521 | gpio_direction_input(20); /* sd1 cd# */ | |
2a32daf1 ML |
522 | |
523 | /* spi_gpio on SSI0 pins */ | |
1d09de7d | 524 | pfc = alchemy_rdsys(AU1000_SYS_PINFUNC); |
2a32daf1 | 525 | pfc |= (1 << 0); /* SSI0 pins as GPIOs */ |
1d09de7d | 526 | alchemy_wrsys(pfc, AU1000_SYS_PINFUNC); |
2a32daf1 ML |
527 | |
528 | spi_register_board_info(db1100_spi_info, | |
529 | ARRAY_SIZE(db1100_spi_info)); | |
c9af5144 | 530 | |
6b1889c1 ML |
531 | /* link LCD clock to AUXPLL */ |
532 | p = clk_get(NULL, "auxpll_clk"); | |
533 | c = clk_get(NULL, "lcd_intclk"); | |
534 | if (!IS_ERR(c) && !IS_ERR(p)) { | |
535 | clk_set_parent(c, p); | |
536 | clk_set_rate(c, clk_get_rate(p)); | |
537 | } | |
538 | if (!IS_ERR(c)) | |
539 | clk_put(c); | |
540 | if (!IS_ERR(p)) | |
541 | clk_put(p); | |
542 | ||
f59c811f | 543 | platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs)); |
851d4f5d | 544 | platform_device_register(&db1100_spi_dev); |
f59c811f ML |
545 | } else if (board == BCSR_WHOAMI_DB1000) { |
546 | c0 = AU1000_GPIO2_INT; | |
547 | c1 = AU1000_GPIO5_INT; | |
e34b6fcf ML |
548 | d0 = 0; /* GPIO number, NOT irq! */ |
549 | d1 = 3; /* GPIO number, NOT irq! */ | |
f59c811f ML |
550 | s0 = AU1000_GPIO1_INT; |
551 | s1 = AU1000_GPIO4_INT; | |
e734ae13 | 552 | platform_add_devices(db1000_devs, ARRAY_SIZE(db1000_devs)); |
851d4f5d ML |
553 | } else if ((board == BCSR_WHOAMI_PB1500) || |
554 | (board == BCSR_WHOAMI_PB1500R2)) { | |
555 | c0 = AU1500_GPIO203_INT; | |
e34b6fcf | 556 | d0 = 1; /* GPIO number, NOT irq! */ |
851d4f5d ML |
557 | s0 = AU1500_GPIO202_INT; |
558 | twosocks = 0; | |
559 | flashsize = 64; | |
560 | /* RTC and daughtercard irqs */ | |
561 | irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_LOW); | |
562 | irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW); | |
563 | /* EPSON S1D13806 0x1b000000 | |
70342287 | 564 | * SRAM 1MB/2MB 0x1a000000 |
851d4f5d ML |
565 | * DS1693 RTC 0x0c000000 |
566 | */ | |
567 | } else if (board == BCSR_WHOAMI_PB1100) { | |
568 | c0 = AU1100_GPIO11_INT; | |
e34b6fcf | 569 | d0 = 9; /* GPIO number, NOT irq! */ |
851d4f5d ML |
570 | s0 = AU1100_GPIO10_INT; |
571 | twosocks = 0; | |
572 | flashsize = 64; | |
573 | /* pendown, rtc, daughtercard irqs */ | |
574 | irq_set_irq_type(AU1100_GPIO8_INT, IRQ_TYPE_LEVEL_LOW); | |
575 | irq_set_irq_type(AU1100_GPIO12_INT, IRQ_TYPE_LEVEL_LOW); | |
576 | irq_set_irq_type(AU1100_GPIO13_INT, IRQ_TYPE_LEVEL_LOW); | |
577 | /* EPSON S1D13806 0x1b000000 | |
70342287 | 578 | * SRAM 1MB/2MB 0x1a000000 |
851d4f5d ML |
579 | * DiskOnChip 0x0d000000 |
580 | * DS1693 RTC 0x0c000000 | |
581 | */ | |
582 | platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs)); | |
f59c811f ML |
583 | } else |
584 | return 0; /* unknown board, no further dev setup to do */ | |
585 | ||
f59c811f | 586 | irq_set_irq_type(c0, IRQ_TYPE_LEVEL_LOW); |
f59c811f | 587 | irq_set_irq_type(s0, IRQ_TYPE_LEVEL_LOW); |
7c4b24da | 588 | |
7cc2e272 ML |
589 | db1x_register_pcmcia_socket( |
590 | AU1000_PCMCIA_ATTR_PHYS_ADDR, | |
591 | AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, | |
592 | AU1000_PCMCIA_MEM_PHYS_ADDR, | |
593 | AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, | |
594 | AU1000_PCMCIA_IO_PHYS_ADDR, | |
595 | AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, | |
70342287 | 596 | c0, d0, /*s0*/0, 0, 0); |
27dd65ac | 597 | |
851d4f5d | 598 | if (twosocks) { |
851d4f5d ML |
599 | irq_set_irq_type(c1, IRQ_TYPE_LEVEL_LOW); |
600 | irq_set_irq_type(s1, IRQ_TYPE_LEVEL_LOW); | |
601 | ||
602 | db1x_register_pcmcia_socket( | |
603 | AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, | |
604 | AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, | |
605 | AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, | |
606 | AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, | |
607 | AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, | |
608 | AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, | |
70342287 | 609 | c1, d1, /*s1*/0, 0, 1); |
851d4f5d | 610 | } |
b2ce305d | 611 | |
f59c811f | 612 | platform_add_devices(db1x00_devs, ARRAY_SIZE(db1x00_devs)); |
851d4f5d | 613 | db1x_register_norflash(flashsize << 20, 4 /* 32bit */, F_SWAPPED); |
27dd65ac ML |
614 | return 0; |
615 | } |