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1da177e4 | 1 | /* |
7916c354 SS |
2 | * Copyright 2000, 2008 MontaVista Software Inc. |
3 | * Author: MontaVista Software, Inc. <source@mvista.com> | |
1da177e4 LT |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2 of the License, or (at your | |
8 | * option) any later version. | |
9 | * | |
10 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
11 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
12 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
13 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
14 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
15 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
16 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
17 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
18 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
19 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License along | |
22 | * with this program; if not, write to the Free Software Foundation, Inc., | |
23 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | */ | |
ce28f94c | 25 | |
1da177e4 | 26 | #include <linux/delay.h> |
23ba25d5 ML |
27 | #include <linux/init.h> |
28 | #include <linux/interrupt.h> | |
1da177e4 LT |
29 | #include <asm/mach-au1x00/au1000.h> |
30 | #include <asm/mach-pb1x00/pb1000.h> | |
7179380e | 31 | #include <prom.h> |
1da177e4 | 32 | |
23ba25d5 ML |
33 | |
34 | struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { | |
35 | { AU1000_GPIO_15, INTC_INT_LOW_LEVEL, 0 }, | |
36 | }; | |
37 | ||
38 | int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); | |
39 | ||
40 | ||
41 | const char *get_system_type(void) | |
42 | { | |
43 | return "Alchemy Pb1000"; | |
44 | } | |
45 | ||
49a89efb | 46 | void board_reset(void) |
1da177e4 LT |
47 | { |
48 | } | |
49 | ||
50 | void __init board_setup(void) | |
51 | { | |
52 | u32 pin_func, static_cfg0; | |
53 | u32 sys_freqctrl, sys_clksrc; | |
54 | u32 prid = read_c0_prid(); | |
55 | ||
7179380e ML |
56 | #ifdef CONFIG_SERIAL_8250_CONSOLE |
57 | char *argptr = prom_getcmdline(); | |
58 | argptr = strstr(argptr, "console="); | |
59 | if (argptr == NULL) { | |
60 | argptr = prom_getcmdline(); | |
61 | strcat(argptr, " console=ttyS0,115200"); | |
62 | } | |
63 | #endif | |
64 | ||
7916c354 | 65 | /* Set AUX clock to 12 MHz * 8 = 96 MHz */ |
1da177e4 LT |
66 | au_writel(8, SYS_AUXPLL); |
67 | au_writel(0, SYS_PINSTATERD); | |
68 | udelay(100); | |
69 | ||
f708631a | 70 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) |
7916c354 | 71 | /* Zero and disable FREQ2 */ |
1da177e4 LT |
72 | sys_freqctrl = au_readl(SYS_FREQCTRL0); |
73 | sys_freqctrl &= ~0xFFF00000; | |
74 | au_writel(sys_freqctrl, SYS_FREQCTRL0); | |
75 | ||
7916c354 | 76 | /* Zero and disable USBH/USBD clocks */ |
1da177e4 | 77 | sys_clksrc = au_readl(SYS_CLKSRC); |
7916c354 SS |
78 | sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK | |
79 | SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK); | |
1da177e4 LT |
80 | au_writel(sys_clksrc, SYS_CLKSRC); |
81 | ||
82 | sys_freqctrl = au_readl(SYS_FREQCTRL0); | |
83 | sys_freqctrl &= ~0xFFF00000; | |
84 | ||
85 | sys_clksrc = au_readl(SYS_CLKSRC); | |
7916c354 SS |
86 | sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK | |
87 | SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK); | |
1da177e4 | 88 | |
7916c354 | 89 | switch (prid & 0x000000FF) { |
1da177e4 LT |
90 | case 0x00: /* DA */ |
91 | case 0x01: /* HA */ | |
92 | case 0x02: /* HB */ | |
7916c354 SS |
93 | /* CPU core freq to 48 MHz to slow it way down... */ |
94 | au_writel(4, SYS_CPUPLL); | |
1da177e4 | 95 | |
7916c354 SS |
96 | /* |
97 | * Setup 48 MHz FREQ2 from CPUPLL for USB Host | |
98 | * FRDIV2 = 3 -> div by 8 of 384 MHz -> 48 MHz | |
99 | */ | |
100 | sys_freqctrl |= (3 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2; | |
101 | au_writel(sys_freqctrl, SYS_FREQCTRL0); | |
1da177e4 | 102 | |
7916c354 SS |
103 | /* CPU core freq to 384 MHz */ |
104 | au_writel(0x20, SYS_CPUPLL); | |
1da177e4 | 105 | |
7916c354 | 106 | printk(KERN_INFO "Au1000: 48 MHz OHCI workaround enabled\n"); |
1da177e4 LT |
107 | break; |
108 | ||
7916c354 SS |
109 | default: /* HC and newer */ |
110 | /* FREQ2 = aux / 2 = 48 MHz */ | |
111 | sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) | | |
112 | SYS_FC_FE2 | SYS_FC_FS2; | |
113 | au_writel(sys_freqctrl, SYS_FREQCTRL0); | |
1da177e4 LT |
114 | break; |
115 | } | |
116 | ||
117 | /* | |
7916c354 | 118 | * Route 48 MHz FREQ2 into USB Host and/or Device |
1da177e4 | 119 | */ |
7916c354 | 120 | sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT; |
1da177e4 LT |
121 | au_writel(sys_clksrc, SYS_CLKSRC); |
122 | ||
7916c354 SS |
123 | /* Configure pins GPIO[14:9] as GPIO */ |
124 | pin_func = au_readl(SYS_PINFUNC) & ~(SYS_PF_UR3 | SYS_PF_USB); | |
1da177e4 | 125 | |
7916c354 SS |
126 | /* 2nd USB port is USB host */ |
127 | pin_func |= SYS_PF_USB; | |
5536b235 | 128 | |
1da177e4 LT |
129 | au_writel(pin_func, SYS_PINFUNC); |
130 | au_writel(0x2800, SYS_TRIOUTCLR); | |
131 | au_writel(0x0030, SYS_OUTPUTCLR); | |
f708631a | 132 | #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ |
1da177e4 | 133 | |
7916c354 SS |
134 | /* Make GPIO 15 an input (for interrupt line) */ |
135 | pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_IRF; | |
136 | /* We don't need I2S, so make it available for GPIO[31:29] */ | |
137 | pin_func |= SYS_PF_I2S; | |
1da177e4 LT |
138 | au_writel(pin_func, SYS_PINFUNC); |
139 | ||
140 | au_writel(0x8000, SYS_TRIOUTCLR); | |
141 | ||
7916c354 | 142 | static_cfg0 = au_readl(MEM_STCFG0) & ~0xc00; |
1da177e4 LT |
143 | au_writel(static_cfg0, MEM_STCFG0); |
144 | ||
7916c354 | 145 | /* configure RCE2* for LCD */ |
1da177e4 LT |
146 | au_writel(0x00000004, MEM_STCFG2); |
147 | ||
7916c354 | 148 | /* MEM_STTIME2 */ |
1da177e4 LT |
149 | au_writel(0x09000000, MEM_STTIME2); |
150 | ||
7916c354 | 151 | /* Set 32-bit base address decoding for RCE2* */ |
1da177e4 LT |
152 | au_writel(0x10003ff0, MEM_STADDR2); |
153 | ||
7916c354 SS |
154 | /* |
155 | * PCI CPLD setup | |
156 | * Expand CE0 to cover PCI | |
157 | */ | |
1da177e4 LT |
158 | au_writel(0x11803e40, MEM_STADDR1); |
159 | ||
7916c354 | 160 | /* Burst visibility on */ |
1da177e4 LT |
161 | au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0); |
162 | ||
7916c354 SS |
163 | au_writel(0x83, MEM_STCFG1); /* ewait enabled, flash timing */ |
164 | au_writel(0x33030a10, MEM_STTIME1); /* slower timing for FPGA */ | |
1da177e4 | 165 | |
7916c354 | 166 | /* Setup the static bus controller */ |
1da177e4 LT |
167 | au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */ |
168 | au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */ | |
169 | au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */ | |
170 | ||
7916c354 SS |
171 | /* |
172 | * Enable Au1000 BCLK switching - note: sed1356 must not use | |
173 | * its BCLK (Au1000 LCLK) for any timings | |
174 | */ | |
175 | switch (prid & 0x000000FF) { | |
1da177e4 LT |
176 | case 0x00: /* DA */ |
177 | case 0x01: /* HA */ | |
178 | case 0x02: /* HB */ | |
179 | break; | |
180 | default: /* HC and newer */ | |
7916c354 SS |
181 | /* |
182 | * Enable sys bus clock divider when IDLE state or no bus | |
183 | * activity. | |
184 | */ | |
1da177e4 LT |
185 | au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL); |
186 | break; | |
187 | } | |
188 | } |