[deliverable/linux.git] / arch / mips / alchemy / devboards / pb1100.c

/*
 * Pb1100 board platform device registration
 *
 * Copyright (C) 2009 Manuel Lauss
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */

#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-db1x00/bcsr.h>
#include <prom.h>
#include "platform.h"

const char *get_system_type(void)
{
	return "PB1100";
}

void __init board_setup(void)
{
	volatile void __iomem *base = (volatile void __iomem *)0xac000000UL;

	bcsr_init(DB1000_BCSR_PHYS_ADDR,
		  DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);

	/* Set AUX clock to 12 MHz * 8 = 96 MHz */
	au_writel(8, SYS_AUXPLL);
	alchemy_gpio1_input_enable();
	udelay(100);

#if IS_ENABLED(CONFIG_USB_OHCI_HCD)
	{
		u32 pin_func, sys_freqctrl, sys_clksrc;

		/* Configure pins GPIO[14:9] as GPIO */
		pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;

		/* Zero and disable FREQ2 */
		sys_freqctrl = au_readl(SYS_FREQCTRL0);
		sys_freqctrl &= ~0xFFF00000;
		au_writel(sys_freqctrl, SYS_FREQCTRL0);

		/* Zero and disable USBH/USBD/IrDA clock */
		sys_clksrc = au_readl(SYS_CLKSRC);
		sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK);
		au_writel(sys_clksrc, SYS_CLKSRC);

		sys_freqctrl = au_readl(SYS_FREQCTRL0);
		sys_freqctrl &= ~0xFFF00000;

		sys_clksrc = au_readl(SYS_CLKSRC);
		sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK);

		/* FREQ2 = aux / 2 = 48 MHz */
		sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
				SYS_FC_FE2 | SYS_FC_FS2;
		au_writel(sys_freqctrl, SYS_FREQCTRL0);

		/*
		 * Route 48 MHz FREQ2 into USBH/USBD/IrDA
		 */
		sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MIR_BIT;
		au_writel(sys_clksrc, SYS_CLKSRC);

		/* Setup the static bus controller */
		au_writel(0x00000002, MEM_STCFG3);  /* type = PCMCIA */
		au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
		au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */

		/*
		 * Get USB Functionality pin state (device vs host drive pins).
		 */
		pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB;
		/* 2nd USB port is USB host. */
		pin_func |= SYS_PF_USB;
		au_writel(pin_func, SYS_PINFUNC);
	}
#endif /* IS_ENABLED(CONFIG_USB_OHCI_HCD) */

	/* Enable sys bus clock divider when IDLE state or no bus activity. */
	au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);

	/* Enable the RTC if not already enabled. */
	if (!(readb(base + 0x28) & 0x20)) {
		writeb(readb(base + 0x28) | 0x20, base + 0x28);
		au_sync();
	}
	/* Put the clock in BCD mode. */
	if (readb(base + 0x2C) & 0x4) { /* reg B */
		writeb(readb(base + 0x2c) & ~0x4, base + 0x2c);
		au_sync();
	}
}

/******************************************************************************/

static struct resource au1100_lcd_resources[] = {
	[0] = {
		.start	= AU1100_LCD_PHYS_ADDR,
		.end	= AU1100_LCD_PHYS_ADDR + 0x800 - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= AU1100_LCD_INT,
		.end	= AU1100_LCD_INT,
		.flags	= IORESOURCE_IRQ,
	}
};

static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);

static struct platform_device au1100_lcd_device = {
	.name		= "au1100-lcd",
	.id		= 0,
	.dev = {
		.dma_mask		= &au1100_lcd_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.num_resources	= ARRAY_SIZE(au1100_lcd_resources),
	.resource	= au1100_lcd_resources,
};

static int __init pb1100_dev_init(void)
{
	int swapped;

	irq_set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */
	irq_set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */
	irq_set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */
	irq_set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */

	/* PCMCIA. single socket, identical to Pb1500 */
	db1x_register_pcmcia_socket(
		AU1000_PCMCIA_ATTR_PHYS_ADDR,
		AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
		AU1000_PCMCIA_MEM_PHYS_ADDR,
		AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
		AU1000_PCMCIA_IO_PHYS_ADDR,
		AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
		AU1100_GPIO11_INT, AU1100_GPIO9_INT,	 /* card / insert */
		/*AU1100_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */

	swapped = bcsr_read(BCSR_STATUS) &  BCSR_STATUS_DB1000_SWAPBOOT;
	db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
	platform_device_register(&au1100_lcd_device);

	return 0;
}
device_initcall(pb1100_dev_init);
Commit	Line	Data
1da177e4	1	/*
7c4b24da	2	* Pb1100 board platform device registration
1da177e4	3	*
7c4b24da	4	* Copyright (C) 2009 Manuel Lauss
1da177e4	5	*
7c4b24da ML	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
1da177e4	10	*
7c4b24da ML	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
1da177e4	19	*/
ce28f94c	20
7c4b24da	21	#include <linux/delay.h>
ce65cc8f	22	#include <linux/gpio.h>
1da177e4	23	#include <linux/init.h>
785e3268	24	#include <linux/interrupt.h>
7c4b24da ML	25	#include <linux/dma-mapping.h>
7c4b24da ML	26	#include <linux/platform_device.h>
1da177e4	27	#include <asm/mach-au1x00/au1000.h>
9bdcf336	28	#include <asm/mach-db1x00/bcsr.h>
7179380e	29	#include <prom.h>
7c4b24da	30	#include "platform.h"
23ba25d5	31
23ba25d5 ML	32	const char *get_system_type(void)
23ba25d5 ML	33	{
7c4b24da	34	return "PB1100";
23ba25d5 ML	35	}
23ba25d5 ML	36
1da177e4 LT	37	void __init board_setup(void)
1da177e4 LT	38	{
be1c3c1e	39	volatile void __iomem base = (volatile void __iomem )0xac000000UL;
7179380e	40
9bdcf336 ML	41	bcsr_init(DB1000_BCSR_PHYS_ADDR,
	42	DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
	43
be1c3c1e	44	/* Set AUX clock to 12 MHz * 8 = 96 MHz */
1da177e4	45	au_writel(8, SYS_AUXPLL);
ce65cc8f	46	alchemy_gpio1_input_enable();
1da177e4 LT	47	udelay(100);
1da177e4 LT	48
4bd5a574	49	#if IS_ENABLED(CONFIG_USB_OHCI_HCD)
3f21cdee RB	50	{
	51	u32 pin_func, sys_freqctrl, sys_clksrc;
	52
be1c3c1e SS	53	/* Configure pins GPIO[14:9] as GPIO */
be1c3c1e SS	54	pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
3f21cdee	55
be1c3c1e	56	/* Zero and disable FREQ2 */
3f21cdee RB	57	sys_freqctrl = au_readl(SYS_FREQCTRL0);
	58	sys_freqctrl &= ~0xFFF00000;
	59	au_writel(sys_freqctrl, SYS_FREQCTRL0);
	60
be1c3c1e	61	/* Zero and disable USBH/USBD/IrDA clock */
3f21cdee	62	sys_clksrc = au_readl(SYS_CLKSRC);
be1c3c1e	63	sys_clksrc &= ~(SYS_CS_CIR \| SYS_CS_DIR \| SYS_CS_MIR_MASK);
3f21cdee RB	64	au_writel(sys_clksrc, SYS_CLKSRC);
	65
	66	sys_freqctrl = au_readl(SYS_FREQCTRL0);
	67	sys_freqctrl &= ~0xFFF00000;
	68
	69	sys_clksrc = au_readl(SYS_CLKSRC);
be1c3c1e	70	sys_clksrc &= ~(SYS_CS_CIR \| SYS_CS_DIR \| SYS_CS_MIR_MASK);
3f21cdee	71
be1c3c1e SS	72	/* FREQ2 = aux / 2 = 48 MHz */
	73	sys_freqctrl \|= (0 << SYS_FC_FRDIV2_BIT) \|
	74	SYS_FC_FE2 \| SYS_FC_FS2;
3f21cdee RB	75	au_writel(sys_freqctrl, SYS_FREQCTRL0);
	76
	77	/*
be1c3c1e	78	* Route 48 MHz FREQ2 into USBH/USBD/IrDA
3f21cdee	79	*/
be1c3c1e	80	sys_clksrc \|= SYS_CS_MUX_FQ2 << SYS_CS_MIR_BIT;
3f21cdee RB	81	au_writel(sys_clksrc, SYS_CLKSRC);
3f21cdee RB	82
be1c3c1e	83	/* Setup the static bus controller */
3f21cdee RB	84	au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */
	85	au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
	86	au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
	87
be1c3c1e SS	88	/*
	89	* Get USB Functionality pin state (device vs host drive pins).
	90	*/
	91	pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB;
	92	/* 2nd USB port is USB host. */
	93	pin_func \|= SYS_PF_USB;
3f21cdee RB	94	au_writel(pin_func, SYS_PINFUNC);
3f21cdee RB	95	}
4bd5a574	96	#endif /* IS_ENABLED(CONFIG_USB_OHCI_HCD) */
1da177e4 LT	97
	98	/* Enable sys bus clock divider when IDLE state or no bus activity. */
	99	au_writel(au_readl(SYS_POWERCTRL) \| (0x3 << 5), SYS_POWERCTRL);
	100
be1c3c1e	101	/* Enable the RTC if not already enabled. */
3f21cdee RB	102	if (!(readb(base + 0x28) & 0x20)) {
3f21cdee RB	103	writeb(readb(base + 0x28) \| 0x20, base + 0x28);
1da177e4 LT	104	au_sync();
1da177e4 LT	105	}
be1c3c1e	106	/* Put the clock in BCD mode. */
3f21cdee RB	107	if (readb(base + 0x2C) & 0x4) { /* reg B */
3f21cdee RB	108	writeb(readb(base + 0x2c) & ~0x4, base + 0x2c);
1da177e4 LT	109	au_sync();
	110	}
	111	}
7e50b2b7	112
7c4b24da ML	113	/******************************************************************************/
	114
	115	static struct resource au1100_lcd_resources[] = {
	116	[0] = {
	117	.start = AU1100_LCD_PHYS_ADDR,
	118	.end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
	119	.flags = IORESOURCE_MEM,
	120	},
	121	[1] = {
	122	.start = AU1100_LCD_INT,
	123	.end = AU1100_LCD_INT,
	124	.flags = IORESOURCE_IRQ,
	125	}
	126	};
	127
	128	static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
	129
	130	static struct platform_device au1100_lcd_device = {
	131	.name = "au1100-lcd",
	132	.id = 0,
	133	.dev = {
	134	.dma_mask = &au1100_lcd_dmamask,
	135	.coherent_dma_mask = DMA_BIT_MASK(32),
	136	},
	137	.num_resources = ARRAY_SIZE(au1100_lcd_resources),
	138	.resource = au1100_lcd_resources,
	139	};
	140
	141	static int __init pb1100_dev_init(void)
7e50b2b7	142	{
7c4b24da ML	143	int swapped;
7c4b24da ML	144
e4ec7989 TG	145	irq_set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */
	146	irq_set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */
	147	irq_set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */
	148	irq_set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */
7e50b2b7	149
7c4b24da ML	150	/* PCMCIA. single socket, identical to Pb1500 */
	151	db1x_register_pcmcia_socket(
	152	AU1000_PCMCIA_ATTR_PHYS_ADDR,
	153	AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
	154	AU1000_PCMCIA_MEM_PHYS_ADDR,
	155	AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
	156	AU1000_PCMCIA_IO_PHYS_ADDR,
	157	AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
	158	AU1100_GPIO11_INT, AU1100_GPIO9_INT, /* card / insert */
	159	/AU1100_GPIO10_INT/0, 0, 0); /* stschg / eject / id */
	160
	161	swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
	162	db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
	163	platform_device_register(&au1100_lcd_device);
	164
7e50b2b7 ML	165	return 0;
7e50b2b7 ML	166	}
7c4b24da	167	device_initcall(pb1100_dev_init);