[deliverable/linux.git] / arch / mips / alchemy / devboards / pb1200 / board_setup.c

/*
 *
 * BRIEF MODULE DESCRIPTION
 *	Alchemy Pb1200/Db1200 board setup.
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/init.h>
#include <linux/sched.h>

#include <asm/mach-db1x00/bcsr.h>

#include <prom.h>
#include <au1xxx.h>


const char *get_system_type(void)
{
	return "Alchemy Pb1200";
}

void board_reset(void)
{
	bcsr_write(BCSR_RESETS, 0);
	bcsr_write(BCSR_SYSTEM, 0);
}

void __init board_setup(void)
{
	char *argptr;

#ifdef CONFIG_MIPS_PB1200
	printk(KERN_INFO "AMD Alchemy Pb1200 Board\n");
	bcsr_init(PB1200_BCSR_PHYS_ADDR,
		  PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
#endif
#ifdef CONFIG_MIPS_DB1200
	printk(KERN_INFO "AMD Alchemy Db1200 Board\n");
	bcsr_init(DB1200_BCSR_PHYS_ADDR,
		  DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
#endif

	argptr = prom_getcmdline();
#ifdef CONFIG_SERIAL_8250_CONSOLE
	argptr = strstr(argptr, "console=");
	if (argptr == NULL) {
		argptr = prom_getcmdline();
		strcat(argptr, " console=ttyS0,115200");
	}
#endif
#ifdef CONFIG_FB_AU1200
	strcat(argptr, " video=au1200fb:panel:bs");
#endif

#if 0
	{
		u32 pin_func;

		/*
		 * Enable PSC1 SYNC for AC97.  Normaly done in audio driver,
		 * but it is board specific code, so put it here.
		 */
		pin_func = au_readl(SYS_PINFUNC);
		au_sync();
		pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
		au_writel(pin_func, SYS_PINFUNC);

		au_writel(0, (u32)bcsr | 0x10); /* turn off PCMCIA power */
		au_sync();
	}
#endif

#if defined(CONFIG_I2C_AU1550)
	{
		u32 freq0, clksrc;
		u32 pin_func;

		/* Select SMBus in CPLD */
		bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);

		pin_func = au_readl(SYS_PINFUNC);
		au_sync();
		pin_func &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
		/* Set GPIOs correctly */
		pin_func |= 2 << 17;
		au_writel(pin_func, SYS_PINFUNC);
		au_sync();

		/* The I2C driver depends on 50 MHz clock */
		freq0 = au_readl(SYS_FREQCTRL0);
		au_sync();
		freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1);
		freq0 |= 3 << SYS_FC_FRDIV1_BIT;
		/* 396 MHz / (3 + 1) * 2 == 49.5 MHz */
		au_writel(freq0, SYS_FREQCTRL0);
		au_sync();
		freq0 |= SYS_FC_FE1;
		au_writel(freq0, SYS_FREQCTRL0);
		au_sync();

		clksrc = au_readl(SYS_CLKSRC);
		au_sync();
		clksrc &= ~(SYS_CS_CE0 | SYS_CS_DE0 | SYS_CS_ME0_MASK);
		/* Bit 22 is EXTCLK0 for PSC0 */
		clksrc |= SYS_CS_MUX_FQ1 << SYS_CS_ME0_BIT;
		au_writel(clksrc, SYS_CLKSRC);
		au_sync();
	}
#endif

	/*
	 * The Pb1200 development board uses external MUX for PSC0 to
	 * support SMB/SPI. bcsr_resets bit 12: 0=SMB 1=SPI
	 */
#ifdef CONFIG_I2C_AU1550
	bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
#endif
	au_sync();
}

int board_au1200fb_panel(void)
{
	return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
}

int board_au1200fb_panel_init(void)
{
	/* Apply power */
	bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
				BCSR_BOARD_LCDBL);
	/* printk(KERN_DEBUG "board_au1200fb_panel_init()\n"); */
	return 0;
}

int board_au1200fb_panel_shutdown(void)
{
	/* Remove power */
	bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
			     BCSR_BOARD_LCDBL, 0);
	/* printk(KERN_DEBUG "board_au1200fb_panel_shutdown()\n"); */
	return 0;
}
Commit	Line	Data
e3ad1c23 PP	1	/*
	2	*
	3	* BRIEF MODULE DESCRIPTION
	4	* Alchemy Pb1200/Db1200 board setup.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*
	11	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
	12	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	13	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	14	* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	15	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	16	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	17	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	18	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	19	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	20	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	21	*
	22	* You should have received a copy of the GNU General Public License along
	23	* with this program; if not, write to the Free Software Foundation, Inc.,
	24	* 675 Mass Ave, Cambridge, MA 02139, USA.
	25	*/
ce28f94c	26
e3ad1c23 PP	27	#include <linux/init.h>
e3ad1c23 PP	28	#include <linux/sched.h>
25b31cb1	29
9bdcf336 ML	30	#include <asm/mach-db1x00/bcsr.h>
9bdcf336 ML	31
25b31cb1	32	#include <prom.h>
c3d1d5c8	33	#include <au1xxx.h>
e3ad1c23	34
e3ad1c23	35
23ba25d5 ML	36	const char *get_system_type(void)
	37	{
	38	return "Alchemy Pb1200";
	39	}
	40
49a89efb	41	void board_reset(void)
e3ad1c23	42	{
9bdcf336 ML	43	bcsr_write(BCSR_RESETS, 0);
9bdcf336 ML	44	bcsr_write(BCSR_SYSTEM, 0);
e3ad1c23 PP	45	}
	46
	47	void __init board_setup(void)
	48	{
7179380e ML	49	char *argptr;
7179380e ML	50
9bdcf336 ML	51	#ifdef CONFIG_MIPS_PB1200
	52	printk(KERN_INFO "AMD Alchemy Pb1200 Board\n");
	53	bcsr_init(PB1200_BCSR_PHYS_ADDR,
	54	PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
	55	#endif
	56	#ifdef CONFIG_MIPS_DB1200
	57	printk(KERN_INFO "AMD Alchemy Db1200 Board\n");
	58	bcsr_init(DB1200_BCSR_PHYS_ADDR,
	59	DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
	60	#endif
	61
7179380e ML	62	argptr = prom_getcmdline();
	63	#ifdef CONFIG_SERIAL_8250_CONSOLE
	64	argptr = strstr(argptr, "console=");
	65	if (argptr == NULL) {
	66	argptr = prom_getcmdline();
	67	strcat(argptr, " console=ttyS0,115200");
	68	}
	69	#endif
	70	#ifdef CONFIG_FB_AU1200
	71	strcat(argptr, " video=au1200fb:panel:bs");
	72	#endif
e3ad1c23 PP	73
e3ad1c23 PP	74	#if 0
f5cd9f14	75	{
c3d1d5c8 SS	76	u32 pin_func;
	77
	78	/*
	79	* Enable PSC1 SYNC for AC97. Normaly done in audio driver,
	80	* but it is board specific code, so put it here.
	81	*/
	82	pin_func = au_readl(SYS_PINFUNC);
	83	au_sync();
	84	pin_func \|= SYS_PF_MUST_BE_SET \| SYS_PF_PSC1_S1;
	85	au_writel(pin_func, SYS_PINFUNC);
	86
	87	au_writel(0, (u32)bcsr \| 0x10); /* turn off PCMCIA power */
	88	au_sync();
f5cd9f14	89	}
e3ad1c23 PP	90	#endif
e3ad1c23 PP	91
64abf64d	92	#if defined(CONFIG_I2C_AU1550)
e3ad1c23	93	{
c3d1d5c8 SS	94	u32 freq0, clksrc;
	95	u32 pin_func;
	96
	97	/* Select SMBus in CPLD */
9bdcf336	98	bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
c3d1d5c8 SS	99
	100	pin_func = au_readl(SYS_PINFUNC);
	101	au_sync();
	102	pin_func &= ~(SYS_PINFUNC_P0A \| SYS_PINFUNC_P0B);
	103	/* Set GPIOs correctly */
	104	pin_func \|= 2 << 17;
	105	au_writel(pin_func, SYS_PINFUNC);
	106	au_sync();
	107
	108	/* The I2C driver depends on 50 MHz clock */
	109	freq0 = au_readl(SYS_FREQCTRL0);
	110	au_sync();
	111	freq0 &= ~(SYS_FC_FRDIV1_MASK \| SYS_FC_FS1 \| SYS_FC_FE1);
	112	freq0 \|= 3 << SYS_FC_FRDIV1_BIT;
	113	/* 396 MHz / (3 + 1) * 2 == 49.5 MHz */
	114	au_writel(freq0, SYS_FREQCTRL0);
	115	au_sync();
	116	freq0 \|= SYS_FC_FE1;
	117	au_writel(freq0, SYS_FREQCTRL0);
	118	au_sync();
	119
	120	clksrc = au_readl(SYS_CLKSRC);
	121	au_sync();
	122	clksrc &= ~(SYS_CS_CE0 \| SYS_CS_DE0 \| SYS_CS_ME0_MASK);
	123	/* Bit 22 is EXTCLK0 for PSC0 */
	124	clksrc \|= SYS_CS_MUX_FQ1 << SYS_CS_ME0_BIT;
	125	au_writel(clksrc, SYS_CLKSRC);
	126	au_sync();
e3ad1c23 PP	127	}
	128	#endif
	129
c3d1d5c8 SS	130	/*
c3d1d5c8 SS	131	* The Pb1200 development board uses external MUX for PSC0 to
9bdcf336	132	* support SMB/SPI. bcsr_resets bit 12: 0=SMB 1=SPI
c3d1d5c8	133	*/
6fec2e17	134	#ifdef CONFIG_I2C_AU1550
9bdcf336	135	bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
e3ad1c23 PP	136	#endif
e3ad1c23 PP	137	au_sync();
e3ad1c23	138	}
64abf64d	139
c3d1d5c8	140	int board_au1200fb_panel(void)
64abf64d	141	{
9bdcf336	142	return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
64abf64d PP	143	}
64abf64d PP	144
c3d1d5c8	145	int board_au1200fb_panel_init(void)
64abf64d PP	146	{
64abf64d PP	147	/* Apply power */
9bdcf336 ML	148	bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE \| BCSR_BOARD_LCDVDD \|
9bdcf336 ML	149	BCSR_BOARD_LCDBL);
c3d1d5c8	150	/* printk(KERN_DEBUG "board_au1200fb_panel_init()\n"); */
64abf64d PP	151	return 0;
	152	}
	153
c3d1d5c8	154	int board_au1200fb_panel_shutdown(void)
64abf64d PP	155	{
64abf64d PP	156	/* Remove power */
9bdcf336 ML	157	bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE \| BCSR_BOARD_LCDVDD \|
9bdcf336 ML	158	BCSR_BOARD_LCDBL, 0);
c3d1d5c8	159	/* printk(KERN_DEBUG "board_au1200fb_panel_shutdown()\n"); */
64abf64d PP	160	return 0;
64abf64d PP	161	}