MIPS: Alchemy: Redo PCI as platform driver
[deliverable/linux.git] / arch / mips / alchemy / gpr / platform.c
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1/*
2 * GPR board platform device registration
3 *
4 * Copyright (C) 2010 Wolfgang Grandegger <wg@denx.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/mtd/partitions.h>
24#include <linux/mtd/physmap.h>
25#include <linux/leds.h>
26#include <linux/gpio.h>
27#include <linux/i2c.h>
28#include <linux/i2c-gpio.h>
29
30#include <asm/mach-au1x00/au1000.h>
31
32/*
33 * Watchdog
34 */
35static struct resource gpr_wdt_resource[] = {
36 [0] = {
37 .start = 1,
38 .end = 1,
39 .name = "gpr-adm6320-wdt",
40 .flags = IORESOURCE_IRQ,
41 }
42};
43
44static struct platform_device gpr_wdt_device = {
45 .name = "adm6320-wdt",
46 .id = 0,
47 .num_resources = ARRAY_SIZE(gpr_wdt_resource),
48 .resource = gpr_wdt_resource,
49};
50
51/*
52 * FLASH
53 *
54 * 0x00000000-0x00200000 : "kernel"
55 * 0x00200000-0x00a00000 : "rootfs"
56 * 0x01d00000-0x01f00000 : "config"
57 * 0x01c00000-0x01d00000 : "yamon"
58 * 0x01d00000-0x01d40000 : "yamon env vars"
59 * 0x00000000-0x00a00000 : "kernel+rootfs"
60 */
61static struct mtd_partition gpr_mtd_partitions[] = {
62 {
63 .name = "kernel",
64 .size = 0x00200000,
65 .offset = 0,
66 },
67 {
68 .name = "rootfs",
69 .size = 0x00800000,
70 .offset = MTDPART_OFS_APPEND,
71 .mask_flags = MTD_WRITEABLE,
72 },
73 {
74 .name = "config",
75 .size = 0x00200000,
76 .offset = 0x01d00000,
77 },
78 {
79 .name = "yamon",
80 .size = 0x00100000,
81 .offset = 0x01c00000,
82 },
83 {
84 .name = "yamon env vars",
85 .size = 0x00040000,
86 .offset = MTDPART_OFS_APPEND,
87 },
88 {
89 .name = "kernel+rootfs",
90 .size = 0x00a00000,
91 .offset = 0,
92 },
93};
94
95static struct physmap_flash_data gpr_flash_data = {
96 .width = 4,
97 .nr_parts = ARRAY_SIZE(gpr_mtd_partitions),
98 .parts = gpr_mtd_partitions,
99};
100
101static struct resource gpr_mtd_resource = {
102 .start = 0x1e000000,
103 .end = 0x1fffffff,
104 .flags = IORESOURCE_MEM,
105};
106
107static struct platform_device gpr_mtd_device = {
108 .name = "physmap-flash",
109 .dev = {
110 .platform_data = &gpr_flash_data,
111 },
112 .num_resources = 1,
113 .resource = &gpr_mtd_resource,
114};
115
116/*
117 * LEDs
118 */
119static struct gpio_led gpr_gpio_leds[] = {
120 { /* green */
121 .name = "gpr:green",
122 .gpio = 4,
123 .active_low = 1,
124 },
125 { /* red */
126 .name = "gpr:red",
127 .gpio = 5,
128 .active_low = 1,
129 }
130};
131
132static struct gpio_led_platform_data gpr_led_data = {
133 .num_leds = ARRAY_SIZE(gpr_gpio_leds),
134 .leds = gpr_gpio_leds,
135};
136
137static struct platform_device gpr_led_devices = {
138 .name = "leds-gpio",
139 .id = -1,
140 .dev = {
141 .platform_data = &gpr_led_data,
142 }
143};
144
145/*
146 * I2C
147 */
148static struct i2c_gpio_platform_data gpr_i2c_data = {
149 .sda_pin = 209,
150 .sda_is_open_drain = 1,
151 .scl_pin = 210,
152 .scl_is_open_drain = 1,
153 .udelay = 2, /* ~100 kHz */
154 .timeout = HZ,
155 };
156
157static struct platform_device gpr_i2c_device = {
158 .name = "i2c-gpio",
159 .id = -1,
160 .dev.platform_data = &gpr_i2c_data,
161};
162
163static struct i2c_board_info gpr_i2c_info[] __initdata = {
164 {
165 I2C_BOARD_INFO("lm83", 0x18),
166 .type = "lm83"
167 }
168};
169
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170
171
172static struct resource alchemy_pci_host_res[] = {
173 [0] = {
174 .start = AU1500_PCI_PHYS_ADDR,
175 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
176 .flags = IORESOURCE_MEM,
177 },
178};
179
180static int gpr_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
181{
182 if ((slot == 0) && (pin == 1))
183 return AU1550_PCI_INTA;
184 else if ((slot == 0) && (pin == 2))
185 return AU1550_PCI_INTB;
186
187 return -1;
188}
189
190static struct alchemy_pci_platdata gpr_pci_pd = {
191 .board_map_irq = gpr_map_pci_irq,
192 .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
193 PCI_CONFIG_CH |
194#if defined(__MIPSEB__)
195 PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
196#else
197 0,
198#endif
199};
200
201static struct platform_device gpr_pci_host_dev = {
202 .dev.platform_data = &gpr_pci_pd,
203 .name = "alchemy-pci",
204 .id = 0,
205 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
206 .resource = alchemy_pci_host_res,
207};
208
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209static struct platform_device *gpr_devices[] __initdata = {
210 &gpr_wdt_device,
211 &gpr_mtd_device,
212 &gpr_i2c_device,
213 &gpr_led_devices,
214};
215
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216static int __init gpr_pci_init(void)
217{
218 return platform_device_register(&gpr_pci_host_dev);
219}
220/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
221arch_initcall(gpr_pci_init);
222
223
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224static int __init gpr_dev_init(void)
225{
226 i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info));
227
228 return platform_add_devices(gpr_devices, ARRAY_SIZE(gpr_devices));
229}
230device_initcall(gpr_dev_init);
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