[deliverable/linux.git] / arch / mips / ath25 / ar2315_regs.h

/*
 * Register definitions for AR2315+
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2003 Atheros Communications, Inc.,  All Rights Reserved.
 * Copyright (C) 2006 FON Technology, SL.
 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
 * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
 */

#ifndef __ASM_MACH_ATH25_AR2315_REGS_H
#define __ASM_MACH_ATH25_AR2315_REGS_H

/*
 * IRQs
 */
#define AR2315_IRQ_MISC		(MIPS_CPU_IRQ_BASE + 2)	/* C0_CAUSE: 0x0400 */
#define AR2315_IRQ_WLAN0	(MIPS_CPU_IRQ_BASE + 3)	/* C0_CAUSE: 0x0800 */
#define AR2315_IRQ_ENET0	(MIPS_CPU_IRQ_BASE + 4)	/* C0_CAUSE: 0x1000 */
#define AR2315_IRQ_LCBUS_PCI	(MIPS_CPU_IRQ_BASE + 5)	/* C0_CAUSE: 0x2000 */
#define AR2315_IRQ_WLAN0_POLL	(MIPS_CPU_IRQ_BASE + 6)	/* C0_CAUSE: 0x4000 */

/*
 * Miscellaneous interrupts, which share IP2.
 */
#define AR2315_MISC_IRQ_UART0		0
#define AR2315_MISC_IRQ_I2C_RSVD	1
#define AR2315_MISC_IRQ_SPI		2
#define AR2315_MISC_IRQ_AHB		3
#define AR2315_MISC_IRQ_APB		4
#define AR2315_MISC_IRQ_TIMER		5
#define AR2315_MISC_IRQ_GPIO		6
#define AR2315_MISC_IRQ_WATCHDOG	7
#define AR2315_MISC_IRQ_IR_RSVD		8
#define AR2315_MISC_IRQ_COUNT		9

/*
 * Address map
 */
#define AR2315_SPI_READ_BASE	0x08000000	/* SPI flash */
#define AR2315_SPI_READ_SIZE	0x01000000
#define AR2315_WLAN0_BASE	0x10000000	/* Wireless MMR */
#define AR2315_PCI_BASE		0x10100000	/* PCI MMR */
#define AR2315_PCI_SIZE		0x00001000
#define AR2315_SDRAMCTL_BASE	0x10300000	/* SDRAM MMR */
#define AR2315_SDRAMCTL_SIZE	0x00000020
#define AR2315_LOCAL_BASE	0x10400000	/* Local bus MMR */
#define AR2315_ENET0_BASE	0x10500000	/* Ethernet MMR */
#define AR2315_RST_BASE		0x11000000	/* Reset control MMR */
#define AR2315_RST_SIZE		0x00000100
#define AR2315_UART0_BASE	0x11100000	/* UART MMR */
#define AR2315_SPI_MMR_BASE	0x11300000	/* SPI flash MMR */
#define AR2315_SPI_MMR_SIZE	0x00000010
#define AR2315_PCI_EXT_BASE	0x80000000	/* PCI external */
#define AR2315_PCI_EXT_SIZE	0x40000000

/*
 * Configuration registers
 */

/* Cold reset register */
#define AR2315_COLD_RESET		0x0000

#define AR2315_RESET_COLD_AHB		0x00000001
#define AR2315_RESET_COLD_APB		0x00000002
#define AR2315_RESET_COLD_CPU		0x00000004
#define AR2315_RESET_COLD_CPUWARM	0x00000008
#define AR2315_RESET_SYSTEM		(RESET_COLD_CPU |\
					 RESET_COLD_APB |\
					 RESET_COLD_AHB)  /* full system */
#define AR2317_RESET_SYSTEM		0x00000010

/* Reset register */
#define AR2315_RESET			0x0004

#define AR2315_RESET_WARM_WLAN0_MAC	0x00000001  /* warm reset WLAN0 MAC */
#define AR2315_RESET_WARM_WLAN0_BB	0x00000002  /* warm reset WLAN0 BB */
#define AR2315_RESET_MPEGTS_RSVD	0x00000004  /* warm reset MPEG-TS */
#define AR2315_RESET_PCIDMA		0x00000008  /* warm reset PCI ahb/dma */
#define AR2315_RESET_MEMCTL		0x00000010  /* warm reset mem control */
#define AR2315_RESET_LOCAL		0x00000020  /* warm reset local bus */
#define AR2315_RESET_I2C_RSVD		0x00000040  /* warm reset I2C bus */
#define AR2315_RESET_SPI		0x00000080  /* warm reset SPI iface */
#define AR2315_RESET_UART0		0x00000100  /* warm reset UART0 */
#define AR2315_RESET_IR_RSVD		0x00000200  /* warm reset IR iface */
#define AR2315_RESET_EPHY0		0x00000400  /* cold reset ENET0 phy */
#define AR2315_RESET_ENET0		0x00000800  /* cold reset ENET0 MAC */

/* AHB master arbitration control */
#define AR2315_AHB_ARB_CTL		0x0008

#define AR2315_ARB_CPU			0x00000001  /* CPU, default */
#define AR2315_ARB_WLAN			0x00000002  /* WLAN */
#define AR2315_ARB_MPEGTS_RSVD		0x00000004  /* MPEG-TS */
#define AR2315_ARB_LOCAL		0x00000008  /* Local bus */
#define AR2315_ARB_PCI			0x00000010  /* PCI bus */
#define AR2315_ARB_ETHERNET		0x00000020  /* Ethernet */
#define AR2315_ARB_RETRY		0x00000100  /* Retry policy (debug) */

/* Config Register */
#define AR2315_ENDIAN_CTL		0x000c

#define AR2315_CONFIG_AHB		0x00000001  /* EC-AHB bridge endian */
#define AR2315_CONFIG_WLAN		0x00000002  /* WLAN byteswap */
#define AR2315_CONFIG_MPEGTS_RSVD	0x00000004  /* MPEG-TS byteswap */
#define AR2315_CONFIG_PCI		0x00000008  /* PCI byteswap */
#define AR2315_CONFIG_MEMCTL		0x00000010  /* Mem controller endian */
#define AR2315_CONFIG_LOCAL		0x00000020  /* Local bus byteswap */
#define AR2315_CONFIG_ETHERNET		0x00000040  /* Ethernet byteswap */
#define AR2315_CONFIG_MERGE		0x00000200  /* CPU write buffer merge */
#define AR2315_CONFIG_CPU		0x00000400  /* CPU big endian */
#define AR2315_CONFIG_BIG		0x00000400
#define AR2315_CONFIG_PCIAHB		0x00000800
#define AR2315_CONFIG_PCIAHB_BRIDGE	0x00001000
#define AR2315_CONFIG_SPI		0x00008000  /* SPI byteswap */
#define AR2315_CONFIG_CPU_DRAM		0x00010000
#define AR2315_CONFIG_CPU_PCI		0x00020000
#define AR2315_CONFIG_CPU_MMR		0x00040000

/* NMI control */
#define AR2315_NMI_CTL			0x0010

#define AR2315_NMI_EN			1

/* Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0). */
#define AR2315_SREV			0x0014

#define AR2315_REV_MAJ			0x000000f0
#define AR2315_REV_MAJ_S		4
#define AR2315_REV_MIN			0x0000000f
#define AR2315_REV_MIN_S		0
#define AR2315_REV_CHIP			(AR2315_REV_MAJ | AR2315_REV_MIN)

/* Interface Enable */
#define AR2315_IF_CTL			0x0018

#define AR2315_IF_MASK			0x00000007
#define AR2315_IF_DISABLED		0		/* Disable all */
#define AR2315_IF_PCI			1		/* PCI */
#define AR2315_IF_TS_LOCAL		2		/* Local bus */
#define AR2315_IF_ALL			3		/* Emulation only */
#define AR2315_IF_LOCAL_HOST		0x00000008
#define AR2315_IF_PCI_HOST		0x00000010
#define AR2315_IF_PCI_INTR		0x00000020
#define AR2315_IF_PCI_CLK_MASK		0x00030000
#define AR2315_IF_PCI_CLK_INPUT		0
#define AR2315_IF_PCI_CLK_OUTPUT_LOW	1
#define AR2315_IF_PCI_CLK_OUTPUT_CLK	2
#define AR2315_IF_PCI_CLK_OUTPUT_HIGH	3
#define AR2315_IF_PCI_CLK_SHIFT		16

/* APB Interrupt control */
#define AR2315_ISR			0x0020
#define AR2315_IMR			0x0024
#define AR2315_GISR			0x0028

#define AR2315_ISR_UART0	0x00000001	/* high speed UART */
#define AR2315_ISR_I2C_RSVD	0x00000002	/* I2C bus */
#define AR2315_ISR_SPI		0x00000004	/* SPI bus */
#define AR2315_ISR_AHB		0x00000008	/* AHB error */
#define AR2315_ISR_APB		0x00000010	/* APB error */
#define AR2315_ISR_TIMER	0x00000020	/* Timer */
#define AR2315_ISR_GPIO		0x00000040	/* GPIO */
#define AR2315_ISR_WD		0x00000080	/* Watchdog */
#define AR2315_ISR_IR_RSVD	0x00000100	/* IR */

#define AR2315_GISR_MISC	0x00000001	/* Misc */
#define AR2315_GISR_WLAN0	0x00000002	/* WLAN0 */
#define AR2315_GISR_MPEGTS_RSVD	0x00000004	/* MPEG-TS */
#define AR2315_GISR_LOCALPCI	0x00000008	/* Local/PCI bus */
#define AR2315_GISR_WMACPOLL	0x00000010
#define AR2315_GISR_TIMER	0x00000020
#define AR2315_GISR_ETHERNET	0x00000040	/* Ethernet */

/* Generic timer */
#define AR2315_TIMER			0x0030
#define AR2315_RELOAD			0x0034

/* Watchdog timer */
#define AR2315_WDT_TIMER		0x0038
#define AR2315_WDT_CTRL			0x003c

#define AR2315_WDT_CTRL_IGNORE	0x00000000	/* ignore expiration */
#define AR2315_WDT_CTRL_NMI	0x00000001	/* NMI on watchdog */
#define AR2315_WDT_CTRL_RESET	0x00000002	/* reset on watchdog */

/* CPU Performance Counters */
#define AR2315_PERFCNT0			0x0048
#define AR2315_PERFCNT1			0x004c

#define AR2315_PERF0_DATAHIT	0x00000001  /* Count Data Cache Hits */
#define AR2315_PERF0_DATAMISS	0x00000002  /* Count Data Cache Misses */
#define AR2315_PERF0_INSTHIT	0x00000004  /* Count Instruction Cache Hits */
#define AR2315_PERF0_INSTMISS	0x00000008  /* Count Instruction Cache Misses */
#define AR2315_PERF0_ACTIVE	0x00000010  /* Count Active Processor Cycles */
#define AR2315_PERF0_WBHIT	0x00000020  /* Count CPU Write Buffer Hits */
#define AR2315_PERF0_WBMISS	0x00000040  /* Count CPU Write Buffer Misses */

#define AR2315_PERF1_EB_ARDY	0x00000001  /* Count EB_ARdy signal */
#define AR2315_PERF1_EB_AVALID	0x00000002  /* Count EB_AValid signal */
#define AR2315_PERF1_EB_WDRDY	0x00000004  /* Count EB_WDRdy signal */
#define AR2315_PERF1_EB_RDVAL	0x00000008  /* Count EB_RdVal signal */
#define AR2315_PERF1_VRADDR	0x00000010  /* Count valid read address cycles*/
#define AR2315_PERF1_VWADDR	0x00000020  /* Count valid write address cycl.*/
#define AR2315_PERF1_VWDATA	0x00000040  /* Count valid write data cycles */

/* AHB Error Reporting */
#define AR2315_AHB_ERR0			0x0050  /* error  */
#define AR2315_AHB_ERR1			0x0054  /* haddr  */
#define AR2315_AHB_ERR2			0x0058  /* hwdata */
#define AR2315_AHB_ERR3			0x005c  /* hrdata */
#define AR2315_AHB_ERR4			0x0060  /* status */

#define AR2315_AHB_ERROR_DET	1 /* AHB Error has been detected,          */
				  /* write 1 to clear all bits in ERR0     */
#define AR2315_AHB_ERROR_OVR	2 /* AHB Error overflow has been detected  */
#define AR2315_AHB_ERROR_WDT	4 /* AHB Error due to wdt instead of hresp */

#define AR2315_PROCERR_HMAST		0x0000000f
#define AR2315_PROCERR_HMAST_DFLT	0
#define AR2315_PROCERR_HMAST_WMAC	1
#define AR2315_PROCERR_HMAST_ENET	2
#define AR2315_PROCERR_HMAST_PCIENDPT	3
#define AR2315_PROCERR_HMAST_LOCAL	4
#define AR2315_PROCERR_HMAST_CPU	5
#define AR2315_PROCERR_HMAST_PCITGT	6
#define AR2315_PROCERR_HMAST_S		0
#define AR2315_PROCERR_HWRITE		0x00000010
#define AR2315_PROCERR_HSIZE		0x00000060
#define AR2315_PROCERR_HSIZE_S		5
#define AR2315_PROCERR_HTRANS		0x00000180
#define AR2315_PROCERR_HTRANS_S		7
#define AR2315_PROCERR_HBURST		0x00000e00
#define AR2315_PROCERR_HBURST_S		9

/* Clock Control */
#define AR2315_PLLC_CTL			0x0064
#define AR2315_PLLV_CTL			0x0068
#define AR2315_CPUCLK			0x006c
#define AR2315_AMBACLK			0x0070
#define AR2315_SYNCCLK			0x0074
#define AR2315_DSL_SLEEP_CTL		0x0080
#define AR2315_DSL_SLEEP_DUR		0x0084

/* PLLc Control fields */
#define AR2315_PLLC_REF_DIV_M		0x00000003
#define AR2315_PLLC_REF_DIV_S		0
#define AR2315_PLLC_FDBACK_DIV_M	0x0000007c
#define AR2315_PLLC_FDBACK_DIV_S	2
#define AR2315_PLLC_ADD_FDBACK_DIV_M	0x00000080
#define AR2315_PLLC_ADD_FDBACK_DIV_S	7
#define AR2315_PLLC_CLKC_DIV_M		0x0001c000
#define AR2315_PLLC_CLKC_DIV_S		14
#define AR2315_PLLC_CLKM_DIV_M		0x00700000
#define AR2315_PLLC_CLKM_DIV_S		20

/* CPU CLK Control fields */
#define AR2315_CPUCLK_CLK_SEL_M		0x00000003
#define AR2315_CPUCLK_CLK_SEL_S		0
#define AR2315_CPUCLK_CLK_DIV_M		0x0000000c
#define AR2315_CPUCLK_CLK_DIV_S		2

/* AMBA CLK Control fields */
#define AR2315_AMBACLK_CLK_SEL_M	0x00000003
#define AR2315_AMBACLK_CLK_SEL_S	0
#define AR2315_AMBACLK_CLK_DIV_M	0x0000000c
#define AR2315_AMBACLK_CLK_DIV_S	2

/* PCI Clock Control */
#define AR2315_PCICLK			0x00a4

#define AR2315_PCICLK_INPUT_M		0x00000003
#define AR2315_PCICLK_INPUT_S		0
#define AR2315_PCICLK_PLLC_CLKM		0
#define AR2315_PCICLK_PLLC_CLKM1	1
#define AR2315_PCICLK_PLLC_CLKC		2
#define AR2315_PCICLK_REF_CLK		3
#define AR2315_PCICLK_DIV_M		0x0000000c
#define AR2315_PCICLK_DIV_S		2
#define AR2315_PCICLK_IN_FREQ		0
#define AR2315_PCICLK_IN_FREQ_DIV_6	1
#define AR2315_PCICLK_IN_FREQ_DIV_8	2
#define AR2315_PCICLK_IN_FREQ_DIV_10	3

/* Observation Control Register */
#define AR2315_OCR			0x00b0

#define AR2315_OCR_GPIO0_IRIN		0x00000040
#define AR2315_OCR_GPIO1_IROUT		0x00000080
#define AR2315_OCR_GPIO3_RXCLR		0x00000200

/* General Clock Control */
#define AR2315_MISCCLK			0x00b4

#define AR2315_MISCCLK_PLLBYPASS_EN	0x00000001
#define AR2315_MISCCLK_PROCREFCLK	0x00000002

/*
 * SDRAM Controller
 *   - No read or write buffers are included.
 */
#define AR2315_MEM_CFG			0x0000
#define AR2315_MEM_CTRL			0x000c
#define AR2315_MEM_REF			0x0010

#define AR2315_MEM_CFG_DATA_WIDTH_M	0x00006000
#define AR2315_MEM_CFG_DATA_WIDTH_S	13
#define AR2315_MEM_CFG_COL_WIDTH_M	0x00001e00
#define AR2315_MEM_CFG_COL_WIDTH_S	9
#define AR2315_MEM_CFG_ROW_WIDTH_M	0x000001e0
#define AR2315_MEM_CFG_ROW_WIDTH_S	5
#define AR2315_MEM_CFG_BANKADDR_BITS_M	0x00000018
#define AR2315_MEM_CFG_BANKADDR_BITS_S	3

/*
 * Local Bus Interface Registers
 */
#define AR2315_LB_CONFIG		0x0000

#define AR2315_LBCONF_OE	0x00000001	/* =1 OE is low-true */
#define AR2315_LBCONF_CS0	0x00000002	/* =1 first CS is low-true */
#define AR2315_LBCONF_CS1	0x00000004	/* =1 2nd CS is low-true */
#define AR2315_LBCONF_RDY	0x00000008	/* =1 RDY is low-true */
#define AR2315_LBCONF_WE	0x00000010	/* =1 Write En is low-true */
#define AR2315_LBCONF_WAIT	0x00000020	/* =1 WAIT is low-true */
#define AR2315_LBCONF_ADS	0x00000040	/* =1 Adr Strobe is low-true */
#define AR2315_LBCONF_MOT	0x00000080	/* =0 Intel, =1 Motorola */
#define AR2315_LBCONF_8CS	0x00000100	/* =1 8 bits CS, 0= 16bits */
#define AR2315_LBCONF_8DS	0x00000200	/* =1 8 bits Data S, 0=16bits */
#define AR2315_LBCONF_ADS_EN	0x00000400	/* =1 Enable ADS */
#define AR2315_LBCONF_ADR_OE	0x00000800	/* =1 Adr cap on OE, WE or DS */
#define AR2315_LBCONF_ADDT_MUX	0x00001000	/* =1 Adr and Data share bus */
#define AR2315_LBCONF_DATA_OE	0x00002000	/* =1 Data cap on OE, WE, DS */
#define AR2315_LBCONF_16DATA	0x00004000	/* =1 Data is 16 bits wide */
#define AR2315_LBCONF_SWAPDT	0x00008000	/* =1 Byte swap data */
#define AR2315_LBCONF_SYNC	0x00010000	/* =1 Bus synchronous to clk */
#define AR2315_LBCONF_INT	0x00020000	/* =1 Intr is low true */
#define AR2315_LBCONF_INT_CTR0	0x00000000	/* GND high-Z, Vdd is high-Z */
#define AR2315_LBCONF_INT_CTR1	0x00040000	/* GND drive, Vdd is high-Z */
#define AR2315_LBCONF_INT_CTR2	0x00080000	/* GND high-Z, Vdd drive */
#define AR2315_LBCONF_INT_CTR3	0x000c0000	/* GND drive, Vdd drive */
#define AR2315_LBCONF_RDY_WAIT	0x00100000	/* =1 RDY is negative of WAIT */
#define AR2315_LBCONF_INT_PULSE	0x00200000	/* =1 Interrupt is a pulse */
#define AR2315_LBCONF_ENABLE	0x00400000	/* =1 Falcon respond to LB */

#define AR2315_LB_CLKSEL		0x0004

#define AR2315_LBCLK_EXT	0x00000001	/* use external clk for lb */

#define AR2315_LB_1MS			0x0008

#define AR2315_LB1MS_MASK	0x0003ffff	/* # of AHB clk cycles in 1ms */

#define AR2315_LB_MISCCFG		0x000c

#define AR2315_LBM_TXD_EN	0x00000001	/* Enable TXD for fragments */
#define AR2315_LBM_RX_INTEN	0x00000002	/* Enable LB ints on RX ready */
#define AR2315_LBM_MBOXWR_INTEN	0x00000004	/* Enable LB ints on mbox wr */
#define AR2315_LBM_MBOXRD_INTEN	0x00000008	/* Enable LB ints on mbox rd */
#define AR2315_LMB_DESCSWAP_EN	0x00000010	/* Byte swap desc enable */
#define AR2315_LBM_TIMEOUT_M	0x00ffff80
#define AR2315_LBM_TIMEOUT_S	7
#define AR2315_LBM_PORTMUX	0x07000000

#define AR2315_LB_RXTSOFF		0x0010

#define AR2315_LB_TX_CHAIN_EN		0x0100

#define AR2315_LB_TXEN_0	0x00000001
#define AR2315_LB_TXEN_1	0x00000002
#define AR2315_LB_TXEN_2	0x00000004
#define AR2315_LB_TXEN_3	0x00000008

#define AR2315_LB_TX_CHAIN_DIS		0x0104
#define AR2315_LB_TX_DESC_PTR		0x0200

#define AR2315_LB_RX_CHAIN_EN		0x0400

#define AR2315_LB_RXEN		0x00000001

#define AR2315_LB_RX_CHAIN_DIS		0x0404
#define AR2315_LB_RX_DESC_PTR		0x0408

#define AR2315_LB_INT_STATUS		0x0500

#define AR2315_LB_INT_TX_DESC		0x00000001
#define AR2315_LB_INT_TX_OK		0x00000002
#define AR2315_LB_INT_TX_ERR		0x00000004
#define AR2315_LB_INT_TX_EOF		0x00000008
#define AR2315_LB_INT_RX_DESC		0x00000010
#define AR2315_LB_INT_RX_OK		0x00000020
#define AR2315_LB_INT_RX_ERR		0x00000040
#define AR2315_LB_INT_RX_EOF		0x00000080
#define AR2315_LB_INT_TX_TRUNC		0x00000100
#define AR2315_LB_INT_TX_STARVE		0x00000200
#define AR2315_LB_INT_LB_TIMEOUT	0x00000400
#define AR2315_LB_INT_LB_ERR		0x00000800
#define AR2315_LB_INT_MBOX_WR		0x00001000
#define AR2315_LB_INT_MBOX_RD		0x00002000

/* Bit definitions for INT MASK are the same as INT_STATUS */
#define AR2315_LB_INT_MASK		0x0504

#define AR2315_LB_INT_EN		0x0508
#define AR2315_LB_MBOX			0x0600

#endif /* __ASM_MACH_ATH25_AR2315_REGS_H */
Commit	Line	Data
ba910345 SR	1	/*
	2	* Register definitions for AR2315+
	3	*
	4	* This file is subject to the terms and conditions of the GNU General Public
	5	* License. See the file "COPYING" in the main directory of this archive
	6	* for more details.
	7	*
	8	* Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
	9	* Copyright (C) 2006 FON Technology, SL.
	10	* Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
	11	* Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
	12	*/
	13
	14	#ifndef __ASM_MACH_ATH25_AR2315_REGS_H
	15	#define __ASM_MACH_ATH25_AR2315_REGS_H
	16
1753e74e SR	17	/*
	18	* IRQs
	19	*/
	20	#define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
	21	#define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
	22	#define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
	23	#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
	24	#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
	25
	26	/*
	27	* Miscellaneous interrupts, which share IP2.
	28	*/
	29	#define AR2315_MISC_IRQ_UART0 0
	30	#define AR2315_MISC_IRQ_I2C_RSVD 1
	31	#define AR2315_MISC_IRQ_SPI 2
	32	#define AR2315_MISC_IRQ_AHB 3
	33	#define AR2315_MISC_IRQ_APB 4
	34	#define AR2315_MISC_IRQ_TIMER 5
	35	#define AR2315_MISC_IRQ_GPIO 6
	36	#define AR2315_MISC_IRQ_WATCHDOG 7
	37	#define AR2315_MISC_IRQ_IR_RSVD 8
	38	#define AR2315_MISC_IRQ_COUNT 9
	39
ba910345 SR	40	/*
	41	* Address map
	42	*/
	43	#define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */
	44	#define AR2315_SPI_READ_SIZE 0x01000000
	45	#define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */
	46	#define AR2315_PCI_BASE 0x10100000 /* PCI MMR */
	47	#define AR2315_PCI_SIZE 0x00001000
	48	#define AR2315_SDRAMCTL_BASE 0x10300000 /* SDRAM MMR */
	49	#define AR2315_SDRAMCTL_SIZE 0x00000020
	50	#define AR2315_LOCAL_BASE 0x10400000 /* Local bus MMR */
	51	#define AR2315_ENET0_BASE 0x10500000 /* Ethernet MMR */
	52	#define AR2315_RST_BASE 0x11000000 /* Reset control MMR */
	53	#define AR2315_RST_SIZE 0x00000100
	54	#define AR2315_UART0_BASE 0x11100000 /* UART MMR */
	55	#define AR2315_SPI_MMR_BASE 0x11300000 /* SPI flash MMR */
	56	#define AR2315_SPI_MMR_SIZE 0x00000010
	57	#define AR2315_PCI_EXT_BASE 0x80000000 /* PCI external */
	58	#define AR2315_PCI_EXT_SIZE 0x40000000
	59
	60	/*
	61	* Configuration registers
	62	*/
	63
	64	/* Cold reset register */
	65	#define AR2315_COLD_RESET 0x0000
	66
	67	#define AR2315_RESET_COLD_AHB 0x00000001
	68	#define AR2315_RESET_COLD_APB 0x00000002
	69	#define AR2315_RESET_COLD_CPU 0x00000004
	70	#define AR2315_RESET_COLD_CPUWARM 0x00000008
	71	#define AR2315_RESET_SYSTEM (RESET_COLD_CPU \|\
	72	RESET_COLD_APB \|\
	73	RESET_COLD_AHB) /* full system */
	74	#define AR2317_RESET_SYSTEM 0x00000010
	75
	76	/* Reset register */
	77	#define AR2315_RESET 0x0004
	78
	79	#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */
	80	#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BB */
	81	#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */
	82	#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */
	83	#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset mem control */
	84	#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */
	85	#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */
	86	#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI iface */
	87	#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */
	88	#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR iface */
	89	#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */
	90	#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 MAC */
	91
	92	/* AHB master arbitration control */
	93	#define AR2315_AHB_ARB_CTL 0x0008
	94
	95	#define AR2315_ARB_CPU 0x00000001 /* CPU, default */
	96	#define AR2315_ARB_WLAN 0x00000002 /* WLAN */
	97	#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
	98	#define AR2315_ARB_LOCAL 0x00000008 /* Local bus */
	99	#define AR2315_ARB_PCI 0x00000010 /* PCI bus */
	100	#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */
	101	#define AR2315_ARB_RETRY 0x00000100 /* Retry policy (debug) */
	102
	103	/* Config Register */
104	#define AR2315_ENDIAN_CTL 0x000c
105
106	#define AR2315_CONFIG_AHB 0x00000001 /* EC-AHB bridge endian */
107	#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */
108	#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */
109	#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */
110	#define AR2315_CONFIG_MEMCTL 0x00000010 /* Mem controller endian */
111	#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */
112	#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */
113	#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */
114	#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */
115	#define AR2315_CONFIG_BIG 0x00000400
116	#define AR2315_CONFIG_PCIAHB 0x00000800
117	#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
118	#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */
119	#define AR2315_CONFIG_CPU_DRAM 0x00010000
120	#define AR2315_CONFIG_CPU_PCI 0x00020000
121	#define AR2315_CONFIG_CPU_MMR 0x00040000
122
123	/* NMI control */
124	#define AR2315_NMI_CTL 0x0010
125
126	#define AR2315_NMI_EN 1
127
128	/* Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0). */
129	#define AR2315_SREV 0x0014
130
131	#define AR2315_REV_MAJ 0x000000f0
132	#define AR2315_REV_MAJ_S 4
133	#define AR2315_REV_MIN 0x0000000f
134	#define AR2315_REV_MIN_S 0
135	#define AR2315_REV_CHIP (AR2315_REV_MAJ \| AR2315_REV_MIN)
136
137	/* Interface Enable */
138	#define AR2315_IF_CTL 0x0018
139
140	#define AR2315_IF_MASK 0x00000007
141	#define AR2315_IF_DISABLED 0 /* Disable all */
142	#define AR2315_IF_PCI 1 /* PCI */
143	#define AR2315_IF_TS_LOCAL 2 /* Local bus */
144	#define AR2315_IF_ALL 3 /* Emulation only */
145	#define AR2315_IF_LOCAL_HOST 0x00000008
146	#define AR2315_IF_PCI_HOST 0x00000010
147	#define AR2315_IF_PCI_INTR 0x00000020
148	#define AR2315_IF_PCI_CLK_MASK 0x00030000
149	#define AR2315_IF_PCI_CLK_INPUT 0
150	#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
151	#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
152	#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
153	#define AR2315_IF_PCI_CLK_SHIFT 16
154
155	/* APB Interrupt control */
156	#define AR2315_ISR 0x0020
157	#define AR2315_IMR 0x0024
158	#define AR2315_GISR 0x0028
159
160	#define AR2315_ISR_UART0 0x00000001 /* high speed UART */
161	#define AR2315_ISR_I2C_RSVD 0x00000002 /* I2C bus */
162	#define AR2315_ISR_SPI 0x00000004 /* SPI bus */
163	#define AR2315_ISR_AHB 0x00000008 /* AHB error */
164	#define AR2315_ISR_APB 0x00000010 /* APB error */
165	#define AR2315_ISR_TIMER 0x00000020 /* Timer */
166	#define AR2315_ISR_GPIO 0x00000040 /* GPIO */
167	#define AR2315_ISR_WD 0x00000080 /* Watchdog */
168	#define AR2315_ISR_IR_RSVD 0x00000100 /* IR */
169
170	#define AR2315_GISR_MISC 0x00000001 /* Misc */
171	#define AR2315_GISR_WLAN0 0x00000002 /* WLAN0 */
172	#define AR2315_GISR_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
173	#define AR2315_GISR_LOCALPCI 0x00000008 /* Local/PCI bus */
174	#define AR2315_GISR_WMACPOLL 0x00000010
175	#define AR2315_GISR_TIMER 0x00000020
176	#define AR2315_GISR_ETHERNET 0x00000040 /* Ethernet */
177
178	/* Generic timer */
179	#define AR2315_TIMER 0x0030
180	#define AR2315_RELOAD 0x0034
181
182	/* Watchdog timer */
183	#define AR2315_WDT_TIMER 0x0038
184	#define AR2315_WDT_CTRL 0x003c
185
186	#define AR2315_WDT_CTRL_IGNORE 0x00000000 /* ignore expiration */
187	#define AR2315_WDT_CTRL_NMI 0x00000001 /* NMI on watchdog */
188	#define AR2315_WDT_CTRL_RESET 0x00000002 /* reset on watchdog */
189
190	/* CPU Performance Counters */
191	#define AR2315_PERFCNT0 0x0048
192	#define AR2315_PERFCNT1 0x004c
193
194	#define AR2315_PERF0_DATAHIT 0x00000001 /* Count Data Cache Hits */
195	#define AR2315_PERF0_DATAMISS 0x00000002 /* Count Data Cache Misses */
196	#define AR2315_PERF0_INSTHIT 0x00000004 /* Count Instruction Cache Hits */
197	#define AR2315_PERF0_INSTMISS 0x00000008 /* Count Instruction Cache Misses */
198	#define AR2315_PERF0_ACTIVE 0x00000010 /* Count Active Processor Cycles */
199	#define AR2315_PERF0_WBHIT 0x00000020 /* Count CPU Write Buffer Hits */
200	#define AR2315_PERF0_WBMISS 0x00000040 /* Count CPU Write Buffer Misses */
201
202	#define AR2315_PERF1_EB_ARDY 0x00000001 /* Count EB_ARdy signal */
203	#define AR2315_PERF1_EB_AVALID 0x00000002 /* Count EB_AValid signal */
204	#define AR2315_PERF1_EB_WDRDY 0x00000004 /* Count EB_WDRdy signal */
205	#define AR2315_PERF1_EB_RDVAL 0x00000008 /* Count EB_RdVal signal */
206	#define AR2315_PERF1_VRADDR 0x00000010 /* Count valid read address cycles*/
207	#define AR2315_PERF1_VWADDR 0x00000020 /* Count valid write address cycl.*/
208	#define AR2315_PERF1_VWDATA 0x00000040 /* Count valid write data cycles */
209
210	/* AHB Error Reporting */
211	#define AR2315_AHB_ERR0 0x0050 /* error */
212	#define AR2315_AHB_ERR1 0x0054 /* haddr */
213	#define AR2315_AHB_ERR2 0x0058 /* hwdata */
214	#define AR2315_AHB_ERR3 0x005c /* hrdata */
215	#define AR2315_AHB_ERR4 0x0060 /* status */
216
217	#define AR2315_AHB_ERROR_DET 1 /* AHB Error has been detected, */
218	/* write 1 to clear all bits in ERR0 */
219	#define AR2315_AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
220	#define AR2315_AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
221
222	#define AR2315_PROCERR_HMAST 0x0000000f
223	#define AR2315_PROCERR_HMAST_DFLT 0
224	#define AR2315_PROCERR_HMAST_WMAC 1
225	#define AR2315_PROCERR_HMAST_ENET 2
226	#define AR2315_PROCERR_HMAST_PCIENDPT 3
227	#define AR2315_PROCERR_HMAST_LOCAL 4
228	#define AR2315_PROCERR_HMAST_CPU 5
229	#define AR2315_PROCERR_HMAST_PCITGT 6
230	#define AR2315_PROCERR_HMAST_S 0
231	#define AR2315_PROCERR_HWRITE 0x00000010
232	#define AR2315_PROCERR_HSIZE 0x00000060
233	#define AR2315_PROCERR_HSIZE_S 5
234	#define AR2315_PROCERR_HTRANS 0x00000180
235	#define AR2315_PROCERR_HTRANS_S 7
236	#define AR2315_PROCERR_HBURST 0x00000e00
237	#define AR2315_PROCERR_HBURST_S 9
238
239	/* Clock Control */
240	#define AR2315_PLLC_CTL 0x0064
241	#define AR2315_PLLV_CTL 0x0068
242	#define AR2315_CPUCLK 0x006c
243	#define AR2315_AMBACLK 0x0070
244	#define AR2315_SYNCCLK 0x0074
245	#define AR2315_DSL_SLEEP_CTL 0x0080
246	#define AR2315_DSL_SLEEP_DUR 0x0084
247
248	/* PLLc Control fields */
249	#define AR2315_PLLC_REF_DIV_M 0x00000003
250	#define AR2315_PLLC_REF_DIV_S 0
251	#define AR2315_PLLC_FDBACK_DIV_M 0x0000007c
252	#define AR2315_PLLC_FDBACK_DIV_S 2
253	#define AR2315_PLLC_ADD_FDBACK_DIV_M 0x00000080
254	#define AR2315_PLLC_ADD_FDBACK_DIV_S 7
255	#define AR2315_PLLC_CLKC_DIV_M 0x0001c000
256	#define AR2315_PLLC_CLKC_DIV_S 14
257	#define AR2315_PLLC_CLKM_DIV_M 0x00700000
258	#define AR2315_PLLC_CLKM_DIV_S 20
259
260	/* CPU CLK Control fields */
261	#define AR2315_CPUCLK_CLK_SEL_M 0x00000003
262	#define AR2315_CPUCLK_CLK_SEL_S 0
263	#define AR2315_CPUCLK_CLK_DIV_M 0x0000000c
264	#define AR2315_CPUCLK_CLK_DIV_S 2
265
266	/* AMBA CLK Control fields */
267	#define AR2315_AMBACLK_CLK_SEL_M 0x00000003
268	#define AR2315_AMBACLK_CLK_SEL_S 0
269	#define AR2315_AMBACLK_CLK_DIV_M 0x0000000c
270	#define AR2315_AMBACLK_CLK_DIV_S 2
271
272	/* PCI Clock Control */
273	#define AR2315_PCICLK 0x00a4
274
275	#define AR2315_PCICLK_INPUT_M 0x00000003
276	#define AR2315_PCICLK_INPUT_S 0
277	#define AR2315_PCICLK_PLLC_CLKM 0
278	#define AR2315_PCICLK_PLLC_CLKM1 1
279	#define AR2315_PCICLK_PLLC_CLKC 2
280	#define AR2315_PCICLK_REF_CLK 3
281	#define AR2315_PCICLK_DIV_M 0x0000000c
282	#define AR2315_PCICLK_DIV_S 2
283	#define AR2315_PCICLK_IN_FREQ 0
284	#define AR2315_PCICLK_IN_FREQ_DIV_6 1
285	#define AR2315_PCICLK_IN_FREQ_DIV_8 2
286	#define AR2315_PCICLK_IN_FREQ_DIV_10 3
287
288	/* Observation Control Register */
289	#define AR2315_OCR 0x00b0
290
291	#define AR2315_OCR_GPIO0_IRIN 0x00000040
292	#define AR2315_OCR_GPIO1_IROUT 0x00000080
293	#define AR2315_OCR_GPIO3_RXCLR 0x00000200
294
295	/* General Clock Control */
296	#define AR2315_MISCCLK 0x00b4
297
298	#define AR2315_MISCCLK_PLLBYPASS_EN 0x00000001
299	#define AR2315_MISCCLK_PROCREFCLK 0x00000002
300
301	/*
302	* SDRAM Controller
303	* - No read or write buffers are included.
304	*/
305	#define AR2315_MEM_CFG 0x0000
306	#define AR2315_MEM_CTRL 0x000c
307	#define AR2315_MEM_REF 0x0010
308
309	#define AR2315_MEM_CFG_DATA_WIDTH_M 0x00006000
310	#define AR2315_MEM_CFG_DATA_WIDTH_S 13
311	#define AR2315_MEM_CFG_COL_WIDTH_M 0x00001e00
312	#define AR2315_MEM_CFG_COL_WIDTH_S 9
313	#define AR2315_MEM_CFG_ROW_WIDTH_M 0x000001e0
314	#define AR2315_MEM_CFG_ROW_WIDTH_S 5
315	#define AR2315_MEM_CFG_BANKADDR_BITS_M 0x00000018
316	#define AR2315_MEM_CFG_BANKADDR_BITS_S 3
317
318	/*
319	* Local Bus Interface Registers
320	*/
321	#define AR2315_LB_CONFIG 0x0000
322
323	#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
324	#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
325	#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
326	#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
327	#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
328	#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
329	#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
330	#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
331	#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
332	#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
333	#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
334	#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
335	#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
336	#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
337	#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
338	#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
339	#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
340	#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
341	#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
342	#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
343	#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
344	#define AR2315_LBCONF_INT_CTR3 0x000c0000 /* GND drive, Vdd drive */
345	#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
346	#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
347	#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
348
349	#define AR2315_LB_CLKSEL 0x0004
350
351	#define AR2315_LBCLK_EXT 0x00000001 /* use external clk for lb */
352
353	#define AR2315_LB_1MS 0x0008
354
355	#define AR2315_LB1MS_MASK 0x0003ffff /* # of AHB clk cycles in 1ms */
356
357	#define AR2315_LB_MISCCFG 0x000c
358
359	#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
360	#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
361	#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
362	#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
363	#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
364	#define AR2315_LBM_TIMEOUT_M 0x00ffff80
365	#define AR2315_LBM_TIMEOUT_S 7
366	#define AR2315_LBM_PORTMUX 0x07000000
367
368	#define AR2315_LB_RXTSOFF 0x0010
369
370	#define AR2315_LB_TX_CHAIN_EN 0x0100
371
372	#define AR2315_LB_TXEN_0 0x00000001
373	#define AR2315_LB_TXEN_1 0x00000002
374	#define AR2315_LB_TXEN_2 0x00000004
375	#define AR2315_LB_TXEN_3 0x00000008
376
377	#define AR2315_LB_TX_CHAIN_DIS 0x0104
378	#define AR2315_LB_TX_DESC_PTR 0x0200
379
380	#define AR2315_LB_RX_CHAIN_EN 0x0400
381
382	#define AR2315_LB_RXEN 0x00000001
383
384	#define AR2315_LB_RX_CHAIN_DIS 0x0404
385	#define AR2315_LB_RX_DESC_PTR 0x0408
386
387	#define AR2315_LB_INT_STATUS 0x0500
388
389	#define AR2315_LB_INT_TX_DESC 0x00000001
390	#define AR2315_LB_INT_TX_OK 0x00000002
391	#define AR2315_LB_INT_TX_ERR 0x00000004
392	#define AR2315_LB_INT_TX_EOF 0x00000008
393	#define AR2315_LB_INT_RX_DESC 0x00000010
394	#define AR2315_LB_INT_RX_OK 0x00000020
395	#define AR2315_LB_INT_RX_ERR 0x00000040
396	#define AR2315_LB_INT_RX_EOF 0x00000080
397	#define AR2315_LB_INT_TX_TRUNC 0x00000100
398	#define AR2315_LB_INT_TX_STARVE 0x00000200
399	#define AR2315_LB_INT_LB_TIMEOUT 0x00000400
400	#define AR2315_LB_INT_LB_ERR 0x00000800
401	#define AR2315_LB_INT_MBOX_WR 0x00001000
402	#define AR2315_LB_INT_MBOX_RD 0x00002000
403
404	/* Bit definitions for INT MASK are the same as INT_STATUS */
405	#define AR2315_LB_INT_MASK 0x0504
406
407	#define AR2315_LB_INT_EN 0x0508
408	#define AR2315_LB_MBOX 0x0600
409
410	#endif /* __ASM_MACH_ATH25_AR2315_REGS_H */