[deliverable/linux.git] / arch / mips / ath25 / ar5312.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2003 Atheros Communications, Inc.,  All Rights Reserved.
 * Copyright (C) 2006 FON Technology, SL.
 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
 * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
 * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
 */

/*
 * Platform devices for Atheros AR5312 SoCs
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/irqdomain.h>
#include <linux/interrupt.h>
#include <linux/reboot.h>
#include <asm/bootinfo.h>
#include <asm/reboot.h>
#include <asm/time.h>

#include <ath25_platform.h>

#include "devices.h"
#include "ar5312.h"
#include "ar5312_regs.h"

static void __iomem *ar5312_rst_base;
static struct irq_domain *ar5312_misc_irq_domain;

static inline u32 ar5312_rst_reg_read(u32 reg)
{
	return __raw_readl(ar5312_rst_base + reg);
}

static inline void ar5312_rst_reg_write(u32 reg, u32 val)
{
	__raw_writel(val, ar5312_rst_base + reg);
}

static inline void ar5312_rst_reg_mask(u32 reg, u32 mask, u32 val)
{
	u32 ret = ar5312_rst_reg_read(reg);

	ret &= ~mask;
	ret |= val;
	ar5312_rst_reg_write(reg, ret);
}

static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id)
{
	u32 proc1 = ar5312_rst_reg_read(AR5312_PROC1);
	u32 proc_addr = ar5312_rst_reg_read(AR5312_PROCADDR); /* clears error */
	u32 dma1 = ar5312_rst_reg_read(AR5312_DMA1);
	u32 dma_addr = ar5312_rst_reg_read(AR5312_DMAADDR);   /* clears error */

	pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
		 proc_addr, proc1, dma_addr, dma1);

	machine_restart("AHB error"); /* Catastrophic failure */
	return IRQ_HANDLED;
}

static struct irqaction ar5312_ahb_err_interrupt  = {
	.handler = ar5312_ahb_err_handler,
	.name    = "ar5312-ahb-error",
};

static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
{
	u32 pending = ar5312_rst_reg_read(AR5312_ISR) &
		      ar5312_rst_reg_read(AR5312_IMR);
	unsigned nr, misc_irq = 0;

	if (pending) {
		struct irq_domain *domain = irq_get_handler_data(irq);

		nr = __ffs(pending);
		misc_irq = irq_find_mapping(domain, nr);
	}

	if (misc_irq) {
		generic_handle_irq(misc_irq);
		if (nr == AR5312_MISC_IRQ_TIMER)
			ar5312_rst_reg_read(AR5312_TIMER);
	} else {
		spurious_interrupt();
	}
}

/* Enable the specified AR5312_MISC_IRQ interrupt */
static void ar5312_misc_irq_unmask(struct irq_data *d)
{
	ar5312_rst_reg_mask(AR5312_IMR, 0, BIT(d->hwirq));
}

/* Disable the specified AR5312_MISC_IRQ interrupt */
static void ar5312_misc_irq_mask(struct irq_data *d)
{
	ar5312_rst_reg_mask(AR5312_IMR, BIT(d->hwirq), 0);
	ar5312_rst_reg_read(AR5312_IMR); /* flush write buffer */
}

static struct irq_chip ar5312_misc_irq_chip = {
	.name		= "ar5312-misc",
	.irq_unmask	= ar5312_misc_irq_unmask,
	.irq_mask	= ar5312_misc_irq_mask,
};

static int ar5312_misc_irq_map(struct irq_domain *d, unsigned irq,
			       irq_hw_number_t hw)
{
	irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip, handle_level_irq);
	return 0;
}

static struct irq_domain_ops ar5312_misc_irq_domain_ops = {
	.map = ar5312_misc_irq_map,
};

static void ar5312_irq_dispatch(void)
{
	u32 pending = read_c0_status() & read_c0_cause();

	if (pending & CAUSEF_IP2)
		do_IRQ(AR5312_IRQ_WLAN0);
	else if (pending & CAUSEF_IP5)
		do_IRQ(AR5312_IRQ_WLAN1);
	else if (pending & CAUSEF_IP6)
		do_IRQ(AR5312_IRQ_MISC);
	else if (pending & CAUSEF_IP7)
		do_IRQ(ATH25_IRQ_CPU_CLOCK);
	else
		spurious_interrupt();
}

void __init ar5312_arch_init_irq(void)
{
	struct irq_domain *domain;
	unsigned irq;

	ath25_irq_dispatch = ar5312_irq_dispatch;

	domain = irq_domain_add_linear(NULL, AR5312_MISC_IRQ_COUNT,
				       &ar5312_misc_irq_domain_ops, NULL);
	if (!domain)
		panic("Failed to add IRQ domain");

	irq = irq_create_mapping(domain, AR5312_MISC_IRQ_AHB_PROC);
	setup_irq(irq, &ar5312_ahb_err_interrupt);

	irq_set_chained_handler(AR5312_IRQ_MISC, ar5312_misc_irq_handler);
	irq_set_handler_data(AR5312_IRQ_MISC, domain);

	ar5312_misc_irq_domain = domain;
}

static void __init ar5312_flash_init(void)
{
	void __iomem *flashctl_base;
	u32 ctl;

	flashctl_base = ioremap_nocache(AR5312_FLASHCTL_BASE,
					AR5312_FLASHCTL_SIZE);

	/*
	 * Configure flash bank 0.
	 * Assume 8M window size. Flash will be aliased if it's smaller
	 */
	ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL0);
	ctl &= AR5312_FLASHCTL_MW;
	ctl |= AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC_8M | AR5312_FLASHCTL_RBLE;
	ctl |= 0x01 << AR5312_FLASHCTL_IDCY_S;
	ctl |= 0x07 << AR5312_FLASHCTL_WST1_S;
	ctl |= 0x07 << AR5312_FLASHCTL_WST2_S;
	__raw_writel(ctl, flashctl_base + AR5312_FLASHCTL0);

	/* Disable other flash banks */
	ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL1);
	ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC);
	__raw_writel(ctl, flashctl_base + AR5312_FLASHCTL1);
	ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL2);
	ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC);
	__raw_writel(ctl, flashctl_base + AR5312_FLASHCTL2);

	iounmap(flashctl_base);
}

void __init ar5312_init_devices(void)
{
	struct ath25_boarddata *config;

	ar5312_flash_init();

	/* Locate board/radio config data */
	ath25_find_config(AR5312_FLASH_BASE, AR5312_FLASH_SIZE);
	config = ath25_board.config;

	/* AR2313 has CPU minor rev. 10 */
	if ((current_cpu_data.processor_id & 0xff) == 0x0a)
		ath25_soc = ATH25_SOC_AR2313;

	/* AR2312 shares the same Silicon ID as AR5312 */
	else if (config->flags & BD_ISCASPER)
		ath25_soc = ATH25_SOC_AR2312;

	/* Everything else is probably AR5312 or compatible */
	else
		ath25_soc = ATH25_SOC_AR5312;
}

static void ar5312_restart(char *command)
{
	/* reset the system */
	local_irq_disable();
	while (1)
		ar5312_rst_reg_write(AR5312_RESET, AR5312_RESET_SYSTEM);
}

/*
 * This table is indexed by bits 5..4 of the CLOCKCTL1 register
 * to determine the predevisor value.
 */
static unsigned clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };

static unsigned __init ar5312_cpu_frequency(void)
{
	u32 scratch, devid, clock_ctl1;
	u32 predivide_mask, multiplier_mask, doubler_mask;
	unsigned predivide_shift, multiplier_shift;
	unsigned predivide_select, predivisor, multiplier;

	/* Trust the bootrom's idea of cpu frequency. */
	scratch = ar5312_rst_reg_read(AR5312_SCRATCH);
	if (scratch)
		return scratch;

	devid = ar5312_rst_reg_read(AR5312_REV);
	devid = (devid & AR5312_REV_MAJ) >> AR5312_REV_MAJ_S;
	if (devid == AR5312_REV_MAJ_AR2313) {
		predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
		predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
		multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
		multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
		doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
	} else { /* AR5312 and AR2312 */
		predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
		predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
		multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
		multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
		doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
	}

	/*
	 * Clocking is derived from a fixed 40MHz input clock.
	 *
	 *  cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
	 *  sys_freq = cpu_freq / 4	  (used for APB clock, serial,
	 *				   flash, Timer, Watchdog Timer)
	 *
	 *  cnt_freq = cpu_freq / 2	  (use for CPU count/compare)
	 *
	 * So, for example, with a PLL multiplier of 5, we have
	 *
	 *  cpu_freq = 200MHz
	 *  sys_freq = 50MHz
	 *  cnt_freq = 100MHz
	 *
	 * We compute the CPU frequency, based on PLL settings.
	 */

	clock_ctl1 = ar5312_rst_reg_read(AR5312_CLOCKCTL1);
	predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
	predivisor = clockctl1_predivide_table[predivide_select];
	multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;

	if (clock_ctl1 & doubler_mask)
		multiplier <<= 1;

	return (40000000 / predivisor) * multiplier;
}

static inline unsigned ar5312_sys_frequency(void)
{
	return ar5312_cpu_frequency() / 4;
}

void __init ar5312_plat_time_init(void)
{
	mips_hpt_frequency = ar5312_cpu_frequency() / 2;
}

void __init ar5312_plat_mem_setup(void)
{
	void __iomem *sdram_base;
	u32 memsize, memcfg, bank0_ac, bank1_ac;
	u32 devid;

	/* Detect memory size */
	sdram_base = ioremap_nocache(AR5312_SDRAMCTL_BASE,
				     AR5312_SDRAMCTL_SIZE);
	memcfg = __raw_readl(sdram_base + AR5312_MEM_CFG1);
	bank0_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC0);
	bank1_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC1);
	memsize = (bank0_ac ? (1 << (bank0_ac + 1)) : 0) +
		  (bank1_ac ? (1 << (bank1_ac + 1)) : 0);
	memsize <<= 20;
	add_memory_region(0, memsize, BOOT_MEM_RAM);
	iounmap(sdram_base);

	ar5312_rst_base = ioremap_nocache(AR5312_RST_BASE, AR5312_RST_SIZE);

	devid = ar5312_rst_reg_read(AR5312_REV);
	devid >>= AR5312_REV_WMAC_MIN_S;
	devid &= AR5312_REV_CHIP;
	ath25_board.devid = (u16)devid;

	/* Clear any lingering AHB errors */
	ar5312_rst_reg_read(AR5312_PROCADDR);
	ar5312_rst_reg_read(AR5312_DMAADDR);
	ar5312_rst_reg_write(AR5312_WDT_CTRL, AR5312_WDT_CTRL_IGNORE);

	_machine_restart = ar5312_restart;
}

void __init ar5312_arch_init(void)
{
	unsigned irq = irq_create_mapping(ar5312_misc_irq_domain,
					  AR5312_MISC_IRQ_UART0);

	ath25_serial_setup(AR5312_UART0_BASE, irq, ar5312_sys_frequency());
}
Commit	Line	Data
3b12308f SR	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
	7	* Copyright (C) 2006 FON Technology, SL.
	8	* Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
	9	* Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
	10	* Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
	11	*/
	12
	13	/*
	14	* Platform devices for Atheros AR5312 SoCs
	15	*/
	16
	17	#include <linux/init.h>
	18	#include <linux/kernel.h>
1753e74e SR	19	#include <linux/bitops.h>
	20	#include <linux/irqdomain.h>
	21	#include <linux/interrupt.h>
3b12308f SR	22	#include <linux/reboot.h>
	23	#include <asm/bootinfo.h>
	24	#include <asm/reboot.h>
	25	#include <asm/time.h>
	26
1654861f SR	27	#include <ath25_platform.h>
1654861f SR	28
3b12308f SR	29	#include "devices.h"
	30	#include "ar5312.h"
	31	#include "ar5312_regs.h"
	32
	33	static void __iomem *ar5312_rst_base;
1753e74e	34	static struct irq_domain *ar5312_misc_irq_domain;
3b12308f SR	35
	36	static inline u32 ar5312_rst_reg_read(u32 reg)
	37	{
	38	return __raw_readl(ar5312_rst_base + reg);
	39	}
	40
	41	static inline void ar5312_rst_reg_write(u32 reg, u32 val)
	42	{
	43	__raw_writel(val, ar5312_rst_base + reg);
	44	}
	45
	46	static inline void ar5312_rst_reg_mask(u32 reg, u32 mask, u32 val)
	47	{
	48	u32 ret = ar5312_rst_reg_read(reg);
	49
	50	ret &= ~mask;
	51	ret \|= val;
	52	ar5312_rst_reg_write(reg, ret);
	53	}
	54
1753e74e SR	55	static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id)
	56	{
	57	u32 proc1 = ar5312_rst_reg_read(AR5312_PROC1);
	58	u32 proc_addr = ar5312_rst_reg_read(AR5312_PROCADDR); /* clears error */
	59	u32 dma1 = ar5312_rst_reg_read(AR5312_DMA1);
	60	u32 dma_addr = ar5312_rst_reg_read(AR5312_DMAADDR); /* clears error */
	61
	62	pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
	63	proc_addr, proc1, dma_addr, dma1);
	64
	65	machine_restart("AHB error"); /* Catastrophic failure */
	66	return IRQ_HANDLED;
	67	}
	68
	69	static struct irqaction ar5312_ahb_err_interrupt = {
	70	.handler = ar5312_ahb_err_handler,
	71	.name = "ar5312-ahb-error",
	72	};
	73
	74	static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
	75	{
	76	u32 pending = ar5312_rst_reg_read(AR5312_ISR) &
	77	ar5312_rst_reg_read(AR5312_IMR);
	78	unsigned nr, misc_irq = 0;
	79
	80	if (pending) {
	81	struct irq_domain *domain = irq_get_handler_data(irq);
	82
	83	nr = __ffs(pending);
	84	misc_irq = irq_find_mapping(domain, nr);
	85	}
	86
	87	if (misc_irq) {
	88	generic_handle_irq(misc_irq);
	89	if (nr == AR5312_MISC_IRQ_TIMER)
	90	ar5312_rst_reg_read(AR5312_TIMER);
	91	} else {
	92	spurious_interrupt();
	93	}
	94	}
	95
	96	/* Enable the specified AR5312_MISC_IRQ interrupt */
	97	static void ar5312_misc_irq_unmask(struct irq_data *d)
	98	{
	99	ar5312_rst_reg_mask(AR5312_IMR, 0, BIT(d->hwirq));
	100	}
	101
	102	/* Disable the specified AR5312_MISC_IRQ interrupt */
	103	static void ar5312_misc_irq_mask(struct irq_data *d)
	104	{
	105	ar5312_rst_reg_mask(AR5312_IMR, BIT(d->hwirq), 0);
	106	ar5312_rst_reg_read(AR5312_IMR); /* flush write buffer */
	107	}
	108
	109	static struct irq_chip ar5312_misc_irq_chip = {
	110	.name = "ar5312-misc",
	111	.irq_unmask = ar5312_misc_irq_unmask,
	112	.irq_mask = ar5312_misc_irq_mask,
	113	};
	114
	115	static int ar5312_misc_irq_map(struct irq_domain *d, unsigned irq,
	116	irq_hw_number_t hw)
	117	{
	118	irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip, handle_level_irq);
119	return 0;
120	}
121
122	static struct irq_domain_ops ar5312_misc_irq_domain_ops = {
123	.map = ar5312_misc_irq_map,
124	};
125
126	static void ar5312_irq_dispatch(void)
127	{
128	u32 pending = read_c0_status() & read_c0_cause();
129
130	if (pending & CAUSEF_IP2)
131	do_IRQ(AR5312_IRQ_WLAN0);
132	else if (pending & CAUSEF_IP5)
133	do_IRQ(AR5312_IRQ_WLAN1);
134	else if (pending & CAUSEF_IP6)
135	do_IRQ(AR5312_IRQ_MISC);
136	else if (pending & CAUSEF_IP7)
137	do_IRQ(ATH25_IRQ_CPU_CLOCK);
138	else
139	spurious_interrupt();
140	}
141
142	void __init ar5312_arch_init_irq(void)
143	{
144	struct irq_domain *domain;
145	unsigned irq;
146
147	ath25_irq_dispatch = ar5312_irq_dispatch;
148
149	domain = irq_domain_add_linear(NULL, AR5312_MISC_IRQ_COUNT,
150	&ar5312_misc_irq_domain_ops, NULL);
151	if (!domain)
152	panic("Failed to add IRQ domain");
153
154	irq = irq_create_mapping(domain, AR5312_MISC_IRQ_AHB_PROC);
155	setup_irq(irq, &ar5312_ahb_err_interrupt);
156
157	irq_set_chained_handler(AR5312_IRQ_MISC, ar5312_misc_irq_handler);
158	irq_set_handler_data(AR5312_IRQ_MISC, domain);
159
160	ar5312_misc_irq_domain = domain;
161	}
162
a7473717 SR	163	static void __init ar5312_flash_init(void)
	164	{
	165	void __iomem *flashctl_base;
	166	u32 ctl;
	167
	168	flashctl_base = ioremap_nocache(AR5312_FLASHCTL_BASE,
	169	AR5312_FLASHCTL_SIZE);
	170
	171	/*
	172	* Configure flash bank 0.
	173	* Assume 8M window size. Flash will be aliased if it's smaller
	174	*/
	175	ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL0);
	176	ctl &= AR5312_FLASHCTL_MW;
	177	ctl \|= AR5312_FLASHCTL_E \| AR5312_FLASHCTL_AC_8M \| AR5312_FLASHCTL_RBLE;
	178	ctl \|= 0x01 << AR5312_FLASHCTL_IDCY_S;
	179	ctl \|= 0x07 << AR5312_FLASHCTL_WST1_S;
	180	ctl \|= 0x07 << AR5312_FLASHCTL_WST2_S;
	181	__raw_writel(ctl, flashctl_base + AR5312_FLASHCTL0);
	182
	183	/* Disable other flash banks */
	184	ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL1);
	185	ctl &= ~(AR5312_FLASHCTL_E \| AR5312_FLASHCTL_AC);
	186	__raw_writel(ctl, flashctl_base + AR5312_FLASHCTL1);
	187	ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL2);
	188	ctl &= ~(AR5312_FLASHCTL_E \| AR5312_FLASHCTL_AC);
	189	__raw_writel(ctl, flashctl_base + AR5312_FLASHCTL2);
	190
	191	iounmap(flashctl_base);
	192	}
	193
	194	void __init ar5312_init_devices(void)
	195	{
1654861f SR	196	struct ath25_boarddata *config;
1654861f SR	197
a7473717 SR	198	ar5312_flash_init();
	199
	200	/* Locate board/radio config data */
	201	ath25_find_config(AR5312_FLASH_BASE, AR5312_FLASH_SIZE);
1654861f SR	202	config = ath25_board.config;
	203
	204	/* AR2313 has CPU minor rev. 10 */
	205	if ((current_cpu_data.processor_id & 0xff) == 0x0a)
	206	ath25_soc = ATH25_SOC_AR2313;
	207
	208	/* AR2312 shares the same Silicon ID as AR5312 */
	209	else if (config->flags & BD_ISCASPER)
	210	ath25_soc = ATH25_SOC_AR2312;
	211
	212	/* Everything else is probably AR5312 or compatible */
	213	else
	214	ath25_soc = ATH25_SOC_AR5312;
a7473717 SR	215	}
a7473717 SR	216
3b12308f SR	217	static void ar5312_restart(char *command)
	218	{
	219	/* reset the system */
	220	local_irq_disable();
	221	while (1)
	222	ar5312_rst_reg_write(AR5312_RESET, AR5312_RESET_SYSTEM);
	223	}
	224
	225	/*
	226	* This table is indexed by bits 5..4 of the CLOCKCTL1 register
	227	* to determine the predevisor value.
	228	*/
	229	static unsigned clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
	230
	231	static unsigned __init ar5312_cpu_frequency(void)
	232	{
	233	u32 scratch, devid, clock_ctl1;
	234	u32 predivide_mask, multiplier_mask, doubler_mask;
	235	unsigned predivide_shift, multiplier_shift;
	236	unsigned predivide_select, predivisor, multiplier;
	237
	238	/* Trust the bootrom's idea of cpu frequency. */
	239	scratch = ar5312_rst_reg_read(AR5312_SCRATCH);
	240	if (scratch)
	241	return scratch;
	242
	243	devid = ar5312_rst_reg_read(AR5312_REV);
	244	devid = (devid & AR5312_REV_MAJ) >> AR5312_REV_MAJ_S;
	245	if (devid == AR5312_REV_MAJ_AR2313) {
	246	predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
	247	predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
	248	multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
	249	multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
	250	doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
	251	} else { /* AR5312 and AR2312 */
	252	predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
	253	predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
	254	multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
	255	multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
	256	doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
	257	}
	258
	259	/*
	260	* Clocking is derived from a fixed 40MHz input clock.
	261	*
	262	* cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
	263	* sys_freq = cpu_freq / 4 (used for APB clock, serial,
	264	* flash, Timer, Watchdog Timer)
	265	*
	266	* cnt_freq = cpu_freq / 2 (use for CPU count/compare)
	267	*
	268	* So, for example, with a PLL multiplier of 5, we have
	269	*
	270	* cpu_freq = 200MHz
	271	* sys_freq = 50MHz
	272	* cnt_freq = 100MHz
	273	*
	274	* We compute the CPU frequency, based on PLL settings.
	275	*/
	276
	277	clock_ctl1 = ar5312_rst_reg_read(AR5312_CLOCKCTL1);
	278	predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
	279	predivisor = clockctl1_predivide_table[predivide_select];
	280	multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
281
282	if (clock_ctl1 & doubler_mask)
283	multiplier <<= 1;
284
285	return (40000000 / predivisor) * multiplier;
286	}
287
288	static inline unsigned ar5312_sys_frequency(void)
289	{
290	return ar5312_cpu_frequency() / 4;
291	}
292
293	void __init ar5312_plat_time_init(void)
294	{
295	mips_hpt_frequency = ar5312_cpu_frequency() / 2;
296	}
297
298	void __init ar5312_plat_mem_setup(void)
299	{
300	void __iomem *sdram_base;
301	u32 memsize, memcfg, bank0_ac, bank1_ac;
1654861f	302	u32 devid;
3b12308f SR	303
	304	/* Detect memory size */
	305	sdram_base = ioremap_nocache(AR5312_SDRAMCTL_BASE,
	306	AR5312_SDRAMCTL_SIZE);
	307	memcfg = __raw_readl(sdram_base + AR5312_MEM_CFG1);
	308	bank0_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC0);
	309	bank1_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC1);
	310	memsize = (bank0_ac ? (1 << (bank0_ac + 1)) : 0) +
	311	(bank1_ac ? (1 << (bank1_ac + 1)) : 0);
	312	memsize <<= 20;
	313	add_memory_region(0, memsize, BOOT_MEM_RAM);
	314	iounmap(sdram_base);
	315
	316	ar5312_rst_base = ioremap_nocache(AR5312_RST_BASE, AR5312_RST_SIZE);
	317
1654861f SR	318	devid = ar5312_rst_reg_read(AR5312_REV);
	319	devid >>= AR5312_REV_WMAC_MIN_S;
	320	devid &= AR5312_REV_CHIP;
	321	ath25_board.devid = (u16)devid;
	322
3b12308f SR	323	/* Clear any lingering AHB errors */
	324	ar5312_rst_reg_read(AR5312_PROCADDR);
	325	ar5312_rst_reg_read(AR5312_DMAADDR);
	326	ar5312_rst_reg_write(AR5312_WDT_CTRL, AR5312_WDT_CTRL_IGNORE);
	327
	328	_machine_restart = ar5312_restart;
	329	}
1ac91b1f SR	330
	331	void __init ar5312_arch_init(void)
	332	{
	333	unsigned irq = irq_create_mapping(ar5312_misc_irq_domain,
	334	AR5312_MISC_IRQ_UART0);
	335
	336	ath25_serial_setup(AR5312_UART0_BASE, irq, ar5312_sys_frequency());
	337	}