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3b12308f SR |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. | |
7 | * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org> | |
8 | * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org> | |
9 | */ | |
10 | ||
11 | #ifndef __ASM_MACH_ATH25_AR5312_REGS_H | |
12 | #define __ASM_MACH_ATH25_AR5312_REGS_H | |
13 | ||
1753e74e SR |
14 | /* |
15 | * IRQs | |
16 | */ | |
17 | #define AR5312_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */ | |
18 | #define AR5312_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */ | |
19 | #define AR5312_IRQ_ENET1 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */ | |
20 | #define AR5312_IRQ_WLAN1 (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */ | |
21 | #define AR5312_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */ | |
22 | ||
23 | /* | |
24 | * Miscellaneous interrupts, which share IP6. | |
25 | */ | |
26 | #define AR5312_MISC_IRQ_TIMER 0 | |
27 | #define AR5312_MISC_IRQ_AHB_PROC 1 | |
28 | #define AR5312_MISC_IRQ_AHB_DMA 2 | |
29 | #define AR5312_MISC_IRQ_GPIO 3 | |
30 | #define AR5312_MISC_IRQ_UART0 4 | |
31 | #define AR5312_MISC_IRQ_UART0_DMA 5 | |
32 | #define AR5312_MISC_IRQ_WATCHDOG 6 | |
33 | #define AR5312_MISC_IRQ_LOCAL 7 | |
34 | #define AR5312_MISC_IRQ_SPI 8 | |
35 | #define AR5312_MISC_IRQ_COUNT 9 | |
36 | ||
3b12308f SR |
37 | /* |
38 | * Address Map | |
39 | * | |
40 | * The AR5312 supports 2 enet MACS, even though many reference boards only | |
41 | * actually use 1 of them (i.e. Only MAC 0 is actually connected to an enet | |
42 | * PHY or PHY switch. The AR2312 supports 1 enet MAC. | |
43 | */ | |
44 | #define AR5312_WLAN0_BASE 0x18000000 | |
45 | #define AR5312_ENET0_BASE 0x18100000 | |
46 | #define AR5312_ENET1_BASE 0x18200000 | |
47 | #define AR5312_SDRAMCTL_BASE 0x18300000 | |
48 | #define AR5312_SDRAMCTL_SIZE 0x00000010 | |
49 | #define AR5312_FLASHCTL_BASE 0x18400000 | |
50 | #define AR5312_FLASHCTL_SIZE 0x00000010 | |
51 | #define AR5312_WLAN1_BASE 0x18500000 | |
52 | #define AR5312_UART0_BASE 0x1c000000 /* UART MMR */ | |
53 | #define AR5312_GPIO_BASE 0x1c002000 | |
54 | #define AR5312_GPIO_SIZE 0x00000010 | |
55 | #define AR5312_RST_BASE 0x1c003000 | |
56 | #define AR5312_RST_SIZE 0x00000100 | |
57 | #define AR5312_FLASH_BASE 0x1e000000 | |
58 | #define AR5312_FLASH_SIZE 0x00800000 | |
59 | ||
60 | /* | |
61 | * Need these defines to determine true number of ethernet MACs | |
62 | */ | |
63 | #define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ | |
64 | #define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ | |
65 | #define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */ | |
66 | ||
67 | /* Reset/Timer Block Address Map */ | |
68 | #define AR5312_TIMER 0x0000 /* countdown timer */ | |
69 | #define AR5312_RELOAD 0x0004 /* timer reload value */ | |
70 | #define AR5312_WDT_CTRL 0x0008 /* watchdog cntrl */ | |
71 | #define AR5312_WDT_TIMER 0x000c /* watchdog timer */ | |
72 | #define AR5312_ISR 0x0010 /* Intr Status Reg */ | |
73 | #define AR5312_IMR 0x0014 /* Intr Mask Reg */ | |
74 | #define AR5312_RESET 0x0020 | |
75 | #define AR5312_CLOCKCTL1 0x0064 | |
76 | #define AR5312_SCRATCH 0x006c | |
77 | #define AR5312_PROCADDR 0x0070 | |
78 | #define AR5312_PROC1 0x0074 | |
79 | #define AR5312_DMAADDR 0x0078 | |
80 | #define AR5312_DMA1 0x007c | |
81 | #define AR5312_ENABLE 0x0080 /* interface enb */ | |
82 | #define AR5312_REV 0x0090 /* revision */ | |
83 | ||
84 | /* AR5312_WDT_CTRL register bit field definitions */ | |
85 | #define AR5312_WDT_CTRL_IGNORE 0x00000000 /* ignore expiration */ | |
86 | #define AR5312_WDT_CTRL_NMI 0x00000001 | |
87 | #define AR5312_WDT_CTRL_RESET 0x00000002 | |
88 | ||
89 | /* AR5312_ISR register bit field definitions */ | |
90 | #define AR5312_ISR_TIMER 0x00000001 | |
91 | #define AR5312_ISR_AHBPROC 0x00000002 | |
92 | #define AR5312_ISR_AHBDMA 0x00000004 | |
93 | #define AR5312_ISR_GPIO 0x00000008 | |
94 | #define AR5312_ISR_UART0 0x00000010 | |
95 | #define AR5312_ISR_UART0DMA 0x00000020 | |
96 | #define AR5312_ISR_WD 0x00000040 | |
97 | #define AR5312_ISR_LOCAL 0x00000080 | |
98 | ||
99 | /* AR5312_RESET register bit field definitions */ | |
100 | #define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */ | |
101 | #define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */ | |
102 | #define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC/BB */ | |
103 | #define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */ | |
104 | #define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */ | |
105 | #define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 MAC */ | |
106 | #define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 MAC */ | |
107 | #define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 */ | |
108 | #define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */ | |
109 | #define AR5312_RESET_APB 0x00000400 /* cold reset APB ar5312 */ | |
110 | #define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */ | |
111 | #define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */ | |
112 | #define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BB */ | |
113 | #define AR5312_RESET_NMI 0x00010000 /* send an NMI to the CPU */ | |
114 | #define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 MAC */ | |
115 | #define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 BB */ | |
116 | #define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */ | |
117 | #define AR5312_RESET_WDOG 0x00100000 /* last reset was a wdt */ | |
118 | ||
119 | #define AR5312_RESET_WMAC0_BITS (AR5312_RESET_WLAN0 |\ | |
120 | AR5312_RESET_WARM_WLAN0_MAC |\ | |
121 | AR5312_RESET_WARM_WLAN0_BB) | |
122 | ||
123 | #define AR5312_RESET_WMAC1_BITS (AR5312_RESET_WLAN1 |\ | |
124 | AR5312_RESET_WARM_WLAN1_MAC |\ | |
125 | AR5312_RESET_WARM_WLAN1_BB) | |
126 | ||
127 | /* AR5312_CLOCKCTL1 register bit field definitions */ | |
128 | #define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030 | |
129 | #define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4 | |
130 | #define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00 | |
131 | #define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8 | |
132 | #define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000 | |
133 | ||
134 | /* Valid for AR5312 and AR2312 */ | |
135 | #define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030 | |
136 | #define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4 | |
137 | #define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00 | |
138 | #define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8 | |
139 | #define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000 | |
140 | ||
141 | /* Valid for AR2313 */ | |
142 | #define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000 | |
143 | #define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12 | |
144 | #define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000 | |
145 | #define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16 | |
146 | #define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000 | |
147 | ||
148 | /* AR5312_ENABLE register bit field definitions */ | |
149 | #define AR5312_ENABLE_WLAN0 0x00000001 | |
150 | #define AR5312_ENABLE_ENET0 0x00000002 | |
151 | #define AR5312_ENABLE_ENET1 0x00000004 | |
152 | #define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x00000008/* UART & WLAN1 PIO */ | |
153 | #define AR5312_ENABLE_WLAN1_DMA 0x00000010/* WLAN1 DMAs */ | |
154 | #define AR5312_ENABLE_WLAN1 (AR5312_ENABLE_UART_AND_WLAN1_PIO |\ | |
155 | AR5312_ENABLE_WLAN1_DMA) | |
156 | ||
157 | /* AR5312_REV register bit field definitions */ | |
158 | #define AR5312_REV_WMAC_MAJ 0x0000f000 | |
159 | #define AR5312_REV_WMAC_MAJ_S 12 | |
160 | #define AR5312_REV_WMAC_MIN 0x00000f00 | |
161 | #define AR5312_REV_WMAC_MIN_S 8 | |
162 | #define AR5312_REV_MAJ 0x000000f0 | |
163 | #define AR5312_REV_MAJ_S 4 | |
164 | #define AR5312_REV_MIN 0x0000000f | |
165 | #define AR5312_REV_MIN_S 0 | |
166 | #define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN) | |
167 | ||
168 | /* Major revision numbers, bits 7..4 of Revision ID register */ | |
169 | #define AR5312_REV_MAJ_AR5312 0x4 | |
170 | #define AR5312_REV_MAJ_AR2313 0x5 | |
171 | ||
172 | /* Minor revision numbers, bits 3..0 of Revision ID register */ | |
173 | #define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */ | |
174 | #define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */ | |
175 | ||
176 | /* | |
177 | * ARM Flash Controller -- 3 flash banks with either x8 or x16 devices | |
178 | */ | |
179 | #define AR5312_FLASHCTL0 0x0000 | |
180 | #define AR5312_FLASHCTL1 0x0004 | |
181 | #define AR5312_FLASHCTL2 0x0008 | |
182 | ||
183 | /* AR5312_FLASHCTL register bit field definitions */ | |
184 | #define AR5312_FLASHCTL_IDCY 0x0000000f /* Idle cycle turnaround time */ | |
185 | #define AR5312_FLASHCTL_IDCY_S 0 | |
186 | #define AR5312_FLASHCTL_WST1 0x000003e0 /* Wait state 1 */ | |
187 | #define AR5312_FLASHCTL_WST1_S 5 | |
188 | #define AR5312_FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */ | |
189 | #define AR5312_FLASHCTL_WST2 0x0000f800 /* Wait state 2 */ | |
190 | #define AR5312_FLASHCTL_WST2_S 11 | |
191 | #define AR5312_FLASHCTL_AC 0x00070000 /* Flash addr check (added) */ | |
192 | #define AR5312_FLASHCTL_AC_S 16 | |
193 | #define AR5312_FLASHCTL_AC_128K 0x00000000 | |
194 | #define AR5312_FLASHCTL_AC_256K 0x00010000 | |
195 | #define AR5312_FLASHCTL_AC_512K 0x00020000 | |
196 | #define AR5312_FLASHCTL_AC_1M 0x00030000 | |
197 | #define AR5312_FLASHCTL_AC_2M 0x00040000 | |
198 | #define AR5312_FLASHCTL_AC_4M 0x00050000 | |
199 | #define AR5312_FLASHCTL_AC_8M 0x00060000 | |
200 | #define AR5312_FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */ | |
201 | #define AR5312_FLASHCTL_E 0x00080000 /* Flash bank enable (added) */ | |
202 | #define AR5312_FLASHCTL_BUSERR 0x01000000 /* Bus transfer error flag */ | |
203 | #define AR5312_FLASHCTL_WPERR 0x02000000 /* Write protect error flag */ | |
204 | #define AR5312_FLASHCTL_WP 0x04000000 /* Write protect */ | |
205 | #define AR5312_FLASHCTL_BM 0x08000000 /* Burst mode */ | |
206 | #define AR5312_FLASHCTL_MW 0x30000000 /* Mem width */ | |
207 | #define AR5312_FLASHCTL_MW8 0x00000000 /* Mem width x8 */ | |
208 | #define AR5312_FLASHCTL_MW16 0x10000000 /* Mem width x16 */ | |
209 | #define AR5312_FLASHCTL_MW32 0x20000000 /* Mem width x32 (not supp) */ | |
210 | #define AR5312_FLASHCTL_ATNR 0x00000000 /* Access == no retry */ | |
211 | #define AR5312_FLASHCTL_ATR 0x80000000 /* Access == retry every */ | |
212 | #define AR5312_FLASHCTL_ATR4 0xc0000000 /* Access == retry every 4 */ | |
213 | ||
214 | /* | |
215 | * ARM SDRAM Controller -- just enough to determine memory size | |
216 | */ | |
217 | #define AR5312_MEM_CFG1 0x0004 | |
218 | ||
219 | #define AR5312_MEM_CFG1_AC0_M 0x00000700 /* bank 0: SDRAM addr check */ | |
220 | #define AR5312_MEM_CFG1_AC0_S 8 | |
221 | #define AR5312_MEM_CFG1_AC1_M 0x00007000 /* bank 1: SDRAM addr check */ | |
222 | #define AR5312_MEM_CFG1_AC1_S 12 | |
223 | ||
224 | #endif /* __ASM_MACH_ATH25_AR5312_REGS_H */ |