[deliverable/linux.git] / arch / mips / ath79 / setup.c

/*
 *  Atheros AR71XX/AR724X/AR913X specific setup
 *
 *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
 *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
 *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 *
 *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/bootmem.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of_platform.h>
#include <linux/of_fdt.h>

#include <asm/bootinfo.h>
#include <asm/idle.h>
#include <asm/time.h>		/* for mips_hpt_frequency */
#include <asm/reboot.h>		/* for _machine_{restart,halt} */
#include <asm/mips_machine.h>
#include <asm/prom.h>
#include <asm/fw/fw.h>

#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"
#include "dev-common.h"
#include "machtypes.h"

#define ATH79_SYS_TYPE_LEN	64

static char ath79_sys_type[ATH79_SYS_TYPE_LEN];

static void ath79_restart(char *command)
{
	ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
	for (;;)
		if (cpu_wait)
			cpu_wait();
}

static void ath79_halt(void)
{
	while (1)
		cpu_wait();
}

static void __init ath79_detect_sys_type(void)
{
	char *chip = "????";
	u32 id;
	u32 major;
	u32 minor;
	u32 rev = 0;

	id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
	major = id & REV_ID_MAJOR_MASK;

	switch (major) {
	case REV_ID_MAJOR_AR71XX:
		minor = id & AR71XX_REV_ID_MINOR_MASK;
		rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
		rev &= AR71XX_REV_ID_REVISION_MASK;
		switch (minor) {
		case AR71XX_REV_ID_MINOR_AR7130:
			ath79_soc = ATH79_SOC_AR7130;
			chip = "7130";
			break;

		case AR71XX_REV_ID_MINOR_AR7141:
			ath79_soc = ATH79_SOC_AR7141;
			chip = "7141";
			break;

		case AR71XX_REV_ID_MINOR_AR7161:
			ath79_soc = ATH79_SOC_AR7161;
			chip = "7161";
			break;
		}
		break;

	case REV_ID_MAJOR_AR7240:
		ath79_soc = ATH79_SOC_AR7240;
		chip = "7240";
		rev = id & AR724X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR7241:
		ath79_soc = ATH79_SOC_AR7241;
		chip = "7241";
		rev = id & AR724X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR7242:
		ath79_soc = ATH79_SOC_AR7242;
		chip = "7242";
		rev = id & AR724X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR913X:
		minor = id & AR913X_REV_ID_MINOR_MASK;
		rev = id >> AR913X_REV_ID_REVISION_SHIFT;
		rev &= AR913X_REV_ID_REVISION_MASK;
		switch (minor) {
		case AR913X_REV_ID_MINOR_AR9130:
			ath79_soc = ATH79_SOC_AR9130;
			chip = "9130";
			break;

		case AR913X_REV_ID_MINOR_AR9132:
			ath79_soc = ATH79_SOC_AR9132;
			chip = "9132";
			break;
		}
		break;

	case REV_ID_MAJOR_AR9330:
		ath79_soc = ATH79_SOC_AR9330;
		chip = "9330";
		rev = id & AR933X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR9331:
		ath79_soc = ATH79_SOC_AR9331;
		chip = "9331";
		rev = id & AR933X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR9341:
		ath79_soc = ATH79_SOC_AR9341;
		chip = "9341";
		rev = id & AR934X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR9342:
		ath79_soc = ATH79_SOC_AR9342;
		chip = "9342";
		rev = id & AR934X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR9344:
		ath79_soc = ATH79_SOC_AR9344;
		chip = "9344";
		rev = id & AR934X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_QCA9556:
		ath79_soc = ATH79_SOC_QCA9556;
		chip = "9556";
		rev = id & QCA955X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_QCA9558:
		ath79_soc = ATH79_SOC_QCA9558;
		chip = "9558";
		rev = id & QCA955X_REV_ID_REVISION_MASK;
		break;

	default:
		panic("ath79: unknown SoC, id:0x%08x", id);
	}

	ath79_soc_rev = rev;

	if (soc_is_qca955x())
		sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
			chip, rev);
	else
		sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
	pr_info("SoC: %s\n", ath79_sys_type);
}

const char *get_system_type(void)
{
	return ath79_sys_type;
}

int get_c0_perfcount_int(void)
{
	return ATH79_MISC_IRQ(5);
}
EXPORT_SYMBOL_GPL(get_c0_perfcount_int);

unsigned int get_c0_compare_int(void)
{
	return CP0_LEGACY_COMPARE_IRQ;
}

void __init plat_mem_setup(void)
{
	unsigned long fdt_start;

	set_io_port_base(KSEG1);

	/* Get the position of the FDT passed by the bootloader */
	fdt_start = fw_getenvl("fdt_start");
	if (fdt_start)
		__dt_setup_arch((void *)KSEG0ADDR(fdt_start));
	else if (fw_arg0 == -2)
		__dt_setup_arch((void *)KSEG0ADDR(fw_arg1));

	if (mips_machtype != ATH79_MACH_GENERIC_OF) {
		ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
						   AR71XX_RESET_SIZE);
		ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
						 AR71XX_PLL_SIZE);
		ath79_detect_sys_type();
		ath79_ddr_ctrl_init();

		detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);

		/* OF machines should use the reset driver */
		_machine_restart = ath79_restart;
	}

	_machine_halt = ath79_halt;
	pm_power_off = ath79_halt;
}

static void __init ath79_of_plat_time_init(void)
{
	struct device_node *np;
	struct clk *clk;
	unsigned long cpu_clk_rate;

	of_clk_init(NULL);

	np = of_get_cpu_node(0, NULL);
	if (!np) {
		pr_err("Failed to get CPU node\n");
		return;
	}

	clk = of_clk_get(np, 0);
	if (IS_ERR(clk)) {
		pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk));
		return;
	}

	cpu_clk_rate = clk_get_rate(clk);

	pr_info("CPU clock: %lu.%03lu MHz\n",
		cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000);

	mips_hpt_frequency = cpu_clk_rate / 2;

	clk_put(clk);
}

void __init plat_time_init(void)
{
	unsigned long cpu_clk_rate;
	unsigned long ahb_clk_rate;
	unsigned long ddr_clk_rate;
	unsigned long ref_clk_rate;

	if (IS_ENABLED(CONFIG_OF) && mips_machtype == ATH79_MACH_GENERIC_OF) {
		ath79_of_plat_time_init();
		return;
	}

	ath79_clocks_init();

	cpu_clk_rate = ath79_get_sys_clk_rate("cpu");
	ahb_clk_rate = ath79_get_sys_clk_rate("ahb");
	ddr_clk_rate = ath79_get_sys_clk_rate("ddr");
	ref_clk_rate = ath79_get_sys_clk_rate("ref");

	pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, Ref:%lu.%03luMHz\n",
		cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000,
		ddr_clk_rate / 1000000, (ddr_clk_rate / 1000) % 1000,
		ahb_clk_rate / 1000000, (ahb_clk_rate / 1000) % 1000,
		ref_clk_rate / 1000000, (ref_clk_rate / 1000) % 1000);

	mips_hpt_frequency = cpu_clk_rate / 2;
}

static int __init ath79_setup(void)
{
	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
	if  (mips_machtype == ATH79_MACH_GENERIC_OF)
		return 0;

	ath79_gpio_init();
	ath79_register_uart();
	ath79_register_wdt();

	mips_machine_setup();

	return 0;
}

arch_initcall(ath79_setup);

void __init device_tree_init(void)
{
	unflatten_and_copy_device_tree();
}

MIPS_MACHINE(ATH79_MACH_GENERIC,
	     "Generic",
	     "Generic AR71XX/AR724X/AR913X based board",
	     NULL);

MIPS_MACHINE(ATH79_MACH_GENERIC_OF,
	     "DTB",
	     "Generic AR71XX/AR724X/AR913X based board (DT)",
	     NULL);
Commit	Line	Data
d4a67d9d GJ	1	/*
	2	* Atheros AR71XX/AR724X/AR913X specific setup
	3	*
d8411466	4	* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
d4a67d9d GJ	5	* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
	6	* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
	7	*
d8411466	8	* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
d4a67d9d GJ	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License version 2 as published
	12	* by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/kernel.h>
	16	#include <linux/init.h>
	17	#include <linux/bootmem.h>
	18	#include <linux/err.h>
	19	#include <linux/clk.h>
3bdf1071	20	#include <linux/clk-provider.h>
03c8c407 AB	21	#include <linux/of_platform.h>
03c8c407 AB	22	#include <linux/of_fdt.h>
d4a67d9d GJ	23
d4a67d9d GJ	24	#include <asm/bootinfo.h>
bdc92d74	25	#include <asm/idle.h>
d4a67d9d GJ	26	#include <asm/time.h> /* for mips_hpt_frequency */
d4a67d9d GJ	27	#include <asm/reboot.h> /* for _machine_{restart,halt} */
0aabf1a4	28	#include <asm/mips_machine.h>
03c8c407 AB	29	#include <asm/prom.h>
03c8c407 AB	30	#include <asm/fw/fw.h>
d4a67d9d GJ	31
	32	#include <asm/mach-ath79/ath79.h>
	33	#include <asm/mach-ath79/ar71xx_regs.h>
	34	#include "common.h"
	35	#include "dev-common.h"
0aabf1a4	36	#include "machtypes.h"
d4a67d9d GJ	37
	38	#define ATH79_SYS_TYPE_LEN 64
	39
d4a67d9d GJ	40	static char ath79_sys_type[ATH79_SYS_TYPE_LEN];
	41
	42	static void ath79_restart(char *command)
	43	{
	44	ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
	45	for (;;)
	46	if (cpu_wait)
	47	cpu_wait();
	48	}
	49
	50	static void ath79_halt(void)
	51	{
	52	while (1)
	53	cpu_wait();
	54	}
	55
d4a67d9d GJ	56	static void __init ath79_detect_sys_type(void)
	57	{
	58	char *chip = "????";
	59	u32 id;
	60	u32 major;
	61	u32 minor;
	62	u32 rev = 0;
	63
	64	id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
	65	major = id & REV_ID_MAJOR_MASK;
	66
	67	switch (major) {
	68	case REV_ID_MAJOR_AR71XX:
	69	minor = id & AR71XX_REV_ID_MINOR_MASK;
	70	rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
	71	rev &= AR71XX_REV_ID_REVISION_MASK;
	72	switch (minor) {
	73	case AR71XX_REV_ID_MINOR_AR7130:
	74	ath79_soc = ATH79_SOC_AR7130;
	75	chip = "7130";
	76	break;
	77
	78	case AR71XX_REV_ID_MINOR_AR7141:
	79	ath79_soc = ATH79_SOC_AR7141;
	80	chip = "7141";
	81	break;
	82
	83	case AR71XX_REV_ID_MINOR_AR7161:
	84	ath79_soc = ATH79_SOC_AR7161;
	85	chip = "7161";
	86	break;
	87	}
	88	break;
	89
	90	case REV_ID_MAJOR_AR7240:
	91	ath79_soc = ATH79_SOC_AR7240;
	92	chip = "7240";
8bed1288	93	rev = id & AR724X_REV_ID_REVISION_MASK;
d4a67d9d GJ	94	break;
	95
	96	case REV_ID_MAJOR_AR7241:
	97	ath79_soc = ATH79_SOC_AR7241;
	98	chip = "7241";
8bed1288	99	rev = id & AR724X_REV_ID_REVISION_MASK;
d4a67d9d GJ	100	break;
	101
	102	case REV_ID_MAJOR_AR7242:
	103	ath79_soc = ATH79_SOC_AR7242;
	104	chip = "7242";
8bed1288	105	rev = id & AR724X_REV_ID_REVISION_MASK;
d4a67d9d GJ	106	break;
	107
	108	case REV_ID_MAJOR_AR913X:
	109	minor = id & AR913X_REV_ID_MINOR_MASK;
	110	rev = id >> AR913X_REV_ID_REVISION_SHIFT;
	111	rev &= AR913X_REV_ID_REVISION_MASK;
	112	switch (minor) {
	113	case AR913X_REV_ID_MINOR_AR9130:
	114	ath79_soc = ATH79_SOC_AR9130;
	115	chip = "9130";
	116	break;
	117
	118	case AR913X_REV_ID_MINOR_AR9132:
	119	ath79_soc = ATH79_SOC_AR9132;
	120	chip = "9132";
	121	break;
	122	}
	123	break;
	124
80a7ed81 GJ	125	case REV_ID_MAJOR_AR9330:
	126	ath79_soc = ATH79_SOC_AR9330;
	127	chip = "9330";
	128	rev = id & AR933X_REV_ID_REVISION_MASK;
	129	break;
	130
	131	case REV_ID_MAJOR_AR9331:
	132	ath79_soc = ATH79_SOC_AR9331;
	133	chip = "9331";
	134	rev = id & AR933X_REV_ID_REVISION_MASK;
	135	break;
	136
d8411466 GJ	137	case REV_ID_MAJOR_AR9341:
	138	ath79_soc = ATH79_SOC_AR9341;
	139	chip = "9341";
	140	rev = id & AR934X_REV_ID_REVISION_MASK;
	141	break;
	142
	143	case REV_ID_MAJOR_AR9342:
	144	ath79_soc = ATH79_SOC_AR9342;
	145	chip = "9342";
	146	rev = id & AR934X_REV_ID_REVISION_MASK;
	147	break;
	148
	149	case REV_ID_MAJOR_AR9344:
	150	ath79_soc = ATH79_SOC_AR9344;
	151	chip = "9344";
	152	rev = id & AR934X_REV_ID_REVISION_MASK;
	153	break;
	154
2e6c91e3 GJ	155	case REV_ID_MAJOR_QCA9556:
	156	ath79_soc = ATH79_SOC_QCA9556;
	157	chip = "9556";
	158	rev = id & QCA955X_REV_ID_REVISION_MASK;
	159	break;
	160
	161	case REV_ID_MAJOR_QCA9558:
	162	ath79_soc = ATH79_SOC_QCA9558;
	163	chip = "9558";
	164	rev = id & QCA955X_REV_ID_REVISION_MASK;
	165	break;
	166
d4a67d9d	167	default:
ab75dc02	168	panic("ath79: unknown SoC, id:0x%08x", id);
d4a67d9d GJ	169	}
d4a67d9d GJ	170
be5f3623 GJ	171	ath79_soc_rev = rev;
be5f3623 GJ	172
2e6c91e3 GJ	173	if (soc_is_qca955x())
	174	sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
	175	chip, rev);
	176	else
	177	sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
d4a67d9d GJ	178	pr_info("SoC: %s\n", ath79_sys_type);
	179	}
	180
	181	const char *get_system_type(void)
	182	{
	183	return ath79_sys_type;
	184	}
	185
a669efc4 AB	186	int get_c0_perfcount_int(void)
	187	{
	188	return ATH79_MISC_IRQ(5);
	189	}
0cb0985f	190	EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
a669efc4	191
078a55fc	192	unsigned int get_c0_compare_int(void)
d4a67d9d GJ	193	{
	194	return CP0_LEGACY_COMPARE_IRQ;
	195	}
	196
	197	void __init plat_mem_setup(void)
	198	{
03c8c407 AB	199	unsigned long fdt_start;
03c8c407 AB	200
d4a67d9d GJ	201	set_io_port_base(KSEG1);
d4a67d9d GJ	202
03c8c407 AB	203	/* Get the position of the FDT passed by the bootloader */
	204	fdt_start = fw_getenvl("fdt_start");
	205	if (fdt_start)
	206	__dt_setup_arch((void *)KSEG0ADDR(fdt_start));
8f4d4d1b AB	207	else if (fw_arg0 == -2)
8f4d4d1b AB	208	__dt_setup_arch((void *)KSEG0ADDR(fw_arg1));
03c8c407	209
81424d0a	210	if (mips_machtype != ATH79_MACH_GENERIC_OF) {
f4fe969d AP	211	ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
	212	AR71XX_RESET_SIZE);
	213	ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
	214	AR71XX_PLL_SIZE);
	215	ath79_detect_sys_type();
	216	ath79_ddr_ctrl_init();
	217
03c8c407	218	detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
f4fe969d	219
81424d0a AB	220	/* OF machines should use the reset driver */
	221	_machine_restart = ath79_restart;
	222	}
f4fe969d	223
d4a67d9d GJ	224	_machine_halt = ath79_halt;
	225	pm_power_off = ath79_halt;
	226	}
	227
3bdf1071 AP	228	static void __init ath79_of_plat_time_init(void)
	229	{
	230	struct device_node *np;
	231	struct clk *clk;
	232	unsigned long cpu_clk_rate;
	233
	234	of_clk_init(NULL);
	235
	236	np = of_get_cpu_node(0, NULL);
	237	if (!np) {
	238	pr_err("Failed to get CPU node\n");
	239	return;
	240	}
	241
	242	clk = of_clk_get(np, 0);
	243	if (IS_ERR(clk)) {
	244	pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk));
	245	return;
	246	}
	247
	248	cpu_clk_rate = clk_get_rate(clk);
	249
	250	pr_info("CPU clock: %lu.%03lu MHz\n",
	251	cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000);
	252
	253	mips_hpt_frequency = cpu_clk_rate / 2;
	254
	255	clk_put(clk);
	256	}
	257
d4a67d9d GJ	258	void __init plat_time_init(void)
d4a67d9d GJ	259	{
23107802	260	unsigned long cpu_clk_rate;
59a8c10b GJ	261	unsigned long ahb_clk_rate;
	262	unsigned long ddr_clk_rate;
	263	unsigned long ref_clk_rate;
d4a67d9d	264
3bdf1071 AP	265	if (IS_ENABLED(CONFIG_OF) && mips_machtype == ATH79_MACH_GENERIC_OF) {
	266	ath79_of_plat_time_init();
	267	return;
	268	}
	269
2c4f1ac5 GJ	270	ath79_clocks_init();
2c4f1ac5 GJ	271
23107802	272	cpu_clk_rate = ath79_get_sys_clk_rate("cpu");
59a8c10b GJ	273	ahb_clk_rate = ath79_get_sys_clk_rate("ahb");
	274	ddr_clk_rate = ath79_get_sys_clk_rate("ddr");
	275	ref_clk_rate = ath79_get_sys_clk_rate("ref");
	276
a26484bb	277	pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, Ref:%lu.%03luMHz\n",
59a8c10b GJ	278	cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000,
	279	ddr_clk_rate / 1000000, (ddr_clk_rate / 1000) % 1000,
	280	ahb_clk_rate / 1000000, (ahb_clk_rate / 1000) % 1000,
	281	ref_clk_rate / 1000000, (ref_clk_rate / 1000) % 1000);
d4a67d9d	282
23107802	283	mips_hpt_frequency = cpu_clk_rate / 2;
d4a67d9d GJ	284	}
	285
	286	static int __init ath79_setup(void)
	287	{
03c8c407 AB	288	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
	289	if (mips_machtype == ATH79_MACH_GENERIC_OF)
	290	return 0;
	291
6eae43c5	292	ath79_gpio_init();
d4a67d9d	293	ath79_register_uart();
858f763c	294	ath79_register_wdt();
0aabf1a4 GJ	295
	296	mips_machine_setup();
	297
d4a67d9d GJ	298	return 0;
	299	}
	300
	301	arch_initcall(ath79_setup);
0aabf1a4	302
03c8c407 AB	303	void __init device_tree_init(void)
	304	{
	305	unflatten_and_copy_device_tree();
	306	}
	307
0aabf1a4 GJ	308	MIPS_MACHINE(ATH79_MACH_GENERIC,
	309	"Generic",
	310	"Generic AR71XX/AR724X/AR913X based board",
fe8766dd	311	NULL);
55f1d598 AB	312
	313	MIPS_MACHINE(ATH79_MACH_GENERIC_OF,
	314	"DTB",
	315	"Generic AR71XX/AR724X/AR913X based board (DT)",
	316	NULL);