[deliverable/linux.git] / arch / mips / ath79 / setup.c

/*
 *  Atheros AR71XX/AR724X/AR913X specific setup
 *
 *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
 *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
 *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 *
 *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/bootmem.h>
#include <linux/err.h>
#include <linux/clk.h>

#include <asm/bootinfo.h>
#include <asm/time.h>		/* for mips_hpt_frequency */
#include <asm/reboot.h>		/* for _machine_{restart,halt} */
#include <asm/mips_machine.h>

#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"
#include "dev-common.h"
#include "machtypes.h"

#define ATH79_SYS_TYPE_LEN	64

#define AR71XX_BASE_FREQ	40000000
#define AR724X_BASE_FREQ	5000000
#define AR913X_BASE_FREQ	5000000

static char ath79_sys_type[ATH79_SYS_TYPE_LEN];

static void ath79_restart(char *command)
{
	ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
	for (;;)
		if (cpu_wait)
			cpu_wait();
}

static void ath79_halt(void)
{
	while (1)
		cpu_wait();
}

static void __init ath79_detect_sys_type(void)
{
	char *chip = "????";
	u32 id;
	u32 major;
	u32 minor;
	u32 rev = 0;

	id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
	major = id & REV_ID_MAJOR_MASK;

	switch (major) {
	case REV_ID_MAJOR_AR71XX:
		minor = id & AR71XX_REV_ID_MINOR_MASK;
		rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
		rev &= AR71XX_REV_ID_REVISION_MASK;
		switch (minor) {
		case AR71XX_REV_ID_MINOR_AR7130:
			ath79_soc = ATH79_SOC_AR7130;
			chip = "7130";
			break;

		case AR71XX_REV_ID_MINOR_AR7141:
			ath79_soc = ATH79_SOC_AR7141;
			chip = "7141";
			break;

		case AR71XX_REV_ID_MINOR_AR7161:
			ath79_soc = ATH79_SOC_AR7161;
			chip = "7161";
			break;
		}
		break;

	case REV_ID_MAJOR_AR7240:
		ath79_soc = ATH79_SOC_AR7240;
		chip = "7240";
		rev = id & AR724X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR7241:
		ath79_soc = ATH79_SOC_AR7241;
		chip = "7241";
		rev = id & AR724X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR7242:
		ath79_soc = ATH79_SOC_AR7242;
		chip = "7242";
		rev = id & AR724X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR913X:
		minor = id & AR913X_REV_ID_MINOR_MASK;
		rev = id >> AR913X_REV_ID_REVISION_SHIFT;
		rev &= AR913X_REV_ID_REVISION_MASK;
		switch (minor) {
		case AR913X_REV_ID_MINOR_AR9130:
			ath79_soc = ATH79_SOC_AR9130;
			chip = "9130";
			break;

		case AR913X_REV_ID_MINOR_AR9132:
			ath79_soc = ATH79_SOC_AR9132;
			chip = "9132";
			break;
		}
		break;

	case REV_ID_MAJOR_AR9330:
		ath79_soc = ATH79_SOC_AR9330;
		chip = "9330";
		rev = id & AR933X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR9331:
		ath79_soc = ATH79_SOC_AR9331;
		chip = "9331";
		rev = id & AR933X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR9341:
		ath79_soc = ATH79_SOC_AR9341;
		chip = "9341";
		rev = id & AR934X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR9342:
		ath79_soc = ATH79_SOC_AR9342;
		chip = "9342";
		rev = id & AR934X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR9344:
		ath79_soc = ATH79_SOC_AR9344;
		chip = "9344";
		rev = id & AR934X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_QCA9556:
		ath79_soc = ATH79_SOC_QCA9556;
		chip = "9556";
		rev = id & QCA955X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_QCA9558:
		ath79_soc = ATH79_SOC_QCA9558;
		chip = "9558";
		rev = id & QCA955X_REV_ID_REVISION_MASK;
		break;

	default:
		panic("ath79: unknown SoC, id:0x%08x", id);
	}

	ath79_soc_rev = rev;

	if (soc_is_qca955x())
		sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
			chip, rev);
	else
		sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
	pr_info("SoC: %s\n", ath79_sys_type);
}

const char *get_system_type(void)
{
	return ath79_sys_type;
}

unsigned int __cpuinit get_c0_compare_int(void)
{
	return CP0_LEGACY_COMPARE_IRQ;
}

void __init plat_mem_setup(void)
{
	set_io_port_base(KSEG1);

	ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
					   AR71XX_RESET_SIZE);
	ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
					 AR71XX_PLL_SIZE);
	ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
					 AR71XX_DDR_CTRL_SIZE);

	ath79_detect_sys_type();
	detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
	ath79_clocks_init();

	_machine_restart = ath79_restart;
	_machine_halt = ath79_halt;
	pm_power_off = ath79_halt;
}

void __init plat_time_init(void)
{
	struct clk *clk;

	clk = clk_get(NULL, "cpu");
	if (IS_ERR(clk))
		panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));

	mips_hpt_frequency = clk_get_rate(clk) / 2;
}

static int __init ath79_setup(void)
{
	ath79_gpio_init();
	ath79_register_uart();
	ath79_register_wdt();

	mips_machine_setup();

	return 0;
}

arch_initcall(ath79_setup);

static void __init ath79_generic_init(void)
{
	/* Nothing to do */
}

MIPS_MACHINE(ATH79_MACH_GENERIC,
	     "Generic",
	     "Generic AR71XX/AR724X/AR913X based board",
	     ath79_generic_init);
Commit	Line	Data
d4a67d9d GJ	1	/*
	2	* Atheros AR71XX/AR724X/AR913X specific setup
	3	*
d8411466	4	* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
d4a67d9d GJ	5	* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
	6	* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
	7	*
d8411466	8	* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
d4a67d9d GJ	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License version 2 as published
	12	* by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/kernel.h>
	16	#include <linux/init.h>
	17	#include <linux/bootmem.h>
	18	#include <linux/err.h>
	19	#include <linux/clk.h>
	20
	21	#include <asm/bootinfo.h>
	22	#include <asm/time.h> /* for mips_hpt_frequency */
	23	#include <asm/reboot.h> /* for _machine_{restart,halt} */
0aabf1a4	24	#include <asm/mips_machine.h>
d4a67d9d GJ	25
	26	#include <asm/mach-ath79/ath79.h>
	27	#include <asm/mach-ath79/ar71xx_regs.h>
	28	#include "common.h"
	29	#include "dev-common.h"
0aabf1a4	30	#include "machtypes.h"
d4a67d9d GJ	31
	32	#define ATH79_SYS_TYPE_LEN 64
	33
	34	#define AR71XX_BASE_FREQ 40000000
	35	#define AR724X_BASE_FREQ 5000000
	36	#define AR913X_BASE_FREQ 5000000
	37
	38	static char ath79_sys_type[ATH79_SYS_TYPE_LEN];
	39
	40	static void ath79_restart(char *command)
	41	{
	42	ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
	43	for (;;)
	44	if (cpu_wait)
	45	cpu_wait();
	46	}
	47
	48	static void ath79_halt(void)
	49	{
	50	while (1)
	51	cpu_wait();
	52	}
	53
d4a67d9d GJ	54	static void __init ath79_detect_sys_type(void)
	55	{
	56	char *chip = "????";
	57	u32 id;
	58	u32 major;
	59	u32 minor;
	60	u32 rev = 0;
	61
	62	id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
	63	major = id & REV_ID_MAJOR_MASK;
	64
	65	switch (major) {
	66	case REV_ID_MAJOR_AR71XX:
	67	minor = id & AR71XX_REV_ID_MINOR_MASK;
	68	rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
	69	rev &= AR71XX_REV_ID_REVISION_MASK;
	70	switch (minor) {
	71	case AR71XX_REV_ID_MINOR_AR7130:
	72	ath79_soc = ATH79_SOC_AR7130;
	73	chip = "7130";
	74	break;
	75
	76	case AR71XX_REV_ID_MINOR_AR7141:
	77	ath79_soc = ATH79_SOC_AR7141;
	78	chip = "7141";
	79	break;
	80
	81	case AR71XX_REV_ID_MINOR_AR7161:
	82	ath79_soc = ATH79_SOC_AR7161;
	83	chip = "7161";
	84	break;
	85	}
	86	break;
	87
	88	case REV_ID_MAJOR_AR7240:
	89	ath79_soc = ATH79_SOC_AR7240;
	90	chip = "7240";
8bed1288	91	rev = id & AR724X_REV_ID_REVISION_MASK;
d4a67d9d GJ	92	break;
	93
	94	case REV_ID_MAJOR_AR7241:
	95	ath79_soc = ATH79_SOC_AR7241;
	96	chip = "7241";
8bed1288	97	rev = id & AR724X_REV_ID_REVISION_MASK;
d4a67d9d GJ	98	break;
	99
	100	case REV_ID_MAJOR_AR7242:
	101	ath79_soc = ATH79_SOC_AR7242;
	102	chip = "7242";
8bed1288	103	rev = id & AR724X_REV_ID_REVISION_MASK;
d4a67d9d GJ	104	break;
	105
	106	case REV_ID_MAJOR_AR913X:
	107	minor = id & AR913X_REV_ID_MINOR_MASK;
	108	rev = id >> AR913X_REV_ID_REVISION_SHIFT;
	109	rev &= AR913X_REV_ID_REVISION_MASK;
	110	switch (minor) {
	111	case AR913X_REV_ID_MINOR_AR9130:
	112	ath79_soc = ATH79_SOC_AR9130;
	113	chip = "9130";
	114	break;
	115
	116	case AR913X_REV_ID_MINOR_AR9132:
	117	ath79_soc = ATH79_SOC_AR9132;
	118	chip = "9132";
	119	break;
	120	}
	121	break;
	122
80a7ed81 GJ	123	case REV_ID_MAJOR_AR9330:
	124	ath79_soc = ATH79_SOC_AR9330;
	125	chip = "9330";
	126	rev = id & AR933X_REV_ID_REVISION_MASK;
	127	break;
	128
	129	case REV_ID_MAJOR_AR9331:
	130	ath79_soc = ATH79_SOC_AR9331;
	131	chip = "9331";
	132	rev = id & AR933X_REV_ID_REVISION_MASK;
	133	break;
	134
d8411466 GJ	135	case REV_ID_MAJOR_AR9341:
	136	ath79_soc = ATH79_SOC_AR9341;
	137	chip = "9341";
	138	rev = id & AR934X_REV_ID_REVISION_MASK;
	139	break;
	140
	141	case REV_ID_MAJOR_AR9342:
	142	ath79_soc = ATH79_SOC_AR9342;
	143	chip = "9342";
	144	rev = id & AR934X_REV_ID_REVISION_MASK;
	145	break;
	146
	147	case REV_ID_MAJOR_AR9344:
	148	ath79_soc = ATH79_SOC_AR9344;
	149	chip = "9344";
	150	rev = id & AR934X_REV_ID_REVISION_MASK;
	151	break;
	152
2e6c91e3 GJ	153	case REV_ID_MAJOR_QCA9556:
	154	ath79_soc = ATH79_SOC_QCA9556;
	155	chip = "9556";
	156	rev = id & QCA955X_REV_ID_REVISION_MASK;
	157	break;
	158
	159	case REV_ID_MAJOR_QCA9558:
	160	ath79_soc = ATH79_SOC_QCA9558;
	161	chip = "9558";
	162	rev = id & QCA955X_REV_ID_REVISION_MASK;
	163	break;
	164
d4a67d9d	165	default:
ab75dc02	166	panic("ath79: unknown SoC, id:0x%08x", id);
d4a67d9d GJ	167	}
d4a67d9d GJ	168
be5f3623 GJ	169	ath79_soc_rev = rev;
be5f3623 GJ	170
2e6c91e3 GJ	171	if (soc_is_qca955x())
	172	sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
	173	chip, rev);
	174	else
	175	sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
d4a67d9d GJ	176	pr_info("SoC: %s\n", ath79_sys_type);
	177	}
	178
	179	const char *get_system_type(void)
	180	{
	181	return ath79_sys_type;
	182	}
	183
	184	unsigned int __cpuinit get_c0_compare_int(void)
	185	{
	186	return CP0_LEGACY_COMPARE_IRQ;
	187	}
	188
	189	void __init plat_mem_setup(void)
	190	{
	191	set_io_port_base(KSEG1);
	192
	193	ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
	194	AR71XX_RESET_SIZE);
	195	ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
	196	AR71XX_PLL_SIZE);
d4a67d9d GJ	197	ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
	198	AR71XX_DDR_CTRL_SIZE);
	199
	200	ath79_detect_sys_type();
9b75733b	201	detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
d4a67d9d GJ	202	ath79_clocks_init();
	203
	204	_machine_restart = ath79_restart;
	205	_machine_halt = ath79_halt;
	206	pm_power_off = ath79_halt;
	207	}
	208
	209	void __init plat_time_init(void)
	210	{
	211	struct clk *clk;
	212
	213	clk = clk_get(NULL, "cpu");
	214	if (IS_ERR(clk))
	215	panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
	216
	217	mips_hpt_frequency = clk_get_rate(clk) / 2;
	218	}
	219
	220	static int __init ath79_setup(void)
	221	{
6eae43c5	222	ath79_gpio_init();
d4a67d9d	223	ath79_register_uart();
858f763c	224	ath79_register_wdt();
0aabf1a4 GJ	225
	226	mips_machine_setup();
	227
d4a67d9d GJ	228	return 0;
	229	}
	230
	231	arch_initcall(ath79_setup);
0aabf1a4 GJ	232
	233	static void __init ath79_generic_init(void)
	234	{
	235	/* Nothing to do */
	236	}
	237
	238	MIPS_MACHINE(ATH79_MACH_GENERIC,
	239	"Generic",
	240	"Generic AR71XX/AR724X/AR913X based board",
	241	ath79_generic_init);