Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Copyright 2000 MontaVista Software Inc. | |
3 | * Author: MontaVista Software, Inc. | |
4 | * ppopov@mvista.com or source@mvista.com | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | * | |
11 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
12 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
13 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
14 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
15 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
16 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
17 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
18 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
19 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
20 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License along | |
23 | * with this program; if not, write to the Free Software Foundation, Inc., | |
24 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | */ | |
ce28f94c | 26 | |
1da177e4 | 27 | #include <linux/init.h> |
1da177e4 LT |
28 | #include <linux/delay.h> |
29 | ||
1da177e4 LT |
30 | #include <asm/mach-au1x00/au1000.h> |
31 | #include <asm/mach-pb1x00/pb1000.h> | |
32 | ||
49a89efb | 33 | void board_reset(void) |
1da177e4 LT |
34 | { |
35 | } | |
36 | ||
37 | void __init board_setup(void) | |
38 | { | |
39 | u32 pin_func, static_cfg0; | |
40 | u32 sys_freqctrl, sys_clksrc; | |
41 | u32 prid = read_c0_prid(); | |
42 | ||
43 | // set AUX clock to 12MHz * 8 = 96 MHz | |
44 | au_writel(8, SYS_AUXPLL); | |
45 | au_writel(0, SYS_PINSTATERD); | |
46 | udelay(100); | |
47 | ||
f708631a | 48 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) |
1da177e4 LT |
49 | /* zero and disable FREQ2 */ |
50 | sys_freqctrl = au_readl(SYS_FREQCTRL0); | |
51 | sys_freqctrl &= ~0xFFF00000; | |
52 | au_writel(sys_freqctrl, SYS_FREQCTRL0); | |
53 | ||
54 | /* zero and disable USBH/USBD clocks */ | |
55 | sys_clksrc = au_readl(SYS_CLKSRC); | |
56 | sys_clksrc &= ~0x00007FE0; | |
57 | au_writel(sys_clksrc, SYS_CLKSRC); | |
58 | ||
59 | sys_freqctrl = au_readl(SYS_FREQCTRL0); | |
60 | sys_freqctrl &= ~0xFFF00000; | |
61 | ||
62 | sys_clksrc = au_readl(SYS_CLKSRC); | |
63 | sys_clksrc &= ~0x00007FE0; | |
64 | ||
65 | switch (prid & 0x000000FF) | |
66 | { | |
67 | case 0x00: /* DA */ | |
68 | case 0x01: /* HA */ | |
69 | case 0x02: /* HB */ | |
70 | /* CPU core freq to 48MHz to slow it way down... */ | |
71 | au_writel(4, SYS_CPUPLL); | |
72 | ||
73 | /* | |
74 | * Setup 48MHz FREQ2 from CPUPLL for USB Host | |
75 | */ | |
76 | /* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */ | |
77 | sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20)); | |
78 | au_writel(sys_freqctrl, SYS_FREQCTRL0); | |
79 | ||
80 | /* CPU core freq to 384MHz */ | |
81 | au_writel(0x20, SYS_CPUPLL); | |
82 | ||
83 | printk("Au1000: 48MHz OHCI workaround enabled\n"); | |
84 | break; | |
85 | ||
86 | default: /* HC and newer */ | |
87 | // FREQ2 = aux/2 = 48 MHz | |
88 | sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20)); | |
89 | au_writel(sys_freqctrl, SYS_FREQCTRL0); | |
90 | break; | |
91 | } | |
92 | ||
93 | /* | |
94 | * Route 48MHz FREQ2 into USB Host and/or Device | |
95 | */ | |
f708631a | 96 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) |
1da177e4 | 97 | sys_clksrc |= ((4<<12) | (0<<11) | (0<<10)); |
1da177e4 LT |
98 | #endif |
99 | au_writel(sys_clksrc, SYS_CLKSRC); | |
100 | ||
101 | // configure pins GPIO[14:9] as GPIO | |
102 | pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080); | |
103 | ||
1da177e4 LT |
104 | // 2nd USB port is USB host |
105 | pin_func |= 0x8000; | |
5536b235 | 106 | |
1da177e4 LT |
107 | au_writel(pin_func, SYS_PINFUNC); |
108 | au_writel(0x2800, SYS_TRIOUTCLR); | |
109 | au_writel(0x0030, SYS_OUTPUTCLR); | |
f708631a | 110 | #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ |
1da177e4 LT |
111 | |
112 | // make gpio 15 an input (for interrupt line) | |
113 | pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x100); | |
114 | // we don't need I2S, so make it available for GPIO[31:29] | |
115 | pin_func |= (1<<5); | |
116 | au_writel(pin_func, SYS_PINFUNC); | |
117 | ||
118 | au_writel(0x8000, SYS_TRIOUTCLR); | |
119 | ||
120 | static_cfg0 = au_readl(MEM_STCFG0) & (u32)(~0xc00); | |
121 | au_writel(static_cfg0, MEM_STCFG0); | |
122 | ||
123 | // configure RCE2* for LCD | |
124 | au_writel(0x00000004, MEM_STCFG2); | |
125 | ||
126 | // MEM_STTIME2 | |
127 | au_writel(0x09000000, MEM_STTIME2); | |
128 | ||
129 | // Set 32-bit base address decoding for RCE2* | |
130 | au_writel(0x10003ff0, MEM_STADDR2); | |
131 | ||
132 | // PCI CPLD setup | |
133 | // expand CE0 to cover PCI | |
134 | au_writel(0x11803e40, MEM_STADDR1); | |
135 | ||
136 | // burst visibility on | |
137 | au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0); | |
138 | ||
139 | au_writel(0x83, MEM_STCFG1); // ewait enabled, flash timing | |
140 | au_writel(0x33030a10, MEM_STTIME1); // slower timing for FPGA | |
141 | ||
142 | /* setup the static bus controller */ | |
143 | au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */ | |
144 | au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */ | |
145 | au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */ | |
146 | ||
147 | #ifdef CONFIG_PCI | |
148 | au_writel(0, PCI_BRIDGE_CONFIG); // set extend byte to 0 | |
149 | au_writel(0, SDRAM_MBAR); // set mbar to 0 | |
150 | au_writel(0x2, SDRAM_CMD); // enable memory accesses | |
151 | au_sync_delay(1); | |
152 | #endif | |
153 | ||
154 | /* Enable Au1000 BCLK switching - note: sed1356 must not use | |
155 | * its BCLK (Au1000 LCLK) for any timings */ | |
156 | switch (prid & 0x000000FF) | |
157 | { | |
158 | case 0x00: /* DA */ | |
159 | case 0x01: /* HA */ | |
160 | case 0x02: /* HB */ | |
161 | break; | |
162 | default: /* HC and newer */ | |
42a3b4f2 | 163 | /* Enable sys bus clock divider when IDLE state or no bus |
1da177e4 LT |
164 | activity. */ |
165 | au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL); | |
166 | break; | |
167 | } | |
168 | } |