[deliverable/linux.git] / arch / mips / bcm63xx / irq.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
 * Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr>
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/irq.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_regs.h>
#include <bcm63xx_io.h>
#include <bcm63xx_irq.h>

static u32 irq_stat_addr[2];
static u32 irq_mask_addr[2];
static void (*dispatch_internal)(void);
static int is_ext_irq_cascaded;
static unsigned int ext_irq_count;
static unsigned int ext_irq_start, ext_irq_end;
static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;
static void (*internal_irq_mask)(unsigned int irq);
static void (*internal_irq_unmask)(unsigned int irq);


static inline u32 get_ext_irq_perf_reg(int irq)
{
	if (irq < 4)
		return ext_irq_cfg_reg1;
	return ext_irq_cfg_reg2;
}

static inline void handle_internal(int intbit)
{
	if (is_ext_irq_cascaded &&
	    intbit >= ext_irq_start && intbit <= ext_irq_end)
		do_IRQ(intbit - ext_irq_start + IRQ_EXTERNAL_BASE);
	else
		do_IRQ(intbit + IRQ_INTERNAL_BASE);
}

/*
 * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
 * prioritize any interrupt relatively to another. the static counter
 * will resume the loop where it ended the last time we left this
 * function.
 */

#define BUILD_IPIC_INTERNAL(width)					\
void __dispatch_internal_##width(void)					\
{									\
	u32 pending[width / 32];					\
	unsigned int src, tgt;						\
	bool irqs_pending = false;					\
	static unsigned int i;						\
									\
	/* read registers in reverse order */				\
	for (src = 0, tgt = (width / 32); src < (width / 32); src++) {	\
		u32 val;						\
									\
		val = bcm_readl(irq_stat_addr[0] + src * sizeof(u32));	\
		val &= bcm_readl(irq_mask_addr[0] + src * sizeof(u32));	\
		pending[--tgt] = val;					\
									\
		if (val)						\
			irqs_pending = true;				\
	}								\
									\
	if (!irqs_pending)						\
		return;							\
									\
	while (1) {							\
		unsigned int to_call = i;				\
									\
		i = (i + 1) & (width - 1);				\
		if (pending[to_call / 32] & (1 << (to_call & 0x1f))) {	\
			handle_internal(to_call);			\
			break;						\
		}							\
	}								\
}									\
									\
static void __internal_irq_mask_##width(unsigned int irq)		\
{									\
	u32 val;							\
	unsigned reg = (irq / 32) ^ (width/32 - 1);			\
	unsigned bit = irq & 0x1f;					\
									\
	val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32));		\
	val &= ~(1 << bit);						\
	bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32));		\
}									\
									\
static void __internal_irq_unmask_##width(unsigned int irq)		\
{									\
	u32 val;							\
	unsigned reg = (irq / 32) ^ (width/32 - 1);			\
	unsigned bit = irq & 0x1f;					\
									\
	val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32));		\
	val |= (1 << bit);						\
	bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32));		\
}

BUILD_IPIC_INTERNAL(32);
BUILD_IPIC_INTERNAL(64);

asmlinkage void plat_irq_dispatch(void)
{
	u32 cause;

	do {
		cause = read_c0_cause() & read_c0_status() & ST0_IM;

		if (!cause)
			break;

		if (cause & CAUSEF_IP7)
			do_IRQ(7);
		if (cause & CAUSEF_IP0)
			do_IRQ(0);
		if (cause & CAUSEF_IP1)
			do_IRQ(1);
		if (cause & CAUSEF_IP2)
			dispatch_internal();
		if (!is_ext_irq_cascaded) {
			if (cause & CAUSEF_IP3)
				do_IRQ(IRQ_EXT_0);
			if (cause & CAUSEF_IP4)
				do_IRQ(IRQ_EXT_1);
			if (cause & CAUSEF_IP5)
				do_IRQ(IRQ_EXT_2);
			if (cause & CAUSEF_IP6)
				do_IRQ(IRQ_EXT_3);
		}
	} while (1);
}

/*
 * internal IRQs operations: only mask/unmask on PERF irq mask
 * register.
 */
static void bcm63xx_internal_irq_mask(struct irq_data *d)
{
	internal_irq_mask(d->irq - IRQ_INTERNAL_BASE);
}

static void bcm63xx_internal_irq_unmask(struct irq_data *d)
{
	internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE);
}

/*
 * external IRQs operations: mask/unmask and clear on PERF external
 * irq control register.
 */
static void bcm63xx_external_irq_mask(struct irq_data *d)
{
	unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
	u32 reg, regaddr;

	regaddr = get_ext_irq_perf_reg(irq);
	reg = bcm_perf_readl(regaddr);

	if (BCMCPU_IS_6348())
		reg &= ~EXTIRQ_CFG_MASK_6348(irq % 4);
	else
		reg &= ~EXTIRQ_CFG_MASK(irq % 4);

	bcm_perf_writel(reg, regaddr);
	if (is_ext_irq_cascaded)
		internal_irq_mask(irq + ext_irq_start);
}

static void bcm63xx_external_irq_unmask(struct irq_data *d)
{
	unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
	u32 reg, regaddr;

	regaddr = get_ext_irq_perf_reg(irq);
	reg = bcm_perf_readl(regaddr);

	if (BCMCPU_IS_6348())
		reg |= EXTIRQ_CFG_MASK_6348(irq % 4);
	else
		reg |= EXTIRQ_CFG_MASK(irq % 4);

	bcm_perf_writel(reg, regaddr);

	if (is_ext_irq_cascaded)
		internal_irq_unmask(irq + ext_irq_start);
}

static void bcm63xx_external_irq_clear(struct irq_data *d)
{
	unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
	u32 reg, regaddr;

	regaddr = get_ext_irq_perf_reg(irq);
	reg = bcm_perf_readl(regaddr);

	if (BCMCPU_IS_6348())
		reg |= EXTIRQ_CFG_CLEAR_6348(irq % 4);
	else
		reg |= EXTIRQ_CFG_CLEAR(irq % 4);

	bcm_perf_writel(reg, regaddr);
}

static int bcm63xx_external_irq_set_type(struct irq_data *d,
					 unsigned int flow_type)
{
	unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
	u32 reg, regaddr;
	int levelsense, sense, bothedge;

	flow_type &= IRQ_TYPE_SENSE_MASK;

	if (flow_type == IRQ_TYPE_NONE)
		flow_type = IRQ_TYPE_LEVEL_LOW;

	levelsense = sense = bothedge = 0;
	switch (flow_type) {
	case IRQ_TYPE_EDGE_BOTH:
		bothedge = 1;
		break;

	case IRQ_TYPE_EDGE_RISING:
		sense = 1;
		break;

	case IRQ_TYPE_EDGE_FALLING:
		break;

	case IRQ_TYPE_LEVEL_HIGH:
		levelsense = 1;
		sense = 1;
		break;

	case IRQ_TYPE_LEVEL_LOW:
		levelsense = 1;
		break;

	default:
		printk(KERN_ERR "bogus flow type combination given !\n");
		return -EINVAL;
	}

	regaddr = get_ext_irq_perf_reg(irq);
	reg = bcm_perf_readl(regaddr);
	irq %= 4;

	switch (bcm63xx_get_cpu_id()) {
	case BCM6348_CPU_ID:
		if (levelsense)
			reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq);
		else
			reg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq);
		if (sense)
			reg |= EXTIRQ_CFG_SENSE_6348(irq);
		else
			reg &= ~EXTIRQ_CFG_SENSE_6348(irq);
		if (bothedge)
			reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq);
		else
			reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
		break;

	case BCM3368_CPU_ID:
	case BCM6328_CPU_ID:
	case BCM6338_CPU_ID:
	case BCM6345_CPU_ID:
	case BCM6358_CPU_ID:
	case BCM6362_CPU_ID:
	case BCM6368_CPU_ID:
		if (levelsense)
			reg |= EXTIRQ_CFG_LEVELSENSE(irq);
		else
			reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
		if (sense)
			reg |= EXTIRQ_CFG_SENSE(irq);
		else
			reg &= ~EXTIRQ_CFG_SENSE(irq);
		if (bothedge)
			reg |= EXTIRQ_CFG_BOTHEDGE(irq);
		else
			reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
		break;
	default:
		BUG();
	}

	bcm_perf_writel(reg, regaddr);

	irqd_set_trigger_type(d, flow_type);
	if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
		__irq_set_handler_locked(d->irq, handle_level_irq);
	else
		__irq_set_handler_locked(d->irq, handle_edge_irq);

	return IRQ_SET_MASK_OK_NOCOPY;
}

static struct irq_chip bcm63xx_internal_irq_chip = {
	.name		= "bcm63xx_ipic",
	.irq_mask	= bcm63xx_internal_irq_mask,
	.irq_unmask	= bcm63xx_internal_irq_unmask,
};

static struct irq_chip bcm63xx_external_irq_chip = {
	.name		= "bcm63xx_epic",
	.irq_ack	= bcm63xx_external_irq_clear,

	.irq_mask	= bcm63xx_external_irq_mask,
	.irq_unmask	= bcm63xx_external_irq_unmask,

	.irq_set_type	= bcm63xx_external_irq_set_type,
};

static struct irqaction cpu_ip2_cascade_action = {
	.handler	= no_action,
	.name		= "cascade_ip2",
	.flags		= IRQF_NO_THREAD,
};

static struct irqaction cpu_ext_cascade_action = {
	.handler	= no_action,
	.name		= "cascade_extirq",
	.flags		= IRQF_NO_THREAD,
};

static void bcm63xx_init_irq(void)
{
	int irq_bits;

	irq_stat_addr[0] = bcm63xx_regset_address(RSET_PERF);
	irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF);
	irq_stat_addr[1] = bcm63xx_regset_address(RSET_PERF);
	irq_mask_addr[1] = bcm63xx_regset_address(RSET_PERF);

	switch (bcm63xx_get_cpu_id()) {
	case BCM3368_CPU_ID:
		irq_stat_addr[0] += PERF_IRQSTAT_3368_REG;
		irq_mask_addr[0] += PERF_IRQMASK_3368_REG;
		irq_stat_addr[1] = 0;
		irq_stat_addr[1] = 0;
		irq_bits = 32;
		ext_irq_count = 4;
		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
		break;
	case BCM6328_CPU_ID:
		irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0);
		irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0);
		irq_stat_addr[1] += PERF_IRQSTAT_6328_REG(1);
		irq_stat_addr[1] += PERF_IRQMASK_6328_REG(1);
		irq_bits = 64;
		ext_irq_count = 4;
		is_ext_irq_cascaded = 1;
		ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
		ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
		break;
	case BCM6338_CPU_ID:
		irq_stat_addr[0] += PERF_IRQSTAT_6338_REG;
		irq_mask_addr[0] += PERF_IRQMASK_6338_REG;
		irq_stat_addr[1] = 0;
		irq_mask_addr[1] = 0;
		irq_bits = 32;
		ext_irq_count = 4;
		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
		break;
	case BCM6345_CPU_ID:
		irq_stat_addr[0] += PERF_IRQSTAT_6345_REG;
		irq_mask_addr[0] += PERF_IRQMASK_6345_REG;
		irq_stat_addr[1] = 0;
		irq_mask_addr[1] = 0;
		irq_bits = 32;
		ext_irq_count = 4;
		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
		break;
	case BCM6348_CPU_ID:
		irq_stat_addr[0] += PERF_IRQSTAT_6348_REG;
		irq_mask_addr[0] += PERF_IRQMASK_6348_REG;
		irq_stat_addr[1] = 0;
		irq_mask_addr[1] = 0;
		irq_bits = 32;
		ext_irq_count = 4;
		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
		break;
	case BCM6358_CPU_ID:
		irq_stat_addr[0] += PERF_IRQSTAT_6358_REG(0);
		irq_mask_addr[0] += PERF_IRQMASK_6358_REG(0);
		irq_stat_addr[1] += PERF_IRQSTAT_6358_REG(1);
		irq_mask_addr[1] += PERF_IRQMASK_6358_REG(1);
		irq_bits = 32;
		ext_irq_count = 4;
		is_ext_irq_cascaded = 1;
		ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
		ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
		break;
	case BCM6362_CPU_ID:
		irq_stat_addr[0] += PERF_IRQSTAT_6362_REG(0);
		irq_mask_addr[0] += PERF_IRQMASK_6362_REG(0);
		irq_stat_addr[1] += PERF_IRQSTAT_6362_REG(1);
		irq_mask_addr[1] += PERF_IRQMASK_6362_REG(1);
		irq_bits = 64;
		ext_irq_count = 4;
		is_ext_irq_cascaded = 1;
		ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
		ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
		break;
	case BCM6368_CPU_ID:
		irq_stat_addr[0] += PERF_IRQSTAT_6368_REG(0);
		irq_mask_addr[0] += PERF_IRQMASK_6368_REG(0);
		irq_stat_addr[1] += PERF_IRQSTAT_6368_REG(1);
		irq_mask_addr[1] += PERF_IRQMASK_6368_REG(1);
		irq_bits = 64;
		ext_irq_count = 6;
		is_ext_irq_cascaded = 1;
		ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
		ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
		ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
		break;
	default:
		BUG();
	}

	if (irq_bits == 32) {
		dispatch_internal = __dispatch_internal_32;
		internal_irq_mask = __internal_irq_mask_32;
		internal_irq_unmask = __internal_irq_unmask_32;
	} else {
		dispatch_internal = __dispatch_internal_64;
		internal_irq_mask = __internal_irq_mask_64;
		internal_irq_unmask = __internal_irq_unmask_64;
	}
}

void __init arch_init_irq(void)
{
	int i;

	bcm63xx_init_irq();
	mips_cpu_irq_init();
	for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
		irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
					 handle_level_irq);

	for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + ext_irq_count; ++i)
		irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,
					 handle_edge_irq);

	if (!is_ext_irq_cascaded) {
		for (i = 3; i < 3 + ext_irq_count; ++i)
			setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action);
	}

	setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
}
Commit	Line	Data
e7300d04 MB	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
	7	* Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr>
	8	*/
	9
	10	#include <linux/kernel.h>
	11	#include <linux/init.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/module.h>
ca4d3e67	14	#include <linux/irq.h>
e7300d04 MB	15	#include <asm/irq_cpu.h>
	16	#include <asm/mipsregs.h>
	17	#include <bcm63xx_cpu.h>
	18	#include <bcm63xx_regs.h>
	19	#include <bcm63xx_io.h>
	20	#include <bcm63xx_irq.h>
	21
cc81d7f3 JG	22	static u32 irq_stat_addr[2];
cc81d7f3 JG	23	static u32 irq_mask_addr[2];
f61cced9	24	static void (*dispatch_internal)(void);
37c42a74	25	static int is_ext_irq_cascaded;
6224892c	26	static unsigned int ext_irq_count;
37c42a74	27	static unsigned int ext_irq_start, ext_irq_end;
6224892c	28	static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;
71a43927 MB	29	static void (*internal_irq_mask)(unsigned int irq);
71a43927 MB	30	static void (*internal_irq_unmask)(unsigned int irq);
f61cced9	31
f61cced9	32
6224892c MB	33	static inline u32 get_ext_irq_perf_reg(int irq)
	34	{
	35	if (irq < 4)
	36	return ext_irq_cfg_reg1;
	37	return ext_irq_cfg_reg2;
	38	}
	39
f61cced9 MB	40	static inline void handle_internal(int intbit)
f61cced9 MB	41	{
37c42a74 MB	42	if (is_ext_irq_cascaded &&
	43	intbit >= ext_irq_start && intbit <= ext_irq_end)
	44	do_IRQ(intbit - ext_irq_start + IRQ_EXTERNAL_BASE);
	45	else
	46	do_IRQ(intbit + IRQ_INTERNAL_BASE);
f61cced9 MB	47	}
f61cced9 MB	48
e7300d04 MB	49	/*
	50	* dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
	51	* prioritize any interrupt relatively to another. the static counter
	52	* will resume the loop where it ended the last time we left this
	53	* function.
	54	*/
e7300d04	55
86ee4333 JG	56	#define BUILD_IPIC_INTERNAL(width) \
	57	void __dispatch_internal_##width(void) \
	58	{ \
	59	u32 pending[width / 32]; \
	60	unsigned int src, tgt; \
	61	bool irqs_pending = false; \
	62	static unsigned int i; \
	63	\
	64	/* read registers in reverse order */ \
	65	for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
	66	u32 val; \
	67	\
cc81d7f3 JG	68	val = bcm_readl(irq_stat_addr[0] + src * sizeof(u32)); \
cc81d7f3 JG	69	val &= bcm_readl(irq_mask_addr[0] + src * sizeof(u32)); \
86ee4333 JG	70	pending[--tgt] = val; \
	71	\
	72	if (val) \
	73	irqs_pending = true; \
	74	} \
	75	\
	76	if (!irqs_pending) \
	77	return; \
	78	\
	79	while (1) { \
	80	unsigned int to_call = i; \
	81	\
	82	i = (i + 1) & (width - 1); \
	83	if (pending[to_call / 32] & (1 << (to_call & 0x1f))) { \
	84	handle_internal(to_call); \
	85	break; \
	86	} \
	87	} \
	88	} \
	89	\
	90	static void __internal_irq_mask_##width(unsigned int irq) \
	91	{ \
	92	u32 val; \
	93	unsigned reg = (irq / 32) ^ (width/32 - 1); \
	94	unsigned bit = irq & 0x1f; \
	95	\
cc81d7f3	96	val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \
86ee4333	97	val &= ~(1 << bit); \
cc81d7f3	98	bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \
86ee4333 JG	99	} \
	100	\
	101	static void __internal_irq_unmask_##width(unsigned int irq) \
	102	{ \
	103	u32 val; \
	104	unsigned reg = (irq / 32) ^ (width/32 - 1); \
	105	unsigned bit = irq & 0x1f; \
	106	\
cc81d7f3	107	val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \
86ee4333	108	val \|= (1 << bit); \
cc81d7f3	109	bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \
e7300d04 MB	110	}
e7300d04 MB	111
86ee4333 JG	112	BUILD_IPIC_INTERNAL(32);
86ee4333 JG	113	BUILD_IPIC_INTERNAL(64);
71a43927	114
e7300d04 MB	115	asmlinkage void plat_irq_dispatch(void)
	116	{
	117	u32 cause;
	118
	119	do {
	120	cause = read_c0_cause() & read_c0_status() & ST0_IM;
	121
	122	if (!cause)
	123	break;
	124
	125	if (cause & CAUSEF_IP7)
	126	do_IRQ(7);
937ad104 KC	127	if (cause & CAUSEF_IP0)
	128	do_IRQ(0);
	129	if (cause & CAUSEF_IP1)
	130	do_IRQ(1);
e7300d04	131	if (cause & CAUSEF_IP2)
f61cced9	132	dispatch_internal();
37c42a74 MB	133	if (!is_ext_irq_cascaded) {
	134	if (cause & CAUSEF_IP3)
	135	do_IRQ(IRQ_EXT_0);
	136	if (cause & CAUSEF_IP4)
	137	do_IRQ(IRQ_EXT_1);
	138	if (cause & CAUSEF_IP5)
	139	do_IRQ(IRQ_EXT_2);
	140	if (cause & CAUSEF_IP6)
	141	do_IRQ(IRQ_EXT_3);
	142	}
e7300d04 MB	143	} while (1);
	144	}
	145
	146	/*
	147	* internal IRQs operations: only mask/unmask on PERF irq mask
	148	* register.
	149	*/
37c42a74 MB	150	static void bcm63xx_internal_irq_mask(struct irq_data *d)
	151	{
	152	internal_irq_mask(d->irq - IRQ_INTERNAL_BASE);
	153	}
	154
	155	static void bcm63xx_internal_irq_unmask(struct irq_data *d)
	156	{
	157	internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE);
	158	}
	159
e7300d04 MB	160	/*
	161	* external IRQs operations: mask/unmask and clear on PERF external
	162	* irq control register.
	163	*/
93f29361	164	static void bcm63xx_external_irq_mask(struct irq_data *d)
e7300d04	165	{
37c42a74	166	unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
6224892c	167	u32 reg, regaddr;
e7300d04	168
6224892c MB	169	regaddr = get_ext_irq_perf_reg(irq);
	170	reg = bcm_perf_readl(regaddr);
	171
	172	if (BCMCPU_IS_6348())
	173	reg &= ~EXTIRQ_CFG_MASK_6348(irq % 4);
	174	else
	175	reg &= ~EXTIRQ_CFG_MASK(irq % 4);
	176
	177	bcm_perf_writel(reg, regaddr);
37c42a74 MB	178	if (is_ext_irq_cascaded)
37c42a74 MB	179	internal_irq_mask(irq + ext_irq_start);
e7300d04 MB	180	}
e7300d04 MB	181
93f29361	182	static void bcm63xx_external_irq_unmask(struct irq_data *d)
e7300d04	183	{
37c42a74	184	unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
6224892c MB	185	u32 reg, regaddr;
	186
	187	regaddr = get_ext_irq_perf_reg(irq);
	188	reg = bcm_perf_readl(regaddr);
	189
	190	if (BCMCPU_IS_6348())
	191	reg \|= EXTIRQ_CFG_MASK_6348(irq % 4);
	192	else
	193	reg \|= EXTIRQ_CFG_MASK(irq % 4);
	194
	195	bcm_perf_writel(reg, regaddr);
e7300d04	196
37c42a74 MB	197	if (is_ext_irq_cascaded)
37c42a74 MB	198	internal_irq_unmask(irq + ext_irq_start);
e7300d04 MB	199	}
e7300d04 MB	200
93f29361	201	static void bcm63xx_external_irq_clear(struct irq_data *d)
e7300d04	202	{
37c42a74	203	unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
6224892c MB	204	u32 reg, regaddr;
	205
	206	regaddr = get_ext_irq_perf_reg(irq);
	207	reg = bcm_perf_readl(regaddr);
e7300d04	208
6224892c MB	209	if (BCMCPU_IS_6348())
	210	reg \|= EXTIRQ_CFG_CLEAR_6348(irq % 4);
	211	else
	212	reg \|= EXTIRQ_CFG_CLEAR(irq % 4);
	213
	214	bcm_perf_writel(reg, regaddr);
e7300d04 MB	215	}
e7300d04 MB	216
93f29361	217	static int bcm63xx_external_irq_set_type(struct irq_data *d,
e7300d04 MB	218	unsigned int flow_type)
e7300d04 MB	219	{
37c42a74	220	unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
6224892c MB	221	u32 reg, regaddr;
6224892c MB	222	int levelsense, sense, bothedge;
e7300d04 MB	223
	224	flow_type &= IRQ_TYPE_SENSE_MASK;
	225
	226	if (flow_type == IRQ_TYPE_NONE)
	227	flow_type = IRQ_TYPE_LEVEL_LOW;
	228
6224892c	229	levelsense = sense = bothedge = 0;
e7300d04 MB	230	switch (flow_type) {
e7300d04 MB	231	case IRQ_TYPE_EDGE_BOTH:
6224892c	232	bothedge = 1;
e7300d04 MB	233	break;
	234
	235	case IRQ_TYPE_EDGE_RISING:
6224892c	236	sense = 1;
e7300d04 MB	237	break;
	238
	239	case IRQ_TYPE_EDGE_FALLING:
e7300d04 MB	240	break;
	241
	242	case IRQ_TYPE_LEVEL_HIGH:
6224892c MB	243	levelsense = 1;
6224892c MB	244	sense = 1;
e7300d04 MB	245	break;
	246
	247	case IRQ_TYPE_LEVEL_LOW:
6224892c	248	levelsense = 1;
e7300d04 MB	249	break;
	250
	251	default:
	252	printk(KERN_ERR "bogus flow type combination given !\n");
	253	return -EINVAL;
	254	}
6224892c MB	255
	256	regaddr = get_ext_irq_perf_reg(irq);
	257	reg = bcm_perf_readl(regaddr);
	258	irq %= 4;
	259
58e380af MB	260	switch (bcm63xx_get_cpu_id()) {
58e380af MB	261	case BCM6348_CPU_ID:
6224892c MB	262	if (levelsense)
	263	reg \|= EXTIRQ_CFG_LEVELSENSE_6348(irq);
	264	else
	265	reg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq);
	266	if (sense)
	267	reg \|= EXTIRQ_CFG_SENSE_6348(irq);
	268	else
	269	reg &= ~EXTIRQ_CFG_SENSE_6348(irq);
	270	if (bothedge)
	271	reg \|= EXTIRQ_CFG_BOTHEDGE_6348(irq);
	272	else
	273	reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
58e380af	274	break;
6224892c	275
7b933421	276	case BCM3368_CPU_ID:
58e380af MB	277	case BCM6328_CPU_ID:
	278	case BCM6338_CPU_ID:
	279	case BCM6345_CPU_ID:
	280	case BCM6358_CPU_ID:
2c8aaf71	281	case BCM6362_CPU_ID:
58e380af	282	case BCM6368_CPU_ID:
6224892c MB	283	if (levelsense)
	284	reg \|= EXTIRQ_CFG_LEVELSENSE(irq);
	285	else
	286	reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
	287	if (sense)
	288	reg \|= EXTIRQ_CFG_SENSE(irq);
	289	else
	290	reg &= ~EXTIRQ_CFG_SENSE(irq);
	291	if (bothedge)
	292	reg \|= EXTIRQ_CFG_BOTHEDGE(irq);
	293	else
	294	reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
58e380af MB	295	break;
	296	default:
	297	BUG();
6224892c MB	298	}
	299
	300	bcm_perf_writel(reg, regaddr);
e7300d04	301
93f29361 TG	302	irqd_set_trigger_type(d, flow_type);
	303	if (flow_type & (IRQ_TYPE_LEVEL_LOW \| IRQ_TYPE_LEVEL_HIGH))
	304	__irq_set_handler_locked(d->irq, handle_level_irq);
	305	else
	306	__irq_set_handler_locked(d->irq, handle_edge_irq);
e7300d04	307
93f29361	308	return IRQ_SET_MASK_OK_NOCOPY;
e7300d04 MB	309	}
	310
	311	static struct irq_chip bcm63xx_internal_irq_chip = {
	312	.name = "bcm63xx_ipic",
93f29361 TG	313	.irq_mask = bcm63xx_internal_irq_mask,
93f29361 TG	314	.irq_unmask = bcm63xx_internal_irq_unmask,
e7300d04 MB	315	};
	316
	317	static struct irq_chip bcm63xx_external_irq_chip = {
	318	.name = "bcm63xx_epic",
93f29361	319	.irq_ack = bcm63xx_external_irq_clear,
e7300d04	320
93f29361 TG	321	.irq_mask = bcm63xx_external_irq_mask,
93f29361 TG	322	.irq_unmask = bcm63xx_external_irq_unmask,
e7300d04	323
93f29361	324	.irq_set_type = bcm63xx_external_irq_set_type,
e7300d04 MB	325	};
	326
	327	static struct irqaction cpu_ip2_cascade_action = {
	328	.handler = no_action,
	329	.name = "cascade_ip2",
5a4a4ad8	330	.flags = IRQF_NO_THREAD,
e7300d04 MB	331	};
e7300d04 MB	332
37c42a74 MB	333	static struct irqaction cpu_ext_cascade_action = {
	334	.handler = no_action,
	335	.name = "cascade_extirq",
	336	.flags = IRQF_NO_THREAD,
	337	};
	338
a6dfde81 JG	339	static void bcm63xx_init_irq(void)
	340	{
	341	int irq_bits;
	342
cc81d7f3 JG	343	irq_stat_addr[0] = bcm63xx_regset_address(RSET_PERF);
cc81d7f3 JG	344	irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF);
3534b5ce JG	345	irq_stat_addr[1] = bcm63xx_regset_address(RSET_PERF);
3534b5ce JG	346	irq_mask_addr[1] = bcm63xx_regset_address(RSET_PERF);
a6dfde81 JG	347
	348	switch (bcm63xx_get_cpu_id()) {
	349	case BCM3368_CPU_ID:
cc81d7f3 JG	350	irq_stat_addr[0] += PERF_IRQSTAT_3368_REG;
cc81d7f3 JG	351	irq_mask_addr[0] += PERF_IRQMASK_3368_REG;
3534b5ce JG	352	irq_stat_addr[1] = 0;
3534b5ce JG	353	irq_stat_addr[1] = 0;
a6dfde81 JG	354	irq_bits = 32;
	355	ext_irq_count = 4;
	356	ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
	357	break;
	358	case BCM6328_CPU_ID:
cc81d7f3 JG	359	irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0);
cc81d7f3 JG	360	irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0);
3534b5ce JG	361	irq_stat_addr[1] += PERF_IRQSTAT_6328_REG(1);
3534b5ce JG	362	irq_stat_addr[1] += PERF_IRQMASK_6328_REG(1);
a6dfde81 JG	363	irq_bits = 64;
	364	ext_irq_count = 4;
	365	is_ext_irq_cascaded = 1;
	366	ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
	367	ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
	368	ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
	369	break;
	370	case BCM6338_CPU_ID:
cc81d7f3 JG	371	irq_stat_addr[0] += PERF_IRQSTAT_6338_REG;
cc81d7f3 JG	372	irq_mask_addr[0] += PERF_IRQMASK_6338_REG;
3534b5ce JG	373	irq_stat_addr[1] = 0;
3534b5ce JG	374	irq_mask_addr[1] = 0;
a6dfde81 JG	375	irq_bits = 32;
	376	ext_irq_count = 4;
	377	ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
	378	break;
	379	case BCM6345_CPU_ID:
cc81d7f3 JG	380	irq_stat_addr[0] += PERF_IRQSTAT_6345_REG;
cc81d7f3 JG	381	irq_mask_addr[0] += PERF_IRQMASK_6345_REG;
3534b5ce JG	382	irq_stat_addr[1] = 0;
3534b5ce JG	383	irq_mask_addr[1] = 0;
a6dfde81 JG	384	irq_bits = 32;
	385	ext_irq_count = 4;
	386	ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
	387	break;
	388	case BCM6348_CPU_ID:
cc81d7f3 JG	389	irq_stat_addr[0] += PERF_IRQSTAT_6348_REG;
cc81d7f3 JG	390	irq_mask_addr[0] += PERF_IRQMASK_6348_REG;
3534b5ce JG	391	irq_stat_addr[1] = 0;
3534b5ce JG	392	irq_mask_addr[1] = 0;
a6dfde81 JG	393	irq_bits = 32;
	394	ext_irq_count = 4;
	395	ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
	396	break;
	397	case BCM6358_CPU_ID:
cc81d7f3 JG	398	irq_stat_addr[0] += PERF_IRQSTAT_6358_REG(0);
cc81d7f3 JG	399	irq_mask_addr[0] += PERF_IRQMASK_6358_REG(0);
3534b5ce JG	400	irq_stat_addr[1] += PERF_IRQSTAT_6358_REG(1);
3534b5ce JG	401	irq_mask_addr[1] += PERF_IRQMASK_6358_REG(1);
a6dfde81 JG	402	irq_bits = 32;
	403	ext_irq_count = 4;
	404	is_ext_irq_cascaded = 1;
	405	ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
	406	ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
	407	ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
	408	break;
	409	case BCM6362_CPU_ID:
cc81d7f3 JG	410	irq_stat_addr[0] += PERF_IRQSTAT_6362_REG(0);
cc81d7f3 JG	411	irq_mask_addr[0] += PERF_IRQMASK_6362_REG(0);
3534b5ce JG	412	irq_stat_addr[1] += PERF_IRQSTAT_6362_REG(1);
3534b5ce JG	413	irq_mask_addr[1] += PERF_IRQMASK_6362_REG(1);
a6dfde81 JG	414	irq_bits = 64;
	415	ext_irq_count = 4;
	416	is_ext_irq_cascaded = 1;
	417	ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
	418	ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
	419	ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
	420	break;
	421	case BCM6368_CPU_ID:
cc81d7f3 JG	422	irq_stat_addr[0] += PERF_IRQSTAT_6368_REG(0);
cc81d7f3 JG	423	irq_mask_addr[0] += PERF_IRQMASK_6368_REG(0);
3534b5ce JG	424	irq_stat_addr[1] += PERF_IRQSTAT_6368_REG(1);
3534b5ce JG	425	irq_mask_addr[1] += PERF_IRQMASK_6368_REG(1);
a6dfde81 JG	426	irq_bits = 64;
	427	ext_irq_count = 6;
	428	is_ext_irq_cascaded = 1;
	429	ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
	430	ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
	431	ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
	432	ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
	433	break;
	434	default:
	435	BUG();
	436	}
	437
	438	if (irq_bits == 32) {
	439	dispatch_internal = __dispatch_internal_32;
	440	internal_irq_mask = __internal_irq_mask_32;
	441	internal_irq_unmask = __internal_irq_unmask_32;
	442	} else {
	443	dispatch_internal = __dispatch_internal_64;
	444	internal_irq_mask = __internal_irq_mask_64;
	445	internal_irq_unmask = __internal_irq_unmask_64;
	446	}
	447	}
	448
e7300d04 MB	449	void __init arch_init_irq(void)
	450	{
	451	int i;
	452
f61cced9	453	bcm63xx_init_irq();
e7300d04 MB	454	mips_cpu_irq_init();
e7300d04 MB	455	for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
e4ec7989	456	irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
e7300d04 MB	457	handle_level_irq);
e7300d04 MB	458
6224892c	459	for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + ext_irq_count; ++i)
e4ec7989	460	irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,
e7300d04 MB	461	handle_edge_irq);
e7300d04 MB	462
37c42a74	463	if (!is_ext_irq_cascaded) {
6224892c	464	for (i = 3; i < 3 + ext_irq_count; ++i)
37c42a74 MB	465	setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action);
	466	}
	467
	468	setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
e7300d04	469	}