[deliverable/linux.git] / arch / mips / bcm63xx / irq.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
 * Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr>
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/irq.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_regs.h>
#include <bcm63xx_io.h>
#include <bcm63xx_irq.h>

static void __dispatch_internal(void) __maybe_unused;
static void __dispatch_internal_64(void) __maybe_unused;
static void __internal_irq_mask_32(unsigned int irq) __maybe_unused;
static void __internal_irq_mask_64(unsigned int irq) __maybe_unused;
static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;

#ifndef BCMCPU_RUNTIME_DETECT
#ifdef CONFIG_BCM63XX_CPU_6338
#define irq_stat_reg		PERF_IRQSTAT_6338_REG
#define irq_mask_reg		PERF_IRQMASK_6338_REG
#define irq_bits		32
#define is_ext_irq_cascaded	0
#define ext_irq_start		0
#define ext_irq_end		0
#define ext_irq_count		4
#define ext_irq_cfg_reg1	PERF_EXTIRQ_CFG_REG_6338
#define ext_irq_cfg_reg2	0
#endif
#ifdef CONFIG_BCM63XX_CPU_6345
#define irq_stat_reg		PERF_IRQSTAT_6345_REG
#define irq_mask_reg		PERF_IRQMASK_6345_REG
#define irq_bits		32
#define is_ext_irq_cascaded	0
#define ext_irq_start		0
#define ext_irq_end		0
#define ext_irq_count		0
#define ext_irq_cfg_reg1	0
#define ext_irq_cfg_reg2	0
#endif
#ifdef CONFIG_BCM63XX_CPU_6348
#define irq_stat_reg		PERF_IRQSTAT_6348_REG
#define irq_mask_reg		PERF_IRQMASK_6348_REG
#define irq_bits		32
#define is_ext_irq_cascaded	0
#define ext_irq_start		0
#define ext_irq_end		0
#define ext_irq_count		4
#define ext_irq_cfg_reg1	PERF_EXTIRQ_CFG_REG_6348
#define ext_irq_cfg_reg2	0
#endif
#ifdef CONFIG_BCM63XX_CPU_6358
#define irq_stat_reg		PERF_IRQSTAT_6358_REG
#define irq_mask_reg		PERF_IRQMASK_6358_REG
#define irq_bits		32
#define is_ext_irq_cascaded	1
#define ext_irq_start		(BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
#define ext_irq_end		(BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE)
#define ext_irq_count		4
#define ext_irq_cfg_reg1	PERF_EXTIRQ_CFG_REG_6358
#define ext_irq_cfg_reg2	0
#endif
#ifdef CONFIG_BCM63XX_CPU_6368
#define irq_stat_reg		PERF_IRQSTAT_6368_REG
#define irq_mask_reg		PERF_IRQMASK_6368_REG
#define irq_bits		64
#define is_ext_irq_cascaded	1
#define ext_irq_start		(BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
#define ext_irq_end		(BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE)
#define ext_irq_count		6
#define ext_irq_cfg_reg1	PERF_EXTIRQ_CFG_REG_6368
#define ext_irq_cfg_reg2	PERF_EXTIRQ_CFG_REG2_6368
#endif

#if irq_bits == 32
#define dispatch_internal			__dispatch_internal
#define internal_irq_mask			__internal_irq_mask_32
#define internal_irq_unmask			__internal_irq_unmask_32
#else
#define dispatch_internal			__dispatch_internal_64
#define internal_irq_mask			__internal_irq_mask_64
#define internal_irq_unmask			__internal_irq_unmask_64
#endif

#define irq_stat_addr	(bcm63xx_regset_address(RSET_PERF) + irq_stat_reg)
#define irq_mask_addr	(bcm63xx_regset_address(RSET_PERF) + irq_mask_reg)

static inline void bcm63xx_init_irq(void)
{
}
#else /* ! BCMCPU_RUNTIME_DETECT */

static u32 irq_stat_addr, irq_mask_addr;
static void (*dispatch_internal)(void);
static int is_ext_irq_cascaded;
static unsigned int ext_irq_count;
static unsigned int ext_irq_start, ext_irq_end;
static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;
static void (*internal_irq_mask)(unsigned int irq);
static void (*internal_irq_unmask)(unsigned int irq);

static void bcm63xx_init_irq(void)
{
	int irq_bits;

	irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
	irq_mask_addr = bcm63xx_regset_address(RSET_PERF);

	switch (bcm63xx_get_cpu_id()) {
	case BCM6338_CPU_ID:
		irq_stat_addr += PERF_IRQSTAT_6338_REG;
		irq_mask_addr += PERF_IRQMASK_6338_REG;
		irq_bits = 32;
		break;
	case BCM6345_CPU_ID:
		irq_stat_addr += PERF_IRQSTAT_6345_REG;
		irq_mask_addr += PERF_IRQMASK_6345_REG;
		irq_bits = 32;
		break;
	case BCM6348_CPU_ID:
		irq_stat_addr += PERF_IRQSTAT_6348_REG;
		irq_mask_addr += PERF_IRQMASK_6348_REG;
		irq_bits = 32;
		ext_irq_count = 4;
		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
		break;
	case BCM6358_CPU_ID:
		irq_stat_addr += PERF_IRQSTAT_6358_REG;
		irq_mask_addr += PERF_IRQMASK_6358_REG;
		irq_bits = 32;
		ext_irq_count = 4;
		is_ext_irq_cascaded = 1;
		ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
		ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
		break;
	case BCM6368_CPU_ID:
		irq_stat_addr += PERF_IRQSTAT_6368_REG;
		irq_mask_addr += PERF_IRQMASK_6368_REG;
		irq_bits = 64;
		ext_irq_count = 6;
		is_ext_irq_cascaded = 1;
		ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
		ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
		ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
		break;
	default:
		BUG();
	}

	if (irq_bits == 32) {
		dispatch_internal = __dispatch_internal;
		internal_irq_mask = __internal_irq_mask_32;
		internal_irq_unmask = __internal_irq_unmask_32;
	} else {
		dispatch_internal = __dispatch_internal_64;
		internal_irq_mask = __internal_irq_mask_64;
		internal_irq_unmask = __internal_irq_unmask_64;
	}
}
#endif /* ! BCMCPU_RUNTIME_DETECT */

static inline u32 get_ext_irq_perf_reg(int irq)
{
	if (irq < 4)
		return ext_irq_cfg_reg1;
	return ext_irq_cfg_reg2;
}

static inline void handle_internal(int intbit)
{
	if (is_ext_irq_cascaded &&
	    intbit >= ext_irq_start && intbit <= ext_irq_end)
		do_IRQ(intbit - ext_irq_start + IRQ_EXTERNAL_BASE);
	else
		do_IRQ(intbit + IRQ_INTERNAL_BASE);
}

/*
 * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
 * prioritize any interrupt relatively to another. the static counter
 * will resume the loop where it ended the last time we left this
 * function.
 */
static void __dispatch_internal(void)
{
	u32 pending;
	static int i;

	pending = bcm_readl(irq_stat_addr) & bcm_readl(irq_mask_addr);

	if (!pending)
		return ;

	while (1) {
		int to_call = i;

		i = (i + 1) & 0x1f;
		if (pending & (1 << to_call)) {
			handle_internal(to_call);
			break;
		}
	}
}

static void __dispatch_internal_64(void)
{
	u64 pending;
	static int i;

	pending = bcm_readq(irq_stat_addr) & bcm_readq(irq_mask_addr);

	if (!pending)
		return ;

	while (1) {
		int to_call = i;

		i = (i + 1) & 0x3f;
		if (pending & (1ull << to_call)) {
			handle_internal(to_call);
			break;
		}
	}
}

asmlinkage void plat_irq_dispatch(void)
{
	u32 cause;

	do {
		cause = read_c0_cause() & read_c0_status() & ST0_IM;

		if (!cause)
			break;

		if (cause & CAUSEF_IP7)
			do_IRQ(7);
		if (cause & CAUSEF_IP2)
			dispatch_internal();
		if (!is_ext_irq_cascaded) {
			if (cause & CAUSEF_IP3)
				do_IRQ(IRQ_EXT_0);
			if (cause & CAUSEF_IP4)
				do_IRQ(IRQ_EXT_1);
			if (cause & CAUSEF_IP5)
				do_IRQ(IRQ_EXT_2);
			if (cause & CAUSEF_IP6)
				do_IRQ(IRQ_EXT_3);
		}
	} while (1);
}

/*
 * internal IRQs operations: only mask/unmask on PERF irq mask
 * register.
 */
static void __internal_irq_mask_32(unsigned int irq)
{
	u32 mask;

	mask = bcm_readl(irq_mask_addr);
	mask &= ~(1 << irq);
	bcm_writel(mask, irq_mask_addr);
}

static void __internal_irq_mask_64(unsigned int irq)
{
	u64 mask;

	mask = bcm_readq(irq_mask_addr);
	mask &= ~(1ull << irq);
	bcm_writeq(mask, irq_mask_addr);
}

static void __internal_irq_unmask_32(unsigned int irq)
{
	u32 mask;

	mask = bcm_readl(irq_mask_addr);
	mask |= (1 << irq);
	bcm_writel(mask, irq_mask_addr);
}

static void __internal_irq_unmask_64(unsigned int irq)
{
	u64 mask;

	mask = bcm_readq(irq_mask_addr);
	mask |= (1ull << irq);
	bcm_writeq(mask, irq_mask_addr);
}

static void bcm63xx_internal_irq_mask(struct irq_data *d)
{
	internal_irq_mask(d->irq - IRQ_INTERNAL_BASE);
}

static void bcm63xx_internal_irq_unmask(struct irq_data *d)
{
	internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE);
}

/*
 * external IRQs operations: mask/unmask and clear on PERF external
 * irq control register.
 */
static void bcm63xx_external_irq_mask(struct irq_data *d)
{
	unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
	u32 reg, regaddr;

	regaddr = get_ext_irq_perf_reg(irq);
	reg = bcm_perf_readl(regaddr);

	if (BCMCPU_IS_6348())
		reg &= ~EXTIRQ_CFG_MASK_6348(irq % 4);
	else
		reg &= ~EXTIRQ_CFG_MASK(irq % 4);

	bcm_perf_writel(reg, regaddr);
	if (is_ext_irq_cascaded)
		internal_irq_mask(irq + ext_irq_start);
}

static void bcm63xx_external_irq_unmask(struct irq_data *d)
{
	unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
	u32 reg, regaddr;

	regaddr = get_ext_irq_perf_reg(irq);
	reg = bcm_perf_readl(regaddr);

	if (BCMCPU_IS_6348())
		reg |= EXTIRQ_CFG_MASK_6348(irq % 4);
	else
		reg |= EXTIRQ_CFG_MASK(irq % 4);

	bcm_perf_writel(reg, regaddr);

	if (is_ext_irq_cascaded)
		internal_irq_unmask(irq + ext_irq_start);
}

static void bcm63xx_external_irq_clear(struct irq_data *d)
{
	unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
	u32 reg, regaddr;

	regaddr = get_ext_irq_perf_reg(irq);
	reg = bcm_perf_readl(regaddr);

	if (BCMCPU_IS_6348())
		reg |= EXTIRQ_CFG_CLEAR_6348(irq % 4);
	else
		reg |= EXTIRQ_CFG_CLEAR(irq % 4);

	bcm_perf_writel(reg, regaddr);
}

static int bcm63xx_external_irq_set_type(struct irq_data *d,
					 unsigned int flow_type)
{
	unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
	u32 reg, regaddr;
	int levelsense, sense, bothedge;

	flow_type &= IRQ_TYPE_SENSE_MASK;

	if (flow_type == IRQ_TYPE_NONE)
		flow_type = IRQ_TYPE_LEVEL_LOW;

	levelsense = sense = bothedge = 0;
	switch (flow_type) {
	case IRQ_TYPE_EDGE_BOTH:
		bothedge = 1;
		break;

	case IRQ_TYPE_EDGE_RISING:
		sense = 1;
		break;

	case IRQ_TYPE_EDGE_FALLING:
		break;

	case IRQ_TYPE_LEVEL_HIGH:
		levelsense = 1;
		sense = 1;
		break;

	case IRQ_TYPE_LEVEL_LOW:
		levelsense = 1;
		break;

	default:
		printk(KERN_ERR "bogus flow type combination given !\n");
		return -EINVAL;
	}

	regaddr = get_ext_irq_perf_reg(irq);
	reg = bcm_perf_readl(regaddr);
	irq %= 4;

	if (BCMCPU_IS_6348()) {
		if (levelsense)
			reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq);
		else
			reg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq);
		if (sense)
			reg |= EXTIRQ_CFG_SENSE_6348(irq);
		else
			reg &= ~EXTIRQ_CFG_SENSE_6348(irq);
		if (bothedge)
			reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq);
		else
			reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
	}

	if (BCMCPU_IS_6338() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
		if (levelsense)
			reg |= EXTIRQ_CFG_LEVELSENSE(irq);
		else
			reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
		if (sense)
			reg |= EXTIRQ_CFG_SENSE(irq);
		else
			reg &= ~EXTIRQ_CFG_SENSE(irq);
		if (bothedge)
			reg |= EXTIRQ_CFG_BOTHEDGE(irq);
		else
			reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
	}

	bcm_perf_writel(reg, regaddr);

	irqd_set_trigger_type(d, flow_type);
	if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
		__irq_set_handler_locked(d->irq, handle_level_irq);
	else
		__irq_set_handler_locked(d->irq, handle_edge_irq);

	return IRQ_SET_MASK_OK_NOCOPY;
}

static struct irq_chip bcm63xx_internal_irq_chip = {
	.name		= "bcm63xx_ipic",
	.irq_mask	= bcm63xx_internal_irq_mask,
	.irq_unmask	= bcm63xx_internal_irq_unmask,
};

static struct irq_chip bcm63xx_external_irq_chip = {
	.name		= "bcm63xx_epic",
	.irq_ack	= bcm63xx_external_irq_clear,

	.irq_mask	= bcm63xx_external_irq_mask,
	.irq_unmask	= bcm63xx_external_irq_unmask,

	.irq_set_type	= bcm63xx_external_irq_set_type,
};

static struct irqaction cpu_ip2_cascade_action = {
	.handler	= no_action,
	.name		= "cascade_ip2",
	.flags		= IRQF_NO_THREAD,
};

static struct irqaction cpu_ext_cascade_action = {
	.handler	= no_action,
	.name		= "cascade_extirq",
	.flags		= IRQF_NO_THREAD,
};

void __init arch_init_irq(void)
{
	int i;

	bcm63xx_init_irq();
	mips_cpu_irq_init();
	for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
		irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
					 handle_level_irq);

	for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + ext_irq_count; ++i)
		irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,
					 handle_edge_irq);

	if (!is_ext_irq_cascaded) {
		for (i = 3; i < 3 + ext_irq_count; ++i)
			setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action);
	}

	setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
}
Commit	Line	Data
e7300d04 MB	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
	7	* Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr>
	8	*/
	9
	10	#include <linux/kernel.h>
	11	#include <linux/init.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/module.h>
ca4d3e67	14	#include <linux/irq.h>
e7300d04 MB	15	#include <asm/irq_cpu.h>
	16	#include <asm/mipsregs.h>
	17	#include <bcm63xx_cpu.h>
	18	#include <bcm63xx_regs.h>
	19	#include <bcm63xx_io.h>
	20	#include <bcm63xx_irq.h>
	21
f61cced9	22	static void __dispatch_internal(void) __maybe_unused;
71a43927 MB	23	static void __dispatch_internal_64(void) __maybe_unused;
	24	static void __internal_irq_mask_32(unsigned int irq) __maybe_unused;
	25	static void __internal_irq_mask_64(unsigned int irq) __maybe_unused;
	26	static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
	27	static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
f61cced9 MB	28
	29	#ifndef BCMCPU_RUNTIME_DETECT
	30	#ifdef CONFIG_BCM63XX_CPU_6338
	31	#define irq_stat_reg PERF_IRQSTAT_6338_REG
	32	#define irq_mask_reg PERF_IRQMASK_6338_REG
71a43927	33	#define irq_bits 32
37c42a74 MB	34	#define is_ext_irq_cascaded 0
	35	#define ext_irq_start 0
	36	#define ext_irq_end 0
6224892c MB	37	#define ext_irq_count 4
	38	#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6338
	39	#define ext_irq_cfg_reg2 0
f61cced9 MB	40	#endif
	41	#ifdef CONFIG_BCM63XX_CPU_6345
	42	#define irq_stat_reg PERF_IRQSTAT_6345_REG
	43	#define irq_mask_reg PERF_IRQMASK_6345_REG
71a43927	44	#define irq_bits 32
37c42a74 MB	45	#define is_ext_irq_cascaded 0
	46	#define ext_irq_start 0
	47	#define ext_irq_end 0
6224892c MB	48	#define ext_irq_count 0
	49	#define ext_irq_cfg_reg1 0
	50	#define ext_irq_cfg_reg2 0
f61cced9 MB	51	#endif
	52	#ifdef CONFIG_BCM63XX_CPU_6348
	53	#define irq_stat_reg PERF_IRQSTAT_6348_REG
	54	#define irq_mask_reg PERF_IRQMASK_6348_REG
71a43927	55	#define irq_bits 32
37c42a74 MB	56	#define is_ext_irq_cascaded 0
	57	#define ext_irq_start 0
	58	#define ext_irq_end 0
6224892c MB	59	#define ext_irq_count 4
	60	#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6348
	61	#define ext_irq_cfg_reg2 0
f61cced9 MB	62	#endif
	63	#ifdef CONFIG_BCM63XX_CPU_6358
	64	#define irq_stat_reg PERF_IRQSTAT_6358_REG
	65	#define irq_mask_reg PERF_IRQMASK_6358_REG
71a43927	66	#define irq_bits 32
37c42a74 MB	67	#define is_ext_irq_cascaded 1
	68	#define ext_irq_start (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
	69	#define ext_irq_end (BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE)
6224892c MB	70	#define ext_irq_count 4
	71	#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6358
	72	#define ext_irq_cfg_reg2 0
f61cced9	73	#endif
04712f3f MB	74	#ifdef CONFIG_BCM63XX_CPU_6368
	75	#define irq_stat_reg PERF_IRQSTAT_6368_REG
	76	#define irq_mask_reg PERF_IRQMASK_6368_REG
	77	#define irq_bits 64
	78	#define is_ext_irq_cascaded 1
	79	#define ext_irq_start (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
	80	#define ext_irq_end (BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE)
	81	#define ext_irq_count 6
	82	#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6368
	83	#define ext_irq_cfg_reg2 PERF_EXTIRQ_CFG_REG2_6368
	84	#endif
f61cced9	85
71a43927 MB	86	#if irq_bits == 32
	87	#define dispatch_internal __dispatch_internal
	88	#define internal_irq_mask __internal_irq_mask_32
	89	#define internal_irq_unmask __internal_irq_unmask_32
	90	#else
	91	#define dispatch_internal __dispatch_internal_64
	92	#define internal_irq_mask __internal_irq_mask_64
	93	#define internal_irq_unmask __internal_irq_unmask_64
	94	#endif
f61cced9 MB	95
	96	#define irq_stat_addr (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg)
	97	#define irq_mask_addr (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg)
	98
	99	static inline void bcm63xx_init_irq(void)
	100	{
	101	}
	102	#else /* ! BCMCPU_RUNTIME_DETECT */
	103
	104	static u32 irq_stat_addr, irq_mask_addr;
	105	static void (*dispatch_internal)(void);
37c42a74	106	static int is_ext_irq_cascaded;
6224892c	107	static unsigned int ext_irq_count;
37c42a74	108	static unsigned int ext_irq_start, ext_irq_end;
6224892c	109	static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;
71a43927 MB	110	static void (*internal_irq_mask)(unsigned int irq);
71a43927 MB	111	static void (*internal_irq_unmask)(unsigned int irq);
f61cced9 MB	112
	113	static void bcm63xx_init_irq(void)
	114	{
71a43927 MB	115	int irq_bits;
71a43927 MB	116
f61cced9 MB	117	irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
	118	irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
	119
	120	switch (bcm63xx_get_cpu_id()) {
	121	case BCM6338_CPU_ID:
	122	irq_stat_addr += PERF_IRQSTAT_6338_REG;
	123	irq_mask_addr += PERF_IRQMASK_6338_REG;
71a43927	124	irq_bits = 32;
f61cced9 MB	125	break;
	126	case BCM6345_CPU_ID:
	127	irq_stat_addr += PERF_IRQSTAT_6345_REG;
	128	irq_mask_addr += PERF_IRQMASK_6345_REG;
71a43927	129	irq_bits = 32;
f61cced9 MB	130	break;
	131	case BCM6348_CPU_ID:
	132	irq_stat_addr += PERF_IRQSTAT_6348_REG;
	133	irq_mask_addr += PERF_IRQMASK_6348_REG;
71a43927	134	irq_bits = 32;
6224892c MB	135	ext_irq_count = 4;
6224892c MB	136	ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
f61cced9 MB	137	break;
	138	case BCM6358_CPU_ID:
	139	irq_stat_addr += PERF_IRQSTAT_6358_REG;
	140	irq_mask_addr += PERF_IRQMASK_6358_REG;
71a43927	141	irq_bits = 32;
6224892c	142	ext_irq_count = 4;
37c42a74 MB	143	is_ext_irq_cascaded = 1;
	144	ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
	145	ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
6224892c	146	ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
f61cced9	147	break;
04712f3f MB	148	case BCM6368_CPU_ID:
	149	irq_stat_addr += PERF_IRQSTAT_6368_REG;
	150	irq_mask_addr += PERF_IRQMASK_6368_REG;
	151	irq_bits = 64;
	152	ext_irq_count = 6;
	153	is_ext_irq_cascaded = 1;
	154	ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
	155	ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
	156	ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
	157	ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
	158	break;
f61cced9 MB	159	default:
	160	BUG();
	161	}
	162
71a43927 MB	163	if (irq_bits == 32) {
	164	dispatch_internal = __dispatch_internal;
	165	internal_irq_mask = __internal_irq_mask_32;
	166	internal_irq_unmask = __internal_irq_unmask_32;
	167	} else {
	168	dispatch_internal = __dispatch_internal_64;
	169	internal_irq_mask = __internal_irq_mask_64;
	170	internal_irq_unmask = __internal_irq_unmask_64;
	171	}
f61cced9 MB	172	}
	173	#endif /* ! BCMCPU_RUNTIME_DETECT */
	174
6224892c MB	175	static inline u32 get_ext_irq_perf_reg(int irq)
	176	{
	177	if (irq < 4)
	178	return ext_irq_cfg_reg1;
	179	return ext_irq_cfg_reg2;
	180	}
	181
f61cced9 MB	182	static inline void handle_internal(int intbit)
f61cced9 MB	183	{
37c42a74 MB	184	if (is_ext_irq_cascaded &&
	185	intbit >= ext_irq_start && intbit <= ext_irq_end)
	186	do_IRQ(intbit - ext_irq_start + IRQ_EXTERNAL_BASE);
	187	else
	188	do_IRQ(intbit + IRQ_INTERNAL_BASE);
f61cced9 MB	189	}
f61cced9 MB	190
e7300d04 MB	191	/*
	192	* dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
	193	* prioritize any interrupt relatively to another. the static counter
	194	* will resume the loop where it ended the last time we left this
	195	* function.
	196	*/
f61cced9	197	static void __dispatch_internal(void)
e7300d04 MB	198	{
	199	u32 pending;
	200	static int i;
	201
f61cced9	202	pending = bcm_readl(irq_stat_addr) & bcm_readl(irq_mask_addr);
e7300d04 MB	203
	204	if (!pending)
	205	return ;
	206
	207	while (1) {
	208	int to_call = i;
	209
	210	i = (i + 1) & 0x1f;
	211	if (pending & (1 << to_call)) {
f61cced9	212	handle_internal(to_call);
e7300d04 MB	213	break;
	214	}
	215	}
	216	}
	217
71a43927 MB	218	static void __dispatch_internal_64(void)
	219	{
	220	u64 pending;
	221	static int i;
	222
	223	pending = bcm_readq(irq_stat_addr) & bcm_readq(irq_mask_addr);
	224
	225	if (!pending)
	226	return ;
	227
	228	while (1) {
	229	int to_call = i;
	230
	231	i = (i + 1) & 0x3f;
	232	if (pending & (1ull << to_call)) {
	233	handle_internal(to_call);
	234	break;
	235	}
	236	}
	237	}
	238
e7300d04 MB	239	asmlinkage void plat_irq_dispatch(void)
	240	{
	241	u32 cause;
	242
	243	do {
	244	cause = read_c0_cause() & read_c0_status() & ST0_IM;
	245
	246	if (!cause)
	247	break;
	248
	249	if (cause & CAUSEF_IP7)
	250	do_IRQ(7);
	251	if (cause & CAUSEF_IP2)
f61cced9	252	dispatch_internal();
37c42a74 MB	253	if (!is_ext_irq_cascaded) {
	254	if (cause & CAUSEF_IP3)
	255	do_IRQ(IRQ_EXT_0);
	256	if (cause & CAUSEF_IP4)
	257	do_IRQ(IRQ_EXT_1);
	258	if (cause & CAUSEF_IP5)
	259	do_IRQ(IRQ_EXT_2);
	260	if (cause & CAUSEF_IP6)
	261	do_IRQ(IRQ_EXT_3);
	262	}
e7300d04 MB	263	} while (1);
	264	}
	265
	266	/*
	267	* internal IRQs operations: only mask/unmask on PERF irq mask
	268	* register.
	269	*/
71a43927	270	static void __internal_irq_mask_32(unsigned int irq)
e7300d04 MB	271	{
	272	u32 mask;
	273
f61cced9	274	mask = bcm_readl(irq_mask_addr);
e7300d04	275	mask &= ~(1 << irq);
f61cced9	276	bcm_writel(mask, irq_mask_addr);
e7300d04 MB	277	}
e7300d04 MB	278
71a43927 MB	279	static void __internal_irq_mask_64(unsigned int irq)
	280	{
	281	u64 mask;
	282
	283	mask = bcm_readq(irq_mask_addr);
	284	mask &= ~(1ull << irq);
	285	bcm_writeq(mask, irq_mask_addr);
	286	}
	287
	288	static void __internal_irq_unmask_32(unsigned int irq)
e7300d04 MB	289	{
	290	u32 mask;
	291
f61cced9	292	mask = bcm_readl(irq_mask_addr);
e7300d04	293	mask \|= (1 << irq);
f61cced9	294	bcm_writel(mask, irq_mask_addr);
e7300d04 MB	295	}
e7300d04 MB	296
71a43927 MB	297	static void __internal_irq_unmask_64(unsigned int irq)
	298	{
	299	u64 mask;
	300
	301	mask = bcm_readq(irq_mask_addr);
	302	mask \|= (1ull << irq);
	303	bcm_writeq(mask, irq_mask_addr);
	304	}
	305
37c42a74 MB	306	static void bcm63xx_internal_irq_mask(struct irq_data *d)
	307	{
	308	internal_irq_mask(d->irq - IRQ_INTERNAL_BASE);
	309	}
	310
	311	static void bcm63xx_internal_irq_unmask(struct irq_data *d)
	312	{
	313	internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE);
	314	}
	315
e7300d04 MB	316	/*
	317	* external IRQs operations: mask/unmask and clear on PERF external
	318	* irq control register.
	319	*/
93f29361	320	static void bcm63xx_external_irq_mask(struct irq_data *d)
e7300d04	321	{
37c42a74	322	unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
6224892c	323	u32 reg, regaddr;
e7300d04	324
6224892c MB	325	regaddr = get_ext_irq_perf_reg(irq);
	326	reg = bcm_perf_readl(regaddr);
	327
	328	if (BCMCPU_IS_6348())
	329	reg &= ~EXTIRQ_CFG_MASK_6348(irq % 4);
	330	else
	331	reg &= ~EXTIRQ_CFG_MASK(irq % 4);
	332
	333	bcm_perf_writel(reg, regaddr);
37c42a74 MB	334	if (is_ext_irq_cascaded)
37c42a74 MB	335	internal_irq_mask(irq + ext_irq_start);
e7300d04 MB	336	}
e7300d04 MB	337
93f29361	338	static void bcm63xx_external_irq_unmask(struct irq_data *d)
e7300d04	339	{
37c42a74	340	unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
6224892c MB	341	u32 reg, regaddr;
	342
	343	regaddr = get_ext_irq_perf_reg(irq);
	344	reg = bcm_perf_readl(regaddr);
	345
	346	if (BCMCPU_IS_6348())
	347	reg \|= EXTIRQ_CFG_MASK_6348(irq % 4);
	348	else
	349	reg \|= EXTIRQ_CFG_MASK(irq % 4);
	350
	351	bcm_perf_writel(reg, regaddr);
e7300d04	352
37c42a74 MB	353	if (is_ext_irq_cascaded)
37c42a74 MB	354	internal_irq_unmask(irq + ext_irq_start);
e7300d04 MB	355	}
e7300d04 MB	356
93f29361	357	static void bcm63xx_external_irq_clear(struct irq_data *d)
e7300d04	358	{
37c42a74	359	unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
6224892c MB	360	u32 reg, regaddr;
	361
	362	regaddr = get_ext_irq_perf_reg(irq);
	363	reg = bcm_perf_readl(regaddr);
e7300d04	364
6224892c MB	365	if (BCMCPU_IS_6348())
	366	reg \|= EXTIRQ_CFG_CLEAR_6348(irq % 4);
	367	else
	368	reg \|= EXTIRQ_CFG_CLEAR(irq % 4);
	369
	370	bcm_perf_writel(reg, regaddr);
e7300d04 MB	371	}
e7300d04 MB	372
93f29361	373	static int bcm63xx_external_irq_set_type(struct irq_data *d,
e7300d04 MB	374	unsigned int flow_type)
e7300d04 MB	375	{
37c42a74	376	unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
6224892c MB	377	u32 reg, regaddr;
6224892c MB	378	int levelsense, sense, bothedge;
e7300d04 MB	379
	380	flow_type &= IRQ_TYPE_SENSE_MASK;
	381
	382	if (flow_type == IRQ_TYPE_NONE)
	383	flow_type = IRQ_TYPE_LEVEL_LOW;
	384
6224892c	385	levelsense = sense = bothedge = 0;
e7300d04 MB	386	switch (flow_type) {
e7300d04 MB	387	case IRQ_TYPE_EDGE_BOTH:
6224892c	388	bothedge = 1;
e7300d04 MB	389	break;
	390
	391	case IRQ_TYPE_EDGE_RISING:
6224892c	392	sense = 1;
e7300d04 MB	393	break;
	394
	395	case IRQ_TYPE_EDGE_FALLING:
e7300d04 MB	396	break;
	397
	398	case IRQ_TYPE_LEVEL_HIGH:
6224892c MB	399	levelsense = 1;
6224892c MB	400	sense = 1;
e7300d04 MB	401	break;
	402
	403	case IRQ_TYPE_LEVEL_LOW:
6224892c	404	levelsense = 1;
e7300d04 MB	405	break;
	406
	407	default:
	408	printk(KERN_ERR "bogus flow type combination given !\n");
	409	return -EINVAL;
	410	}
6224892c MB	411
	412	regaddr = get_ext_irq_perf_reg(irq);
	413	reg = bcm_perf_readl(regaddr);
	414	irq %= 4;
	415
	416	if (BCMCPU_IS_6348()) {
	417	if (levelsense)
	418	reg \|= EXTIRQ_CFG_LEVELSENSE_6348(irq);
	419	else
	420	reg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq);
	421	if (sense)
	422	reg \|= EXTIRQ_CFG_SENSE_6348(irq);
	423	else
	424	reg &= ~EXTIRQ_CFG_SENSE_6348(irq);
	425	if (bothedge)
	426	reg \|= EXTIRQ_CFG_BOTHEDGE_6348(irq);
	427	else
	428	reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
	429	}
	430
04712f3f	431	if (BCMCPU_IS_6338() \|\| BCMCPU_IS_6358() \|\| BCMCPU_IS_6368()) {
6224892c MB	432	if (levelsense)
	433	reg \|= EXTIRQ_CFG_LEVELSENSE(irq);
	434	else
	435	reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
	436	if (sense)
	437	reg \|= EXTIRQ_CFG_SENSE(irq);
	438	else
	439	reg &= ~EXTIRQ_CFG_SENSE(irq);
	440	if (bothedge)
	441	reg \|= EXTIRQ_CFG_BOTHEDGE(irq);
	442	else
	443	reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
	444	}
	445
	446	bcm_perf_writel(reg, regaddr);
e7300d04	447
93f29361 TG	448	irqd_set_trigger_type(d, flow_type);
	449	if (flow_type & (IRQ_TYPE_LEVEL_LOW \| IRQ_TYPE_LEVEL_HIGH))
	450	__irq_set_handler_locked(d->irq, handle_level_irq);
	451	else
	452	__irq_set_handler_locked(d->irq, handle_edge_irq);
e7300d04	453
93f29361	454	return IRQ_SET_MASK_OK_NOCOPY;
e7300d04 MB	455	}
	456
	457	static struct irq_chip bcm63xx_internal_irq_chip = {
	458	.name = "bcm63xx_ipic",
93f29361 TG	459	.irq_mask = bcm63xx_internal_irq_mask,
93f29361 TG	460	.irq_unmask = bcm63xx_internal_irq_unmask,
e7300d04 MB	461	};
	462
	463	static struct irq_chip bcm63xx_external_irq_chip = {
	464	.name = "bcm63xx_epic",
93f29361	465	.irq_ack = bcm63xx_external_irq_clear,
e7300d04	466
93f29361 TG	467	.irq_mask = bcm63xx_external_irq_mask,
93f29361 TG	468	.irq_unmask = bcm63xx_external_irq_unmask,
e7300d04	469
93f29361	470	.irq_set_type = bcm63xx_external_irq_set_type,
e7300d04 MB	471	};
	472
	473	static struct irqaction cpu_ip2_cascade_action = {
	474	.handler = no_action,
	475	.name = "cascade_ip2",
5a4a4ad8	476	.flags = IRQF_NO_THREAD,
e7300d04 MB	477	};
e7300d04 MB	478
37c42a74 MB	479	static struct irqaction cpu_ext_cascade_action = {
	480	.handler = no_action,
	481	.name = "cascade_extirq",
	482	.flags = IRQF_NO_THREAD,
	483	};
	484
e7300d04 MB	485	void __init arch_init_irq(void)
	486	{
	487	int i;
	488
f61cced9	489	bcm63xx_init_irq();
e7300d04 MB	490	mips_cpu_irq_init();
e7300d04 MB	491	for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
e4ec7989	492	irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
e7300d04 MB	493	handle_level_irq);
e7300d04 MB	494
6224892c	495	for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + ext_irq_count; ++i)
e4ec7989	496	irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,
e7300d04 MB	497	handle_edge_irq);
e7300d04 MB	498
37c42a74	499	if (!is_ext_irq_cascaded) {
6224892c	500	for (i = 3; i < 3 + ext_irq_count; ++i)
37c42a74 MB	501	setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action);
	502	}
	503
	504	setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
e7300d04	505	}