Commit | Line | Data |
---|---|---|
d666cd02 KC |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> | |
7 | * Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com> | |
8 | */ | |
9 | ||
10 | #include <linux/init.h> | |
4b049a6b | 11 | #include <linux/bitops.h> |
d666cd02 KC |
12 | #include <linux/bootmem.h> |
13 | #include <linux/clk-provider.h> | |
14 | #include <linux/ioport.h> | |
4b049a6b KC |
15 | #include <linux/kernel.h> |
16 | #include <linux/io.h> | |
d666cd02 KC |
17 | #include <linux/of.h> |
18 | #include <linux/of_fdt.h> | |
19 | #include <linux/of_platform.h> | |
20 | #include <linux/smp.h> | |
21 | #include <asm/addrspace.h> | |
22 | #include <asm/bmips.h> | |
23 | #include <asm/bootinfo.h> | |
4b049a6b KC |
24 | #include <asm/cpu-type.h> |
25 | #include <asm/mipsregs.h> | |
d666cd02 KC |
26 | #include <asm/prom.h> |
27 | #include <asm/smp-ops.h> | |
28 | #include <asm/time.h> | |
4b049a6b KC |
29 | #include <asm/traps.h> |
30 | ||
31 | #define RELO_NORMAL_VEC BIT(18) | |
32 | ||
33 | #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c)) | |
34 | #define BCM6328_TP1_DISABLED BIT(9) | |
35 | ||
36 | static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000; | |
37 | ||
38 | struct bmips_quirk { | |
39 | const char *compatible; | |
40 | void (*quirk_fn)(void); | |
41 | }; | |
42 | ||
43 | static void kbase_setup(void) | |
44 | { | |
45 | __raw_writel(kbase | RELO_NORMAL_VEC, | |
46 | BMIPS_GET_CBR() + BMIPS_RELO_VECTOR_CONTROL_1); | |
47 | ebase = kbase; | |
48 | } | |
49 | ||
50 | static void bcm3384_viper_quirks(void) | |
51 | { | |
52 | /* | |
53 | * Some experimental CM boxes are set up to let CM own the Viper TP0 | |
54 | * and let Linux own TP1. This requires moving the kernel | |
55 | * load address to a non-conflicting region (e.g. via | |
56 | * CONFIG_PHYSICAL_START) and supplying an alternate DTB. | |
57 | * If we detect this condition, we need to move the MIPS exception | |
58 | * vectors up to an area that we own. | |
59 | * | |
60 | * This is distinct from the OTHER special case mentioned in | |
61 | * smp-bmips.c (boot on TP1, but enable SMP, then TP0 becomes our | |
62 | * logical CPU#1). For the Viper TP1 case, SMP is off limits. | |
63 | * | |
64 | * Also note that many BMIPS435x CPUs do not have a | |
65 | * BMIPS_RELO_VECTOR_CONTROL_1 register, so it isn't safe to just | |
66 | * write VMLINUX_LOAD_ADDRESS into that register on every SoC. | |
67 | */ | |
68 | board_ebase_setup = &kbase_setup; | |
69 | bmips_smp_enabled = 0; | |
70 | } | |
71 | ||
72 | static void bcm63xx_fixup_cpu1(void) | |
73 | { | |
74 | /* | |
75 | * The bootloader has set up the CPU1 reset vector at | |
76 | * 0xa000_0200. | |
77 | * This conflicts with the special interrupt vector (IV). | |
78 | * The bootloader has also set up CPU1 to respond to the wrong | |
79 | * IPI interrupt. | |
80 | * Here we will start up CPU1 in the background and ask it to | |
81 | * reconfigure itself then go back to sleep. | |
82 | */ | |
83 | memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20); | |
84 | __sync(); | |
85 | set_c0_cause(C_SW0); | |
86 | cpumask_set_cpu(1, &bmips_booted_mask); | |
87 | } | |
88 | ||
89 | static void bcm6328_quirks(void) | |
90 | { | |
91 | /* Check CPU1 status in OTP (it is usually disabled) */ | |
92 | if (__raw_readl(REG_BCM6328_OTP) & BCM6328_TP1_DISABLED) | |
93 | bmips_smp_enabled = 0; | |
94 | else | |
95 | bcm63xx_fixup_cpu1(); | |
96 | } | |
97 | ||
3604b451 ÁFR |
98 | static void bcm6358_quirks(void) |
99 | { | |
100 | /* | |
101 | * BCM6358 needs special handling for its shared TLB, so | |
102 | * disable SMP for now | |
103 | */ | |
104 | bmips_smp_enabled = 0; | |
105 | } | |
106 | ||
4b049a6b KC |
107 | static void bcm6368_quirks(void) |
108 | { | |
109 | bcm63xx_fixup_cpu1(); | |
110 | } | |
111 | ||
112 | static const struct bmips_quirk bmips_quirk_list[] = { | |
113 | { "brcm,bcm3384-viper", &bcm3384_viper_quirks }, | |
114 | { "brcm,bcm33843-viper", &bcm3384_viper_quirks }, | |
115 | { "brcm,bcm6328", &bcm6328_quirks }, | |
3604b451 | 116 | { "brcm,bcm6358", &bcm6358_quirks }, |
4b049a6b | 117 | { "brcm,bcm6368", &bcm6368_quirks }, |
16580796 | 118 | { "brcm,bcm63168", &bcm6368_quirks }, |
3652acd2 | 119 | { "brcm,bcm63268", &bcm6368_quirks }, |
4b049a6b KC |
120 | { }, |
121 | }; | |
d666cd02 KC |
122 | |
123 | void __init prom_init(void) | |
124 | { | |
738a3f79 | 125 | bmips_cpu_setup(); |
d666cd02 KC |
126 | register_bmips_smp_ops(); |
127 | } | |
128 | ||
129 | void __init prom_free_prom_memory(void) | |
130 | { | |
131 | } | |
132 | ||
133 | const char *get_system_type(void) | |
134 | { | |
5f2d4459 | 135 | return "Generic BMIPS kernel"; |
d666cd02 KC |
136 | } |
137 | ||
138 | void __init plat_time_init(void) | |
139 | { | |
140 | struct device_node *np; | |
141 | u32 freq; | |
142 | ||
143 | np = of_find_node_by_name(NULL, "cpus"); | |
144 | if (!np) | |
145 | panic("missing 'cpus' DT node"); | |
146 | if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0) | |
147 | panic("missing 'mips-hpt-frequency' property"); | |
148 | of_node_put(np); | |
149 | ||
150 | mips_hpt_frequency = freq; | |
151 | } | |
152 | ||
153 | void __init plat_mem_setup(void) | |
154 | { | |
4b049a6b KC |
155 | void *dtb; |
156 | const struct bmips_quirk *q; | |
d666cd02 KC |
157 | |
158 | set_io_port_base(0); | |
159 | ioport_resource.start = 0; | |
160 | ioport_resource.end = ~0; | |
161 | ||
162 | /* intended to somewhat resemble ARM; see Documentation/arm/Booting */ | |
163 | if (fw_arg0 == 0 && fw_arg1 == 0xffffffff) | |
164 | dtb = phys_to_virt(fw_arg2); | |
ca668a2d JG |
165 | else if (fw_arg0 == -2) /* UHI interface */ |
166 | dtb = (void *)fw_arg1; | |
4b049a6b KC |
167 | else if (__dtb_start != __dtb_end) |
168 | dtb = (void *)__dtb_start; | |
169 | else | |
170 | panic("no dtb found"); | |
d666cd02 KC |
171 | |
172 | __dt_setup_arch(dtb); | |
4b049a6b KC |
173 | |
174 | for (q = bmips_quirk_list; q->quirk_fn; q++) { | |
175 | if (of_flat_dt_is_compatible(of_get_flat_dt_root(), | |
176 | q->compatible)) { | |
177 | q->quirk_fn(); | |
178 | } | |
179 | } | |
d666cd02 KC |
180 | } |
181 | ||
182 | void __init device_tree_init(void) | |
183 | { | |
184 | struct device_node *np; | |
185 | ||
186 | unflatten_and_copy_device_tree(); | |
187 | ||
188 | /* Disable SMP boot unless both CPUs are listed in DT and !disabled */ | |
189 | np = of_find_node_by_name(NULL, "cpus"); | |
190 | if (np && of_get_available_child_count(np) <= 1) | |
191 | bmips_smp_enabled = 0; | |
192 | of_node_put(np); | |
193 | } | |
194 | ||
195 | int __init plat_of_setup(void) | |
196 | { | |
c4b25709 | 197 | return __dt_register_buses("simple-bus", NULL); |
d666cd02 KC |
198 | } |
199 | ||
200 | arch_initcall(plat_of_setup); | |
201 | ||
202 | static int __init plat_dev_init(void) | |
203 | { | |
204 | of_clk_init(NULL); | |
205 | return 0; | |
206 | } | |
207 | ||
208 | device_initcall(plat_dev_init); |