[deliverable/linux.git] / arch / mips / cavium-octeon / Kconfig

if CPU_CAVIUM_OCTEON

config CAVIUM_CN63XXP1
	bool "Enable CN63XXP1 errata workarounds"
	default "n"
	help
	  The CN63XXP1 chip requires build time workarounds to
	  function reliably, select this option to enable them.  These
	  workarounds will cause a slight decrease in performance on
	  non-CN63XXP1 hardware, so it is recommended to select "n"
	  unless it is known the workarounds are needed.

config CAVIUM_OCTEON_CVMSEG_SIZE
	int "Number of L1 cache lines reserved for CVMSEG memory"
	range 0 54
	default 1
	help
	  CVMSEG LM is a segment that accesses portions of the dcache as a
	  local memory; the larger CVMSEG is, the smaller the cache is.
	  This selects the size of CVMSEG LM, which is in cache blocks. The
	  legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
	  between zero and 6192 bytes).

endif # CPU_CAVIUM_OCTEON

if CAVIUM_OCTEON_SOC

config CAVIUM_OCTEON_2ND_KERNEL
	bool "Build the kernel to be used as a 2nd kernel on the same chip"
	default "n"
	help
	  This option configures this kernel to be linked at a different
	  address and use the 2nd uart for output. This allows a kernel built
	  with this option to be run at the same time as one built without this
	  option.

config CAVIUM_OCTEON_LOCK_L2
	bool "Lock often used kernel code in the L2"
	default "y"
	help
	  Enable locking parts of the kernel into the L2 cache.

config CAVIUM_OCTEON_LOCK_L2_TLB
	bool "Lock the TLB handler in L2"
	depends on CAVIUM_OCTEON_LOCK_L2
	default "y"
	help
	  Lock the low level TLB fast path into L2.

config CAVIUM_OCTEON_LOCK_L2_EXCEPTION
	bool "Lock the exception handler in L2"
	depends on CAVIUM_OCTEON_LOCK_L2
	default "y"
	help
	  Lock the low level exception handler into L2.

config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
	bool "Lock the interrupt handler in L2"
	depends on CAVIUM_OCTEON_LOCK_L2
	default "y"
	help
	  Lock the low level interrupt handler into L2.

config CAVIUM_OCTEON_LOCK_L2_INTERRUPT
	bool "Lock the 2nd level interrupt handler in L2"
	depends on CAVIUM_OCTEON_LOCK_L2
	default "y"
	help
	  Lock the 2nd level interrupt handler in L2.

config CAVIUM_OCTEON_LOCK_L2_MEMCPY
	bool "Lock memcpy() in L2"
	depends on CAVIUM_OCTEON_LOCK_L2
	default "y"
	help
	  Lock the kernel's implementation of memcpy() into L2.

config IOMMU_HELPER
	bool

config NEED_SG_DMA_LENGTH
	bool

config SWIOTLB
	def_bool y
	select IOMMU_HELPER
	select NEED_SG_DMA_LENGTH

config OCTEON_ILM
	tristate "Module to measure interrupt latency using Octeon CIU Timer"
	help
	  This driver is a module to measure interrupt latency using the
	  the CIU Timers on Octeon.

	  To compile this driver as a module, choose M here.  The module
	  will be called octeon-ilm

endif # CAVIUM_OCTEON_SOC
Commit	Line	Data
23a271ec	1	if CPU_CAVIUM_OCTEON
5b3b1688	2
c9941158	3	config CAVIUM_CN63XXP1
f54619f2	4	bool "Enable CN63XXP1 errata workarounds"
c9941158 DD	5	default "n"
	6	help
	7	The CN63XXP1 chip requires build time workarounds to
	8	function reliably, select this option to enable them. These
	9	workarounds will cause a slight decrease in performance on
	10	non-CN63XXP1 hardware, so it is recommended to select "n"
	11	unless it is known the workarounds are needed.
	12
8a837cdb DD	13	config CAVIUM_OCTEON_CVMSEG_SIZE
	14	int "Number of L1 cache lines reserved for CVMSEG memory"
	15	range 0 54
	16	default 1
	17	help
	18	CVMSEG LM is a segment that accesses portions of the dcache as a
	19	local memory; the larger CVMSEG is, the smaller the cache is.
	20	This selects the size of CVMSEG LM, which is in cache blocks. The
	21	legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
	22	between zero and 6192 bytes).
	23
9ddebc46 DD	24	endif # CPU_CAVIUM_OCTEON
	25
	26	if CAVIUM_OCTEON_SOC
	27
5b3b1688 DD	28	config CAVIUM_OCTEON_2ND_KERNEL
5b3b1688 DD	29	bool "Build the kernel to be used as a 2nd kernel on the same chip"
5b3b1688 DD	30	default "n"
	31	help
	32	This option configures this kernel to be linked at a different
	33	address and use the 2nd uart for output. This allows a kernel built
	34	with this option to be run at the same time as one built without this
	35	option.
	36
5b3b1688 DD	37	config CAVIUM_OCTEON_LOCK_L2
5b3b1688 DD	38	bool "Lock often used kernel code in the L2"
5b3b1688 DD	39	default "y"
	40	help
	41	Enable locking parts of the kernel into the L2 cache.
	42
	43	config CAVIUM_OCTEON_LOCK_L2_TLB
	44	bool "Lock the TLB handler in L2"
	45	depends on CAVIUM_OCTEON_LOCK_L2
	46	default "y"
	47	help
	48	Lock the low level TLB fast path into L2.
	49
	50	config CAVIUM_OCTEON_LOCK_L2_EXCEPTION
	51	bool "Lock the exception handler in L2"
	52	depends on CAVIUM_OCTEON_LOCK_L2
	53	default "y"
	54	help
	55	Lock the low level exception handler into L2.
	56
	57	config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
	58	bool "Lock the interrupt handler in L2"
	59	depends on CAVIUM_OCTEON_LOCK_L2
	60	default "y"
	61	help
	62	Lock the low level interrupt handler into L2.
	63
	64	config CAVIUM_OCTEON_LOCK_L2_INTERRUPT
	65	bool "Lock the 2nd level interrupt handler in L2"
	66	depends on CAVIUM_OCTEON_LOCK_L2
	67	default "y"
	68	help
	69	Lock the 2nd level interrupt handler in L2.
	70
	71	config CAVIUM_OCTEON_LOCK_L2_MEMCPY
	72	bool "Lock memcpy() in L2"
	73	depends on CAVIUM_OCTEON_LOCK_L2
	74	default "y"
	75	help
	76	Lock the kernel's implementation of memcpy() into L2.
	77
b93b2abc DD	78	config IOMMU_HELPER
	79	bool
	80
	81	config NEED_SG_DMA_LENGTH
	82	bool
	83
	84	config SWIOTLB
	85	def_bool y
b93b2abc DD	86	select IOMMU_HELPER
b93b2abc DD	87	select NEED_SG_DMA_LENGTH
23a271ec	88
0e49caf6 VS	89	config OCTEON_ILM
	90	tristate "Module to measure interrupt latency using Octeon CIU Timer"
	91	help
	92	This driver is a module to measure interrupt latency using the
	93	the CIU Timers on Octeon.
	94
	95	To compile this driver as a module, choose M here. The module
	96	will be called octeon-ilm
	97
9ddebc46	98	endif # CAVIUM_OCTEON_SOC