[deliverable/linux.git] / arch / mips / cavium-octeon / octeon-platform.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2004-2011 Cavium Networks
 * Copyright (C) 2008 Wind River Systems
 */

#include <linux/init.h>
#include <linux/irq.h>
#include <linux/i2c.h>
#include <linux/usb.h>
#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/of_platform.h>
#include <linux/of_fdt.h>
#include <linux/libfdt.h>

#include <asm/octeon/octeon.h>
#include <asm/octeon/cvmx-rnm-defs.h>
#include <asm/octeon/cvmx-helper.h>
#include <asm/octeon/cvmx-helper-board.h>

/* Octeon Random Number Generator.  */
static int __init octeon_rng_device_init(void)
{
	struct platform_device *pd;
	int ret = 0;

	struct resource rng_resources[] = {
		{
			.flags	= IORESOURCE_MEM,
			.start	= XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
			.end	= XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
		}, {
			.flags	= IORESOURCE_MEM,
			.start	= cvmx_build_io_address(8, 0),
			.end	= cvmx_build_io_address(8, 0) + 0x7
		}
	};

	pd = platform_device_alloc("octeon_rng", -1);
	if (!pd) {
		ret = -ENOMEM;
		goto out;
	}

	ret = platform_device_add_resources(pd, rng_resources,
					    ARRAY_SIZE(rng_resources));
	if (ret)
		goto fail;

	ret = platform_device_add(pd);
	if (ret)
		goto fail;

	return ret;
fail:
	platform_device_put(pd);

out:
	return ret;
}
device_initcall(octeon_rng_device_init);

#ifdef CONFIG_USB

static int __init octeon_ehci_device_init(void)
{
	struct platform_device *pd;
	int ret = 0;

	struct resource usb_resources[] = {
		{
			.flags	= IORESOURCE_MEM,
		}, {
			.flags	= IORESOURCE_IRQ,
		}
	};

	/* Only Octeon2 has ehci/ohci */
	if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
		return 0;

	if (octeon_is_simulation() || usb_disabled())
		return 0; /* No USB in the simulator. */

	pd = platform_device_alloc("octeon-ehci", 0);
	if (!pd) {
		ret = -ENOMEM;
		goto out;
	}

	usb_resources[0].start = 0x00016F0000000000ULL;
	usb_resources[0].end = usb_resources[0].start + 0x100;

	usb_resources[1].start = OCTEON_IRQ_USB0;
	usb_resources[1].end = OCTEON_IRQ_USB0;

	ret = platform_device_add_resources(pd, usb_resources,
					    ARRAY_SIZE(usb_resources));
	if (ret)
		goto fail;

	ret = platform_device_add(pd);
	if (ret)
		goto fail;

	return ret;
fail:
	platform_device_put(pd);
out:
	return ret;
}
device_initcall(octeon_ehci_device_init);

static int __init octeon_ohci_device_init(void)
{
	struct platform_device *pd;
	int ret = 0;

	struct resource usb_resources[] = {
		{
			.flags	= IORESOURCE_MEM,
		}, {
			.flags	= IORESOURCE_IRQ,
		}
	};

	/* Only Octeon2 has ehci/ohci */
	if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
		return 0;

	if (octeon_is_simulation() || usb_disabled())
		return 0; /* No USB in the simulator. */

	pd = platform_device_alloc("octeon-ohci", 0);
	if (!pd) {
		ret = -ENOMEM;
		goto out;
	}

	usb_resources[0].start = 0x00016F0000000400ULL;
	usb_resources[0].end = usb_resources[0].start + 0x100;

	usb_resources[1].start = OCTEON_IRQ_USB0;
	usb_resources[1].end = OCTEON_IRQ_USB0;

	ret = platform_device_add_resources(pd, usb_resources,
					    ARRAY_SIZE(usb_resources));
	if (ret)
		goto fail;

	ret = platform_device_add(pd);
	if (ret)
		goto fail;

	return ret;
fail:
	platform_device_put(pd);
out:
	return ret;
}
device_initcall(octeon_ohci_device_init);

#endif /* CONFIG_USB */

static struct of_device_id __initdata octeon_ids[] = {
	{ .compatible = "simple-bus", },
	{ .compatible = "cavium,octeon-6335-uctl", },
	{ .compatible = "cavium,octeon-3860-bootbus", },
	{ .compatible = "cavium,mdio-mux", },
	{ .compatible = "gpio-leds", },
	{},
};

static bool __init octeon_has_88e1145(void)
{
	return !OCTEON_IS_MODEL(OCTEON_CN52XX) &&
	       !OCTEON_IS_MODEL(OCTEON_CN6XXX) &&
	       !OCTEON_IS_MODEL(OCTEON_CN56XX);
}

static void __init octeon_fdt_set_phy(int eth, int phy_addr)
{
	const __be32 *phy_handle;
	const __be32 *alt_phy_handle;
	const __be32 *reg;
	u32 phandle;
	int phy;
	int alt_phy;
	const char *p;
	int current_len;
	char new_name[20];

	phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL);
	if (!phy_handle)
		return;

	phandle = be32_to_cpup(phy_handle);
	phy = fdt_node_offset_by_phandle(initial_boot_params, phandle);

	alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
	if (alt_phy_handle) {
		u32 alt_phandle = be32_to_cpup(alt_phy_handle);
		alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle);
	} else {
		alt_phy = -1;
	}

	if (phy_addr < 0 || phy < 0) {
		/* Delete the PHY things */
		fdt_nop_property(initial_boot_params, eth, "phy-handle");
		/* This one may fail */
		fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle");
		if (phy >= 0)
			fdt_nop_node(initial_boot_params, phy);
		if (alt_phy >= 0)
			fdt_nop_node(initial_boot_params, alt_phy);
		return;
	}

	if (phy_addr >= 256 && alt_phy > 0) {
		const struct fdt_property *phy_prop;
		struct fdt_property *alt_prop;
		u32 phy_handle_name;

		/* Use the alt phy node instead.*/
		phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL);
		phy_handle_name = phy_prop->nameoff;
		fdt_nop_node(initial_boot_params, phy);
		fdt_nop_property(initial_boot_params, eth, "phy-handle");
		alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
		alt_prop->nameoff = phy_handle_name;
		phy = alt_phy;
	}

	phy_addr &= 0xff;

	if (octeon_has_88e1145()) {
		fdt_nop_property(initial_boot_params, phy, "marvell,reg-init");
		memset(new_name, 0, sizeof(new_name));
		strcpy(new_name, "marvell,88e1145");
		p = fdt_getprop(initial_boot_params, phy, "compatible",
				&current_len);
		if (p && current_len >= strlen(new_name))
			fdt_setprop_inplace(initial_boot_params, phy,
					"compatible", new_name, current_len);
	}

	reg = fdt_getprop(initial_boot_params, phy, "reg", NULL);
	if (phy_addr == be32_to_cpup(reg))
		return;

	fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr);

	snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr);

	p = fdt_get_name(initial_boot_params, phy, &current_len);
	if (p && current_len == strlen(new_name))
		fdt_set_name(initial_boot_params, phy, new_name);
	else
		pr_err("Error: could not rename ethernet phy: <%s>", p);
}

static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac)
{
	u8 new_mac[6];
	u64 mac = *pmac;
	int r;

	new_mac[0] = (mac >> 40) & 0xff;
	new_mac[1] = (mac >> 32) & 0xff;
	new_mac[2] = (mac >> 24) & 0xff;
	new_mac[3] = (mac >> 16) & 0xff;
	new_mac[4] = (mac >> 8) & 0xff;
	new_mac[5] = mac & 0xff;

	r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address",
				new_mac, sizeof(new_mac));

	if (r) {
		pr_err("Setting \"local-mac-address\" failed %d", r);
		return;
	}
	*pmac = mac + 1;
}

static void __init octeon_fdt_rm_ethernet(int node)
{
	const __be32 *phy_handle;

	phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL);
	if (phy_handle) {
		u32 ph = be32_to_cpup(phy_handle);
		int p = fdt_node_offset_by_phandle(initial_boot_params, ph);
		if (p >= 0)
			fdt_nop_node(initial_boot_params, p);
	}
	fdt_nop_node(initial_boot_params, node);
}

static void __init octeon_fdt_pip_port(int iface, int i, int p, int max, u64 *pmac)
{
	char name_buffer[20];
	int eth;
	int phy_addr;
	int ipd_port;

	snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p);
	eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer);
	if (eth < 0)
		return;
	if (p > max) {
		pr_debug("Deleting port %x:%x\n", i, p);
		octeon_fdt_rm_ethernet(eth);
		return;
	}
	if (OCTEON_IS_MODEL(OCTEON_CN68XX))
		ipd_port = (0x100 * i) + (0x10 * p) + 0x800;
	else
		ipd_port = 16 * i + p;

	phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
	octeon_fdt_set_phy(eth, phy_addr);
	octeon_fdt_set_mac_addr(eth, pmac);
}

static void __init octeon_fdt_pip_iface(int pip, int idx, u64 *pmac)
{
	char name_buffer[20];
	int iface;
	int p;
	int count = 0;

	if (cvmx_helper_interface_enumerate(idx) == 0)
		count = cvmx_helper_ports_on_interface(idx);

	snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx);
	iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer);
	if (iface < 0)
		return;

	for (p = 0; p < 16; p++)
		octeon_fdt_pip_port(iface, idx, p, count - 1, pmac);
}

int __init octeon_prune_device_tree(void)
{
	int i, max_port, uart_mask;
	const char *pip_path;
	const char *alias_prop;
	char name_buffer[20];
	int aliases;
	u64 mac_addr_base;

	if (fdt_check_header(initial_boot_params))
		panic("Corrupt Device Tree.");

	aliases = fdt_path_offset(initial_boot_params, "/aliases");
	if (aliases < 0) {
		pr_err("Error: No /aliases node in device tree.");
		return -EINVAL;
	}


	mac_addr_base =
		((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 |
		((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 |
		((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 |
		((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 |
		((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 |
		(octeon_bootinfo->mac_addr_base[5] & 0xffull);

	if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
		max_port = 2;
	else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))
		max_port = 1;
	else
		max_port = 0;

	if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E)
		max_port = 0;

	for (i = 0; i < 2; i++) {
		int mgmt;
		snprintf(name_buffer, sizeof(name_buffer),
			 "mix%d", i);
		alias_prop = fdt_getprop(initial_boot_params, aliases,
					name_buffer, NULL);
		if (alias_prop) {
			mgmt = fdt_path_offset(initial_boot_params, alias_prop);
			if (mgmt < 0)
				continue;
			if (i >= max_port) {
				pr_debug("Deleting mix%d\n", i);
				octeon_fdt_rm_ethernet(mgmt);
				fdt_nop_property(initial_boot_params, aliases,
						 name_buffer);
			} else {
				int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i);
				octeon_fdt_set_phy(mgmt, phy_addr);
				octeon_fdt_set_mac_addr(mgmt, &mac_addr_base);
			}
		}
	}

	pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
	if (pip_path) {
		int pip = fdt_path_offset(initial_boot_params, pip_path);
		if (pip	 >= 0)
			for (i = 0; i <= 4; i++)
				octeon_fdt_pip_iface(pip, i, &mac_addr_base);
	}

	/* I2C */
	if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
	    OCTEON_IS_MODEL(OCTEON_CN63XX) ||
	    OCTEON_IS_MODEL(OCTEON_CN68XX) ||
	    OCTEON_IS_MODEL(OCTEON_CN56XX))
		max_port = 2;
	else
		max_port = 1;

	for (i = 0; i < 2; i++) {
		int i2c;
		snprintf(name_buffer, sizeof(name_buffer),
			 "twsi%d", i);
		alias_prop = fdt_getprop(initial_boot_params, aliases,
					name_buffer, NULL);

		if (alias_prop) {
			i2c = fdt_path_offset(initial_boot_params, alias_prop);
			if (i2c < 0)
				continue;
			if (i >= max_port) {
				pr_debug("Deleting twsi%d\n", i);
				fdt_nop_node(initial_boot_params, i2c);
				fdt_nop_property(initial_boot_params, aliases,
						 name_buffer);
			}
		}
	}

	/* SMI/MDIO */
	if (OCTEON_IS_MODEL(OCTEON_CN68XX))
		max_port = 4;
	else if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
		 OCTEON_IS_MODEL(OCTEON_CN63XX) ||
		 OCTEON_IS_MODEL(OCTEON_CN56XX))
		max_port = 2;
	else
		max_port = 1;

	for (i = 0; i < 2; i++) {
		int i2c;
		snprintf(name_buffer, sizeof(name_buffer),
			 "smi%d", i);
		alias_prop = fdt_getprop(initial_boot_params, aliases,
					name_buffer, NULL);

		if (alias_prop) {
			i2c = fdt_path_offset(initial_boot_params, alias_prop);
			if (i2c < 0)
				continue;
			if (i >= max_port) {
				pr_debug("Deleting smi%d\n", i);
				fdt_nop_node(initial_boot_params, i2c);
				fdt_nop_property(initial_boot_params, aliases,
						 name_buffer);
			}
		}
	}

	/* Serial */
	uart_mask = 3;

	/* Right now CN52XX is the only chip with a third uart */
	if (OCTEON_IS_MODEL(OCTEON_CN52XX))
		uart_mask |= 4; /* uart2 */

	for (i = 0; i < 3; i++) {
		int uart;
		snprintf(name_buffer, sizeof(name_buffer),
			 "uart%d", i);
		alias_prop = fdt_getprop(initial_boot_params, aliases,
					name_buffer, NULL);

		if (alias_prop) {
			uart = fdt_path_offset(initial_boot_params, alias_prop);
			if (uart_mask & (1 << i)) {
				__be32 f;

				f = cpu_to_be32(octeon_get_io_clock_rate());
				fdt_setprop_inplace(initial_boot_params,
						    uart, "clock-frequency",
						    &f, sizeof(f));
				continue;
			}
			pr_debug("Deleting uart%d\n", i);
			fdt_nop_node(initial_boot_params, uart);
			fdt_nop_property(initial_boot_params, aliases,
					 name_buffer);
		}
	}

	/* Compact Flash */
	alias_prop = fdt_getprop(initial_boot_params, aliases,
				 "cf0", NULL);
	if (alias_prop) {
		union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
		unsigned long base_ptr, region_base, region_size;
		unsigned long region1_base = 0;
		unsigned long region1_size = 0;
		int cs, bootbus;
		bool is_16bit = false;
		bool is_true_ide = false;
		__be32 new_reg[6];
		__be32 *ranges;
		int len;

		int cf = fdt_path_offset(initial_boot_params, alias_prop);
		base_ptr = 0;
		if (octeon_bootinfo->major_version == 1
			&& octeon_bootinfo->minor_version >= 1) {
			if (octeon_bootinfo->compact_flash_common_base_addr)
				base_ptr = octeon_bootinfo->compact_flash_common_base_addr;
		} else {
			base_ptr = 0x1d000800;
		}

		if (!base_ptr)
			goto no_cf;

		/* Find CS0 region. */
		for (cs = 0; cs < 8; cs++) {
			mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
			region_base = mio_boot_reg_cfg.s.base << 16;
			region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
			if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
				&& base_ptr < region_base + region_size) {
				is_16bit = mio_boot_reg_cfg.s.width;
				break;
			}
		}
		if (cs >= 7) {
			/* cs and cs + 1 are CS0 and CS1, both must be less than 8. */
			goto no_cf;
		}

		if (!(base_ptr & 0xfffful)) {
			/*
			 * Boot loader signals availability of DMA (true_ide
			 * mode) by setting low order bits of base_ptr to
			 * zero.
			 */

			/* Asume that CS1 immediately follows. */
			mio_boot_reg_cfg.u64 =
				cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1));
			region1_base = mio_boot_reg_cfg.s.base << 16;
			region1_size = (mio_boot_reg_cfg.s.size + 1) << 16;
			if (!mio_boot_reg_cfg.s.en)
				goto no_cf;
			is_true_ide = true;

		} else {
			fdt_nop_property(initial_boot_params, cf, "cavium,true-ide");
			fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle");
			if (!is_16bit) {
				__be32 width = cpu_to_be32(8);
				fdt_setprop_inplace(initial_boot_params, cf,
						"cavium,bus-width", &width, sizeof(width));
			}
		}
		new_reg[0] = cpu_to_be32(cs);
		new_reg[1] = cpu_to_be32(0);
		new_reg[2] = cpu_to_be32(0x10000);
		new_reg[3] = cpu_to_be32(cs + 1);
		new_reg[4] = cpu_to_be32(0);
		new_reg[5] = cpu_to_be32(0x10000);
		fdt_setprop_inplace(initial_boot_params, cf,
				    "reg",  new_reg, sizeof(new_reg));

		bootbus = fdt_parent_offset(initial_boot_params, cf);
		if (bootbus < 0)
			goto no_cf;
		ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
		if (!ranges || len < (5 * 8 * sizeof(__be32)))
			goto no_cf;

		ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
		ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
		ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
		if (is_true_ide) {
			cs++;
			ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32);
			ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff);
			ranges[(cs * 5) + 4] = cpu_to_be32(region1_size);
		}
		goto end_cf;
no_cf:
		fdt_nop_node(initial_boot_params, cf);

end_cf:
		;
	}

	/* 8 char LED */
	alias_prop = fdt_getprop(initial_boot_params, aliases,
				 "led0", NULL);
	if (alias_prop) {
		union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
		unsigned long base_ptr, region_base, region_size;
		int cs, bootbus;
		__be32 new_reg[6];
		__be32 *ranges;
		int len;
		int led = fdt_path_offset(initial_boot_params, alias_prop);

		base_ptr = octeon_bootinfo->led_display_base_addr;
		if (base_ptr == 0)
			goto no_led;
		/* Find CS0 region. */
		for (cs = 0; cs < 8; cs++) {
			mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
			region_base = mio_boot_reg_cfg.s.base << 16;
			region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
			if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
				&& base_ptr < region_base + region_size)
				break;
		}

		if (cs > 7)
			goto no_led;

		new_reg[0] = cpu_to_be32(cs);
		new_reg[1] = cpu_to_be32(0x20);
		new_reg[2] = cpu_to_be32(0x20);
		new_reg[3] = cpu_to_be32(cs);
		new_reg[4] = cpu_to_be32(0);
		new_reg[5] = cpu_to_be32(0x20);
		fdt_setprop_inplace(initial_boot_params, led,
				    "reg",  new_reg, sizeof(new_reg));

		bootbus = fdt_parent_offset(initial_boot_params, led);
		if (bootbus < 0)
			goto no_led;
		ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
		if (!ranges || len < (5 * 8 * sizeof(__be32)))
			goto no_led;

		ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
		ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
		ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
		goto end_led;

no_led:
		fdt_nop_node(initial_boot_params, led);
end_led:
		;
	}

	/* OHCI/UHCI USB */
	alias_prop = fdt_getprop(initial_boot_params, aliases,
				 "uctl", NULL);
	if (alias_prop) {
		int uctl = fdt_path_offset(initial_boot_params, alias_prop);

		if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) ||
				  octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) {
			pr_debug("Deleting uctl\n");
			fdt_nop_node(initial_boot_params, uctl);
			fdt_nop_property(initial_boot_params, aliases, "uctl");
		} else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E ||
			   octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) {
			/* Missing "refclk-type" defaults to crystal. */
			fdt_nop_property(initial_boot_params, uctl, "refclk-type");
		}
	}

	return 0;
}

static int __init octeon_publish_devices(void)
{
	return of_platform_bus_probe(NULL, octeon_ids, NULL);
}
device_initcall(octeon_publish_devices);

MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Platform driver for Octeon SOC");
Commit	Line	Data
512254ba DD	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
7ed18152	6	* Copyright (C) 2004-2011 Cavium Networks
512254ba DD	7	* Copyright (C) 2008 Wind River Systems
	8	*/
	9
	10	#include <linux/init.h>
	11	#include <linux/irq.h>
d9577054	12	#include <linux/i2c.h>
340fbb8b	13	#include <linux/usb.h>
f1299072	14	#include <linux/dma-mapping.h>
512254ba	15	#include <linux/module.h>
7ed18152	16	#include <linux/slab.h>
512254ba	17	#include <linux/platform_device.h>
7ed18152 DD	18	#include <linux/of_platform.h>
	19	#include <linux/of_fdt.h>
	20	#include <linux/libfdt.h>
512254ba DD	21
	22	#include <asm/octeon/octeon.h>
	23	#include <asm/octeon/cvmx-rnm-defs.h>
7ed18152 DD	24	#include <asm/octeon/cvmx-helper.h>
7ed18152 DD	25	#include <asm/octeon/cvmx-helper-board.h>
512254ba	26
512254ba DD	27	/* Octeon Random Number Generator. */
	28	static int __init octeon_rng_device_init(void)
	29	{
	30	struct platform_device *pd;
	31	int ret = 0;
	32
	33	struct resource rng_resources[] = {
	34	{
	35	.flags = IORESOURCE_MEM,
	36	.start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
	37	.end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
	38	}, {
	39	.flags = IORESOURCE_MEM,
	40	.start = cvmx_build_io_address(8, 0),
	41	.end = cvmx_build_io_address(8, 0) + 0x7
	42	}
	43	};
	44
	45	pd = platform_device_alloc("octeon_rng", -1);
	46	if (!pd) {
	47	ret = -ENOMEM;
	48	goto out;
	49	}
	50
	51	ret = platform_device_add_resources(pd, rng_resources,
	52	ARRAY_SIZE(rng_resources));
	53	if (ret)
	54	goto fail;
	55
	56	ret = platform_device_add(pd);
	57	if (ret)
	58	goto fail;
	59
	60	return ret;
	61	fail:
	62	platform_device_put(pd);
	63
	64	out:
	65	return ret;
	66	}
	67	device_initcall(octeon_rng_device_init);
	68
340fbb8b DD	69	#ifdef CONFIG_USB
	70
	71	static int __init octeon_ehci_device_init(void)
	72	{
	73	struct platform_device *pd;
	74	int ret = 0;
	75
	76	struct resource usb_resources[] = {
	77	{
	78	.flags = IORESOURCE_MEM,
	79	}, {
	80	.flags = IORESOURCE_IRQ,
	81	}
	82	};
	83
	84	/* Only Octeon2 has ehci/ohci */
	85	if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
	86	return 0;
	87
	88	if (octeon_is_simulation() \|\| usb_disabled())
	89	return 0; /* No USB in the simulator. */
	90
	91	pd = platform_device_alloc("octeon-ehci", 0);
	92	if (!pd) {
	93	ret = -ENOMEM;
	94	goto out;
	95	}
	96
	97	usb_resources[0].start = 0x00016F0000000000ULL;
	98	usb_resources[0].end = usb_resources[0].start + 0x100;
	99
	100	usb_resources[1].start = OCTEON_IRQ_USB0;
	101	usb_resources[1].end = OCTEON_IRQ_USB0;
	102
	103	ret = platform_device_add_resources(pd, usb_resources,
	104	ARRAY_SIZE(usb_resources));
	105	if (ret)
	106	goto fail;
	107
	108	ret = platform_device_add(pd);
	109	if (ret)
	110	goto fail;
	111
	112	return ret;
	113	fail:
	114	platform_device_put(pd);
	115	out:
	116	return ret;
	117	}
	118	device_initcall(octeon_ehci_device_init);
	119
	120	static int __init octeon_ohci_device_init(void)
	121	{
	122	struct platform_device *pd;
	123	int ret = 0;
	124
	125	struct resource usb_resources[] = {
	126	{
	127	.flags = IORESOURCE_MEM,
	128	}, {
	129	.flags = IORESOURCE_IRQ,
	130	}
	131	};
	132
133	/* Only Octeon2 has ehci/ohci */
134	if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
135	return 0;
136
137	if (octeon_is_simulation() \|\| usb_disabled())
138	return 0; /* No USB in the simulator. */
139
140	pd = platform_device_alloc("octeon-ohci", 0);
141	if (!pd) {
142	ret = -ENOMEM;
143	goto out;
144	}
145
146	usb_resources[0].start = 0x00016F0000000400ULL;
147	usb_resources[0].end = usb_resources[0].start + 0x100;
148
149	usb_resources[1].start = OCTEON_IRQ_USB0;
150	usb_resources[1].end = OCTEON_IRQ_USB0;
151
152	ret = platform_device_add_resources(pd, usb_resources,
153	ARRAY_SIZE(usb_resources));
154	if (ret)
155	goto fail;
156
157	ret = platform_device_add(pd);
158	if (ret)
159	goto fail;
160
161	return ret;
162	fail:
163	platform_device_put(pd);
164	out:
165	return ret;
166	}
167	device_initcall(octeon_ohci_device_init);
168
169	#endif /* CONFIG_USB */
170
7ed18152 DD	171	static struct of_device_id __initdata octeon_ids[] = {
	172	{ .compatible = "simple-bus", },
	173	{ .compatible = "cavium,octeon-6335-uctl", },
	174	{ .compatible = "cavium,octeon-3860-bootbus", },
	175	{ .compatible = "cavium,mdio-mux", },
	176	{ .compatible = "gpio-leds", },
	177	{},
	178	};
	179
	180	static bool __init octeon_has_88e1145(void)
	181	{
	182	return !OCTEON_IS_MODEL(OCTEON_CN52XX) &&
	183	!OCTEON_IS_MODEL(OCTEON_CN6XXX) &&
	184	!OCTEON_IS_MODEL(OCTEON_CN56XX);
	185	}
	186
	187	static void __init octeon_fdt_set_phy(int eth, int phy_addr)
	188	{
	189	const __be32 *phy_handle;
	190	const __be32 *alt_phy_handle;
	191	const __be32 *reg;
	192	u32 phandle;
	193	int phy;
	194	int alt_phy;
	195	const char *p;
	196	int current_len;
	197	char new_name[20];
	198
	199	phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL);
	200	if (!phy_handle)
	201	return;
	202
	203	phandle = be32_to_cpup(phy_handle);
	204	phy = fdt_node_offset_by_phandle(initial_boot_params, phandle);
	205
	206	alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
	207	if (alt_phy_handle) {
	208	u32 alt_phandle = be32_to_cpup(alt_phy_handle);
	209	alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle);
	210	} else {
	211	alt_phy = -1;
	212	}
	213
	214	if (phy_addr < 0 \|\| phy < 0) {
	215	/* Delete the PHY things */
	216	fdt_nop_property(initial_boot_params, eth, "phy-handle");
	217	/* This one may fail */
	218	fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle");
	219	if (phy >= 0)
	220	fdt_nop_node(initial_boot_params, phy);
	221	if (alt_phy >= 0)
	222	fdt_nop_node(initial_boot_params, alt_phy);
	223	return;
	224	}
	225
	226	if (phy_addr >= 256 && alt_phy > 0) {
	227	const struct fdt_property *phy_prop;
	228	struct fdt_property *alt_prop;
	229	u32 phy_handle_name;
	230
	231	/* Use the alt phy node instead.*/
	232	phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL);
	233	phy_handle_name = phy_prop->nameoff;
	234	fdt_nop_node(initial_boot_params, phy);
235	fdt_nop_property(initial_boot_params, eth, "phy-handle");
236	alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
237	alt_prop->nameoff = phy_handle_name;
238	phy = alt_phy;
239	}
240
241	phy_addr &= 0xff;
242
243	if (octeon_has_88e1145()) {
244	fdt_nop_property(initial_boot_params, phy, "marvell,reg-init");
245	memset(new_name, 0, sizeof(new_name));
246	strcpy(new_name, "marvell,88e1145");
247	p = fdt_getprop(initial_boot_params, phy, "compatible",
248	&current_len);
249	if (p && current_len >= strlen(new_name))
250	fdt_setprop_inplace(initial_boot_params, phy,
251	"compatible", new_name, current_len);
252	}
253
254	reg = fdt_getprop(initial_boot_params, phy, "reg", NULL);
255	if (phy_addr == be32_to_cpup(reg))
256	return;
257
258	fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr);
259
260	snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr);
261
262	p = fdt_get_name(initial_boot_params, phy, &current_len);
263	if (p && current_len == strlen(new_name))
264	fdt_set_name(initial_boot_params, phy, new_name);
265	else
266	pr_err("Error: could not rename ethernet phy: <%s>", p);
267	}
268
269	static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac)
270	{
271	u8 new_mac[6];
272	u64 mac = *pmac;
273	int r;
274
275	new_mac[0] = (mac >> 40) & 0xff;
276	new_mac[1] = (mac >> 32) & 0xff;
277	new_mac[2] = (mac >> 24) & 0xff;
278	new_mac[3] = (mac >> 16) & 0xff;
279	new_mac[4] = (mac >> 8) & 0xff;
280	new_mac[5] = mac & 0xff;
281
282	r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address",
283	new_mac, sizeof(new_mac));
284
285	if (r) {
286	pr_err("Setting \"local-mac-address\" failed %d", r);
287	return;
288	}
289	*pmac = mac + 1;
290	}
291
292	static void __init octeon_fdt_rm_ethernet(int node)
293	{
294	const __be32 *phy_handle;
295
296	phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL);
297	if (phy_handle) {
298	u32 ph = be32_to_cpup(phy_handle);
299	int p = fdt_node_offset_by_phandle(initial_boot_params, ph);
300	if (p >= 0)
301	fdt_nop_node(initial_boot_params, p);
302	}
303	fdt_nop_node(initial_boot_params, node);
304	}
305
306	static void __init octeon_fdt_pip_port(int iface, int i, int p, int max, u64 *pmac)
307	{
308	char name_buffer[20];
309	int eth;
310	int phy_addr;
311	int ipd_port;
312
313	snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p);
314	eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer);
315	if (eth < 0)
316	return;
317	if (p > max) {
318	pr_debug("Deleting port %x:%x\n", i, p);
319	octeon_fdt_rm_ethernet(eth);
320	return;
321	}
322	if (OCTEON_IS_MODEL(OCTEON_CN68XX))
323	ipd_port = (0x100 * i) + (0x10 * p) + 0x800;
324	else
325	ipd_port = 16 * i + p;
326
327	phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
328	octeon_fdt_set_phy(eth, phy_addr);
329	octeon_fdt_set_mac_addr(eth, pmac);
330	}
331
332	static void __init octeon_fdt_pip_iface(int pip, int idx, u64 *pmac)
333	{
334	char name_buffer[20];
335	int iface;
336	int p;
ab2bb148	337	int count = 0;
7ed18152	338
ab2bb148 FL	339	if (cvmx_helper_interface_enumerate(idx) == 0)
ab2bb148 FL	340	count = cvmx_helper_ports_on_interface(idx);
7ed18152 DD	341
	342	snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx);
	343	iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer);
	344	if (iface < 0)
	345	return;
	346
	347	for (p = 0; p < 16; p++)
	348	octeon_fdt_pip_port(iface, idx, p, count - 1, pmac);
	349	}
	350
	351	int __init octeon_prune_device_tree(void)
	352	{
	353	int i, max_port, uart_mask;
	354	const char *pip_path;
	355	const char *alias_prop;
	356	char name_buffer[20];
	357	int aliases;
	358	u64 mac_addr_base;
	359
	360	if (fdt_check_header(initial_boot_params))
	361	panic("Corrupt Device Tree.");
	362
	363	aliases = fdt_path_offset(initial_boot_params, "/aliases");
	364	if (aliases < 0) {
	365	pr_err("Error: No /aliases node in device tree.");
	366	return -EINVAL;
	367	}
	368
	369
	370	mac_addr_base =
	371	((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 \|
	372	((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 \|
	373	((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 \|
	374	((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 \|
	375	((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 \|
	376	(octeon_bootinfo->mac_addr_base[5] & 0xffull);
	377
	378	if (OCTEON_IS_MODEL(OCTEON_CN52XX) \|\| OCTEON_IS_MODEL(OCTEON_CN63XX))
	379	max_port = 2;
	380	else if (OCTEON_IS_MODEL(OCTEON_CN56XX) \|\| OCTEON_IS_MODEL(OCTEON_CN68XX))
	381	max_port = 1;
	382	else
	383	max_port = 0;
	384
	385	if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E)
	386	max_port = 0;
	387
	388	for (i = 0; i < 2; i++) {
	389	int mgmt;
	390	snprintf(name_buffer, sizeof(name_buffer),
	391	"mix%d", i);
	392	alias_prop = fdt_getprop(initial_boot_params, aliases,
	393	name_buffer, NULL);
	394	if (alias_prop) {
	395	mgmt = fdt_path_offset(initial_boot_params, alias_prop);
	396	if (mgmt < 0)
	397	continue;
	398	if (i >= max_port) {
	399	pr_debug("Deleting mix%d\n", i);
	400	octeon_fdt_rm_ethernet(mgmt);
	401	fdt_nop_property(initial_boot_params, aliases,
	402	name_buffer);
	403	} else {
	404	int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i);
405	octeon_fdt_set_phy(mgmt, phy_addr);
406	octeon_fdt_set_mac_addr(mgmt, &mac_addr_base);
407	}
408	}
409	}
410
411	pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
412	if (pip_path) {
413	int pip = fdt_path_offset(initial_boot_params, pip_path);
70342287	414	if (pip >= 0)
7ed18152 DD	415	for (i = 0; i <= 4; i++)
	416	octeon_fdt_pip_iface(pip, i, &mac_addr_base);
	417	}
	418
	419	/* I2C */
	420	if (OCTEON_IS_MODEL(OCTEON_CN52XX) \|\|
	421	OCTEON_IS_MODEL(OCTEON_CN63XX) \|\|
	422	OCTEON_IS_MODEL(OCTEON_CN68XX) \|\|
	423	OCTEON_IS_MODEL(OCTEON_CN56XX))
	424	max_port = 2;
	425	else
	426	max_port = 1;
	427
	428	for (i = 0; i < 2; i++) {
	429	int i2c;
	430	snprintf(name_buffer, sizeof(name_buffer),
	431	"twsi%d", i);
	432	alias_prop = fdt_getprop(initial_boot_params, aliases,
	433	name_buffer, NULL);
	434
	435	if (alias_prop) {
	436	i2c = fdt_path_offset(initial_boot_params, alias_prop);
	437	if (i2c < 0)
	438	continue;
	439	if (i >= max_port) {
	440	pr_debug("Deleting twsi%d\n", i);
	441	fdt_nop_node(initial_boot_params, i2c);
	442	fdt_nop_property(initial_boot_params, aliases,
	443	name_buffer);
	444	}
	445	}
	446	}
	447
	448	/* SMI/MDIO */
	449	if (OCTEON_IS_MODEL(OCTEON_CN68XX))
	450	max_port = 4;
	451	else if (OCTEON_IS_MODEL(OCTEON_CN52XX) \|\|
	452	OCTEON_IS_MODEL(OCTEON_CN63XX) \|\|
	453	OCTEON_IS_MODEL(OCTEON_CN56XX))
	454	max_port = 2;
	455	else
	456	max_port = 1;
	457
	458	for (i = 0; i < 2; i++) {
	459	int i2c;
	460	snprintf(name_buffer, sizeof(name_buffer),
	461	"smi%d", i);
	462	alias_prop = fdt_getprop(initial_boot_params, aliases,
	463	name_buffer, NULL);
	464
	465	if (alias_prop) {
	466	i2c = fdt_path_offset(initial_boot_params, alias_prop);
	467	if (i2c < 0)
	468	continue;
	469	if (i >= max_port) {
	470	pr_debug("Deleting smi%d\n", i);
	471	fdt_nop_node(initial_boot_params, i2c);
	472	fdt_nop_property(initial_boot_params, aliases,
	473	name_buffer);
	474	}
	475	}
	476	}
	477
	478	/* Serial */
479	uart_mask = 3;
480
481	/* Right now CN52XX is the only chip with a third uart */
482	if (OCTEON_IS_MODEL(OCTEON_CN52XX))
483	uart_mask \|= 4; /* uart2 */
484
485	for (i = 0; i < 3; i++) {
486	int uart;
487	snprintf(name_buffer, sizeof(name_buffer),
488	"uart%d", i);
489	alias_prop = fdt_getprop(initial_boot_params, aliases,
490	name_buffer, NULL);
491
492	if (alias_prop) {
493	uart = fdt_path_offset(initial_boot_params, alias_prop);
5219343f DD	494	if (uart_mask & (1 << i)) {
	495	__be32 f;
	496
	497	f = cpu_to_be32(octeon_get_io_clock_rate());
	498	fdt_setprop_inplace(initial_boot_params,
	499	uart, "clock-frequency",
	500	&f, sizeof(f));
7ed18152	501	continue;
5219343f	502	}
7ed18152 DD	503	pr_debug("Deleting uart%d\n", i);
	504	fdt_nop_node(initial_boot_params, uart);
	505	fdt_nop_property(initial_boot_params, aliases,
	506	name_buffer);
	507	}
	508	}
	509
	510	/* Compact Flash */
	511	alias_prop = fdt_getprop(initial_boot_params, aliases,
	512	"cf0", NULL);
	513	if (alias_prop) {
	514	union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
	515	unsigned long base_ptr, region_base, region_size;
	516	unsigned long region1_base = 0;
	517	unsigned long region1_size = 0;
	518	int cs, bootbus;
	519	bool is_16bit = false;
	520	bool is_true_ide = false;
	521	__be32 new_reg[6];
	522	__be32 *ranges;
	523	int len;
	524
	525	int cf = fdt_path_offset(initial_boot_params, alias_prop);
	526	base_ptr = 0;
	527	if (octeon_bootinfo->major_version == 1
	528	&& octeon_bootinfo->minor_version >= 1) {
	529	if (octeon_bootinfo->compact_flash_common_base_addr)
	530	base_ptr = octeon_bootinfo->compact_flash_common_base_addr;
	531	} else {
	532	base_ptr = 0x1d000800;
	533	}
	534
	535	if (!base_ptr)
	536	goto no_cf;
	537
	538	/* Find CS0 region. */
	539	for (cs = 0; cs < 8; cs++) {
	540	mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
	541	region_base = mio_boot_reg_cfg.s.base << 16;
	542	region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
	543	if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
	544	&& base_ptr < region_base + region_size) {
	545	is_16bit = mio_boot_reg_cfg.s.width;
	546	break;
	547	}
	548	}
	549	if (cs >= 7) {
	550	/* cs and cs + 1 are CS0 and CS1, both must be less than 8. */
	551	goto no_cf;
	552	}
	553
	554	if (!(base_ptr & 0xfffful)) {
	555	/*
	556	* Boot loader signals availability of DMA (true_ide
	557	* mode) by setting low order bits of base_ptr to
	558	* zero.
	559	*/
	560
	561	/* Asume that CS1 immediately follows. */
	562	mio_boot_reg_cfg.u64 =
	563	cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1));
	564	region1_base = mio_boot_reg_cfg.s.base << 16;
	565	region1_size = (mio_boot_reg_cfg.s.size + 1) << 16;
	566	if (!mio_boot_reg_cfg.s.en)
567	goto no_cf;
568	is_true_ide = true;
569
570	} else {
571	fdt_nop_property(initial_boot_params, cf, "cavium,true-ide");
572	fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle");
573	if (!is_16bit) {
574	__be32 width = cpu_to_be32(8);
575	fdt_setprop_inplace(initial_boot_params, cf,
576	"cavium,bus-width", &width, sizeof(width));
577	}
578	}
579	new_reg[0] = cpu_to_be32(cs);
580	new_reg[1] = cpu_to_be32(0);
581	new_reg[2] = cpu_to_be32(0x10000);
582	new_reg[3] = cpu_to_be32(cs + 1);
583	new_reg[4] = cpu_to_be32(0);
584	new_reg[5] = cpu_to_be32(0x10000);
585	fdt_setprop_inplace(initial_boot_params, cf,
586	"reg", new_reg, sizeof(new_reg));
587
588	bootbus = fdt_parent_offset(initial_boot_params, cf);
589	if (bootbus < 0)
590	goto no_cf;
591	ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
592	if (!ranges \|\| len < (5 * 8 * sizeof(__be32)))
593	goto no_cf;
594
595	ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
596	ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
597	ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
598	if (is_true_ide) {
599	cs++;
600	ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32);
601	ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff);
602	ranges[(cs * 5) + 4] = cpu_to_be32(region1_size);
603	}
604	goto end_cf;
605	no_cf:
606	fdt_nop_node(initial_boot_params, cf);
607
608	end_cf:
609	;
610	}
611
612	/* 8 char LED */
613	alias_prop = fdt_getprop(initial_boot_params, aliases,
614	"led0", NULL);
615	if (alias_prop) {
616	union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
617	unsigned long base_ptr, region_base, region_size;
618	int cs, bootbus;
619	__be32 new_reg[6];
620	__be32 *ranges;
621	int len;
622	int led = fdt_path_offset(initial_boot_params, alias_prop);
623
624	base_ptr = octeon_bootinfo->led_display_base_addr;
625	if (base_ptr == 0)
626	goto no_led;
627	/* Find CS0 region. */
628	for (cs = 0; cs < 8; cs++) {
629	mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
630	region_base = mio_boot_reg_cfg.s.base << 16;
631	region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
632	if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
633	&& base_ptr < region_base + region_size)
634	break;
635	}
636
637	if (cs > 7)
638	goto no_led;
639
640	new_reg[0] = cpu_to_be32(cs);
641	new_reg[1] = cpu_to_be32(0x20);
642	new_reg[2] = cpu_to_be32(0x20);
643	new_reg[3] = cpu_to_be32(cs);
644	new_reg[4] = cpu_to_be32(0);
645	new_reg[5] = cpu_to_be32(0x20);
646	fdt_setprop_inplace(initial_boot_params, led,
647	"reg", new_reg, sizeof(new_reg));
648
649	bootbus = fdt_parent_offset(initial_boot_params, led);
650	if (bootbus < 0)
651	goto no_led;
652	ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
653	if (!ranges \|\| len < (5 * 8 * sizeof(__be32)))
654	goto no_led;
655
656	ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
657	ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
658	ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
659	goto end_led;
660
661	no_led:
662	fdt_nop_node(initial_boot_params, led);
663	end_led:
664	;
665	}
666
667	/* OHCI/UHCI USB */
668	alias_prop = fdt_getprop(initial_boot_params, aliases,
669	"uctl", NULL);
670	if (alias_prop) {
671	int uctl = fdt_path_offset(initial_boot_params, alias_prop);
672
673	if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) \|\|
674	octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) {
675	pr_debug("Deleting uctl\n");
676	fdt_nop_node(initial_boot_params, uctl);
677	fdt_nop_property(initial_boot_params, aliases, "uctl");
678	} else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E \|\|
679	octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) {
680	/* Missing "refclk-type" defaults to crystal. */
681	fdt_nop_property(initial_boot_params, uctl, "refclk-type");
682	}
683	}
684
685	return 0;
686	}
687
688	static int __init octeon_publish_devices(void)
689	{
690	return of_platform_bus_probe(NULL, octeon_ids, NULL);
691	}
692	device_initcall(octeon_publish_devices);
693
512254ba DD	694	MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
	695	MODULE_LICENSE("GPL");
	696	MODULE_DESCRIPTION("Platform driver for Octeon SOC");