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5b3b1688 DD |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2004-2007 Cavium Networks | |
f65aad41 RB |
7 | * Copyright (C) 2008, 2009 Wind River Systems |
8 | * written by Ralf Baechle <ralf@linux-mips.org> | |
5b3b1688 | 9 | */ |
39205750 | 10 | #include <linux/compiler.h> |
d8b74276 | 11 | #include <linux/vmalloc.h> |
5b3b1688 | 12 | #include <linux/init.h> |
f65aad41 | 13 | #include <linux/kernel.h> |
5b3b1688 DD |
14 | #include <linux/console.h> |
15 | #include <linux/delay.h> | |
f9ded569 | 16 | #include <linux/export.h> |
5b3b1688 DD |
17 | #include <linux/interrupt.h> |
18 | #include <linux/io.h> | |
5b3b1688 | 19 | #include <linux/serial.h> |
631330f5 | 20 | #include <linux/smp.h> |
5b3b1688 DD |
21 | #include <linux/types.h> |
22 | #include <linux/string.h> /* for memset */ | |
5b3b1688 DD |
23 | #include <linux/tty.h> |
24 | #include <linux/time.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/serial_core.h> | |
27 | #include <linux/serial_8250.h> | |
7ed18152 DD |
28 | #include <linux/of_fdt.h> |
29 | #include <linux/libfdt.h> | |
abe77f90 | 30 | #include <linux/kexec.h> |
5b3b1688 DD |
31 | |
32 | #include <asm/processor.h> | |
33 | #include <asm/reboot.h> | |
34 | #include <asm/smp-ops.h> | |
5b3b1688 DD |
35 | #include <asm/irq_cpu.h> |
36 | #include <asm/mipsregs.h> | |
37 | #include <asm/bootinfo.h> | |
38 | #include <asm/sections.h> | |
39 | #include <asm/time.h> | |
40 | ||
41 | #include <asm/octeon/octeon.h> | |
2b5987ab | 42 | #include <asm/octeon/pci-octeon.h> |
e195aa30 | 43 | #include <asm/octeon/cvmx-mio-defs.h> |
ac6d9b3a | 44 | #include <asm/octeon/cvmx-rst-defs.h> |
5b3b1688 | 45 | |
5b3b1688 DD |
46 | extern struct plat_smp_ops octeon_smp_ops; |
47 | ||
48 | #ifdef CONFIG_PCI | |
49 | extern void pci_console_init(const char *arg); | |
50 | #endif | |
51 | ||
5b3b1688 DD |
52 | static unsigned long long MAX_MEMORY = 512ull << 20; |
53 | ||
24d4e7f6 DD |
54 | DEFINE_SEMAPHORE(octeon_bootbus_sem); |
55 | EXPORT_SYMBOL(octeon_bootbus_sem); | |
56 | ||
5b3b1688 DD |
57 | struct octeon_boot_descriptor *octeon_boot_desc_ptr; |
58 | ||
59 | struct cvmx_bootinfo *octeon_bootinfo; | |
60 | EXPORT_SYMBOL(octeon_bootinfo); | |
61 | ||
abe77f90 RB |
62 | static unsigned long long RESERVE_LOW_MEM = 0ull; |
63 | #ifdef CONFIG_KEXEC | |
64 | #ifdef CONFIG_SMP | |
65 | /* | |
66 | * Wait for relocation code is prepared and send | |
67 | * secondary CPUs to spin until kernel is relocated. | |
68 | */ | |
69 | static void octeon_kexec_smp_down(void *ignored) | |
70 | { | |
71 | int cpu = smp_processor_id(); | |
72 | ||
73 | local_irq_disable(); | |
74 | set_cpu_online(cpu, false); | |
75 | while (!atomic_read(&kexec_ready_to_reboot)) | |
76 | cpu_relax(); | |
77 | ||
78 | asm volatile ( | |
79 | " sync \n" | |
80 | " synci ($0) \n"); | |
81 | ||
82 | relocated_kexec_smp_wait(NULL); | |
83 | } | |
84 | #endif | |
85 | ||
86 | #define OCTEON_DDR0_BASE (0x0ULL) | |
87 | #define OCTEON_DDR0_SIZE (0x010000000ULL) | |
88 | #define OCTEON_DDR1_BASE (0x410000000ULL) | |
89 | #define OCTEON_DDR1_SIZE (0x010000000ULL) | |
90 | #define OCTEON_DDR2_BASE (0x020000000ULL) | |
91 | #define OCTEON_DDR2_SIZE (0x3e0000000ULL) | |
92 | #define OCTEON_MAX_PHY_MEM_SIZE (16*1024*1024*1024ULL) | |
93 | ||
94 | static struct kimage *kimage_ptr; | |
95 | ||
96 | static void kexec_bootmem_init(uint64_t mem_size, uint32_t low_reserved_bytes) | |
97 | { | |
98 | int64_t addr; | |
99 | struct cvmx_bootmem_desc *bootmem_desc; | |
100 | ||
101 | bootmem_desc = cvmx_bootmem_get_desc(); | |
102 | ||
103 | if (mem_size > OCTEON_MAX_PHY_MEM_SIZE) { | |
104 | mem_size = OCTEON_MAX_PHY_MEM_SIZE; | |
105 | pr_err("Error: requested memory too large," | |
106 | "truncating to maximum size\n"); | |
107 | } | |
108 | ||
109 | bootmem_desc->major_version = CVMX_BOOTMEM_DESC_MAJ_VER; | |
110 | bootmem_desc->minor_version = CVMX_BOOTMEM_DESC_MIN_VER; | |
111 | ||
112 | addr = (OCTEON_DDR0_BASE + RESERVE_LOW_MEM + low_reserved_bytes); | |
113 | bootmem_desc->head_addr = 0; | |
114 | ||
115 | if (mem_size <= OCTEON_DDR0_SIZE) { | |
116 | __cvmx_bootmem_phy_free(addr, | |
117 | mem_size - RESERVE_LOW_MEM - | |
118 | low_reserved_bytes, 0); | |
119 | return; | |
120 | } | |
121 | ||
122 | __cvmx_bootmem_phy_free(addr, | |
123 | OCTEON_DDR0_SIZE - RESERVE_LOW_MEM - | |
124 | low_reserved_bytes, 0); | |
125 | ||
126 | mem_size -= OCTEON_DDR0_SIZE; | |
127 | ||
128 | if (mem_size > OCTEON_DDR1_SIZE) { | |
129 | __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, OCTEON_DDR1_SIZE, 0); | |
130 | __cvmx_bootmem_phy_free(OCTEON_DDR2_BASE, | |
131 | mem_size - OCTEON_DDR1_SIZE, 0); | |
132 | } else | |
133 | __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, mem_size, 0); | |
134 | } | |
135 | ||
136 | static int octeon_kexec_prepare(struct kimage *image) | |
137 | { | |
138 | int i; | |
139 | char *bootloader = "kexec"; | |
140 | ||
141 | octeon_boot_desc_ptr->argc = 0; | |
142 | for (i = 0; i < image->nr_segments; i++) { | |
143 | if (!strncmp(bootloader, (char *)image->segment[i].buf, | |
144 | strlen(bootloader))) { | |
145 | /* | |
146 | * convert command line string to array | |
147 | * of parameters (as bootloader does). | |
148 | */ | |
149 | int argc = 0, offt; | |
150 | char *str = (char *)image->segment[i].buf; | |
151 | char *ptr = strchr(str, ' '); | |
152 | while (ptr && (OCTEON_ARGV_MAX_ARGS > argc)) { | |
153 | *ptr = '\0'; | |
154 | if (ptr[1] != ' ') { | |
155 | offt = (int)(ptr - str + 1); | |
156 | octeon_boot_desc_ptr->argv[argc] = | |
157 | image->segment[i].mem + offt; | |
158 | argc++; | |
159 | } | |
160 | ptr = strchr(ptr + 1, ' '); | |
161 | } | |
162 | octeon_boot_desc_ptr->argc = argc; | |
163 | break; | |
164 | } | |
165 | } | |
166 | ||
167 | /* | |
168 | * Information about segments will be needed during pre-boot memory | |
169 | * initialization. | |
170 | */ | |
171 | kimage_ptr = image; | |
172 | return 0; | |
173 | } | |
174 | ||
175 | static void octeon_generic_shutdown(void) | |
176 | { | |
ed1197f9 ES |
177 | int i; |
178 | #ifdef CONFIG_SMP | |
179 | int cpu; | |
180 | #endif | |
abe77f90 RB |
181 | struct cvmx_bootmem_desc *bootmem_desc; |
182 | void *named_block_array_ptr; | |
183 | ||
184 | bootmem_desc = cvmx_bootmem_get_desc(); | |
185 | named_block_array_ptr = | |
186 | cvmx_phys_to_ptr(bootmem_desc->named_block_array_addr); | |
187 | ||
188 | #ifdef CONFIG_SMP | |
189 | /* disable watchdogs */ | |
190 | for_each_online_cpu(cpu) | |
191 | cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); | |
192 | #else | |
193 | cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); | |
194 | #endif | |
195 | if (kimage_ptr != kexec_crash_image) { | |
196 | memset(named_block_array_ptr, | |
197 | 0x0, | |
198 | CVMX_BOOTMEM_NUM_NAMED_BLOCKS * | |
199 | sizeof(struct cvmx_bootmem_named_block_desc)); | |
200 | /* | |
201 | * Mark all memory (except low 0x100000 bytes) as free. | |
202 | * It is the same thing that bootloader does. | |
203 | */ | |
204 | kexec_bootmem_init(octeon_bootinfo->dram_size*1024ULL*1024ULL, | |
205 | 0x100000); | |
206 | /* | |
207 | * Allocate all segments to avoid their corruption during boot. | |
208 | */ | |
209 | for (i = 0; i < kimage_ptr->nr_segments; i++) | |
210 | cvmx_bootmem_alloc_address( | |
211 | kimage_ptr->segment[i].memsz + 2*PAGE_SIZE, | |
212 | kimage_ptr->segment[i].mem - PAGE_SIZE, | |
213 | PAGE_SIZE); | |
214 | } else { | |
215 | /* | |
216 | * Do not mark all memory as free. Free only named sections | |
217 | * leaving the rest of memory unchanged. | |
218 | */ | |
219 | struct cvmx_bootmem_named_block_desc *ptr = | |
220 | (struct cvmx_bootmem_named_block_desc *) | |
221 | named_block_array_ptr; | |
222 | ||
223 | for (i = 0; i < bootmem_desc->named_block_num_blocks; i++) | |
224 | if (ptr[i].size) | |
225 | cvmx_bootmem_free_named(ptr[i].name); | |
226 | } | |
227 | kexec_args[2] = 1UL; /* running on octeon_main_processor */ | |
228 | kexec_args[3] = (unsigned long)octeon_boot_desc_ptr; | |
229 | #ifdef CONFIG_SMP | |
230 | secondary_kexec_args[2] = 0UL; /* running on secondary cpu */ | |
231 | secondary_kexec_args[3] = (unsigned long)octeon_boot_desc_ptr; | |
232 | #endif | |
233 | } | |
234 | ||
235 | static void octeon_shutdown(void) | |
236 | { | |
237 | octeon_generic_shutdown(); | |
238 | #ifdef CONFIG_SMP | |
239 | smp_call_function(octeon_kexec_smp_down, NULL, 0); | |
240 | smp_wmb(); | |
241 | while (num_online_cpus() > 1) { | |
242 | cpu_relax(); | |
243 | mdelay(1); | |
244 | } | |
245 | #endif | |
246 | } | |
247 | ||
248 | static void octeon_crash_shutdown(struct pt_regs *regs) | |
249 | { | |
250 | octeon_generic_shutdown(); | |
251 | default_machine_crash_shutdown(regs); | |
252 | } | |
253 | ||
254 | #endif /* CONFIG_KEXEC */ | |
255 | ||
5b3b1688 DD |
256 | #ifdef CONFIG_CAVIUM_RESERVE32 |
257 | uint64_t octeon_reserve32_memory; | |
258 | EXPORT_SYMBOL(octeon_reserve32_memory); | |
259 | #endif | |
260 | ||
abe77f90 RB |
261 | #ifdef CONFIG_KEXEC |
262 | /* crashkernel cmdline parameter is parsed _after_ memory setup | |
263 | * we also parse it here (workaround for EHB5200) */ | |
264 | static uint64_t crashk_size, crashk_base; | |
265 | #endif | |
266 | ||
5b3b1688 DD |
267 | static int octeon_uart; |
268 | ||
269 | extern asmlinkage void handle_int(void); | |
5b3b1688 DD |
270 | |
271 | /** | |
272 | * Return non zero if we are currently running in the Octeon simulator | |
273 | * | |
274 | * Returns | |
275 | */ | |
276 | int octeon_is_simulation(void) | |
277 | { | |
278 | return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM; | |
279 | } | |
280 | EXPORT_SYMBOL(octeon_is_simulation); | |
281 | ||
282 | /** | |
283 | * Return true if Octeon is in PCI Host mode. This means | |
284 | * Linux can control the PCI bus. | |
285 | * | |
286 | * Returns Non zero if Octeon in host mode. | |
287 | */ | |
288 | int octeon_is_pci_host(void) | |
289 | { | |
290 | #ifdef CONFIG_PCI | |
291 | return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST; | |
292 | #else | |
293 | return 0; | |
294 | #endif | |
295 | } | |
296 | ||
297 | /** | |
298 | * Get the clock rate of Octeon | |
299 | * | |
300 | * Returns Clock rate in HZ | |
301 | */ | |
302 | uint64_t octeon_get_clock_rate(void) | |
303 | { | |
e195aa30 DD |
304 | struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get(); |
305 | ||
306 | return sysinfo->cpu_clock_hz; | |
5b3b1688 DD |
307 | } |
308 | EXPORT_SYMBOL(octeon_get_clock_rate); | |
309 | ||
e195aa30 DD |
310 | static u64 octeon_io_clock_rate; |
311 | ||
312 | u64 octeon_get_io_clock_rate(void) | |
313 | { | |
314 | return octeon_io_clock_rate; | |
315 | } | |
316 | EXPORT_SYMBOL(octeon_get_io_clock_rate); | |
317 | ||
318 | ||
5b3b1688 DD |
319 | /** |
320 | * Write to the LCD display connected to the bootbus. This display | |
321 | * exists on most Cavium evaluation boards. If it doesn't exist, then | |
322 | * this function doesn't do anything. | |
323 | * | |
70342287 | 324 | * @s: String to write |
5b3b1688 DD |
325 | */ |
326 | void octeon_write_lcd(const char *s) | |
327 | { | |
328 | if (octeon_bootinfo->led_display_base_addr) { | |
329 | void __iomem *lcd_address = | |
330 | ioremap_nocache(octeon_bootinfo->led_display_base_addr, | |
331 | 8); | |
332 | int i; | |
333 | for (i = 0; i < 8; i++, s++) { | |
334 | if (*s) | |
335 | iowrite8(*s, lcd_address + i); | |
336 | else | |
337 | iowrite8(' ', lcd_address + i); | |
338 | } | |
339 | iounmap(lcd_address); | |
340 | } | |
341 | } | |
342 | ||
343 | /** | |
344 | * Return the console uart passed by the bootloader | |
345 | * | |
70342287 | 346 | * Returns uart (0 or 1) |
5b3b1688 DD |
347 | */ |
348 | int octeon_get_boot_uart(void) | |
349 | { | |
350 | int uart; | |
351 | #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL | |
352 | uart = 1; | |
353 | #else | |
354 | uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ? | |
355 | 1 : 0; | |
356 | #endif | |
357 | return uart; | |
358 | } | |
359 | ||
360 | /** | |
361 | * Get the coremask Linux was booted on. | |
362 | * | |
363 | * Returns Core mask | |
364 | */ | |
365 | int octeon_get_boot_coremask(void) | |
366 | { | |
367 | return octeon_boot_desc_ptr->core_mask; | |
368 | } | |
369 | ||
370 | /** | |
371 | * Check the hardware BIST results for a CPU | |
372 | */ | |
373 | void octeon_check_cpu_bist(void) | |
374 | { | |
375 | const int coreid = cvmx_get_core_num(); | |
376 | unsigned long long mask; | |
377 | unsigned long long bist_val; | |
378 | ||
379 | /* Check BIST results for COP0 registers */ | |
380 | mask = 0x1f00000000ull; | |
381 | bist_val = read_octeon_c0_icacheerr(); | |
382 | if (bist_val & mask) | |
383 | pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n", | |
384 | coreid, bist_val); | |
385 | ||
386 | bist_val = read_octeon_c0_dcacheerr(); | |
387 | if (bist_val & 1) | |
388 | pr_err("Core%d L1 Dcache parity error: " | |
389 | "CacheErr(dcache) = 0x%llx\n", | |
390 | coreid, bist_val); | |
391 | ||
392 | mask = 0xfc00000000000000ull; | |
393 | bist_val = read_c0_cvmmemctl(); | |
394 | if (bist_val & mask) | |
395 | pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n", | |
396 | coreid, bist_val); | |
397 | ||
398 | write_octeon_c0_dcacheerr(0); | |
399 | } | |
400 | ||
5b3b1688 DD |
401 | /** |
402 | * Reboot Octeon | |
403 | * | |
404 | * @command: Command to pass to the bootloader. Currently ignored. | |
405 | */ | |
406 | static void octeon_restart(char *command) | |
407 | { | |
408 | /* Disable all watchdogs before soft reset. They don't get cleared */ | |
409 | #ifdef CONFIG_SMP | |
410 | int cpu; | |
411 | for_each_online_cpu(cpu) | |
412 | cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); | |
413 | #else | |
414 | cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); | |
415 | #endif | |
416 | ||
417 | mb(); | |
418 | while (1) | |
fe2360f8 CC |
419 | if (OCTEON_IS_OCTEON3()) |
420 | cvmx_write_csr(CVMX_RST_SOFT_RST, 1); | |
421 | else | |
422 | cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); | |
5b3b1688 DD |
423 | } |
424 | ||
425 | ||
426 | /** | |
427 | * Permanently stop a core. | |
428 | * | |
429 | * @arg: Ignored. | |
430 | */ | |
431 | static void octeon_kill_core(void *arg) | |
432 | { | |
38c3c0f6 | 433 | if (octeon_is_simulation()) |
5b3b1688 | 434 | /* A break instruction causes the simulator stop a core */ |
38c3c0f6 DD |
435 | asm volatile ("break" ::: "memory"); |
436 | ||
437 | local_irq_disable(); | |
438 | /* Disable watchdog on this core. */ | |
439 | cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); | |
440 | /* Spin in a low power mode. */ | |
441 | while (true) | |
442 | asm volatile ("wait" ::: "memory"); | |
5b3b1688 DD |
443 | } |
444 | ||
445 | ||
446 | /** | |
447 | * Halt the system | |
448 | */ | |
449 | static void octeon_halt(void) | |
450 | { | |
451 | smp_call_function(octeon_kill_core, NULL, 0); | |
452 | ||
453 | switch (octeon_bootinfo->board_type) { | |
454 | case CVMX_BOARD_TYPE_NAO38: | |
455 | /* Driving a 1 to GPIO 12 shuts off this board */ | |
456 | cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1); | |
457 | cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000); | |
458 | break; | |
459 | default: | |
460 | octeon_write_lcd("PowerOff"); | |
461 | break; | |
462 | } | |
463 | ||
464 | octeon_kill_core(NULL); | |
465 | } | |
466 | ||
60830868 AK |
467 | static char __read_mostly octeon_system_type[80]; |
468 | ||
469 | static int __init init_octeon_system_type(void) | |
470 | { | |
471 | snprintf(octeon_system_type, sizeof(octeon_system_type), "%s (%s)", | |
472 | cvmx_board_type_to_string(octeon_bootinfo->board_type), | |
473 | octeon_model_get_string(read_c0_prid())); | |
474 | ||
475 | return 0; | |
476 | } | |
477 | early_initcall(init_octeon_system_type); | |
478 | ||
5b3b1688 DD |
479 | /** |
480 | * Return a string representing the system type | |
481 | * | |
482 | * Returns | |
483 | */ | |
484 | const char *octeon_board_type_string(void) | |
485 | { | |
60830868 | 486 | return octeon_system_type; |
5b3b1688 DD |
487 | } |
488 | ||
489 | const char *get_system_type(void) | |
490 | __attribute__ ((alias("octeon_board_type_string"))); | |
491 | ||
492 | void octeon_user_io_init(void) | |
493 | { | |
494 | union octeon_cvmemctl cvmmemctl; | |
495 | union cvmx_iob_fau_timeout fau_timeout; | |
496 | union cvmx_pow_nw_tim nm_tim; | |
5b3b1688 DD |
497 | |
498 | /* Get the current settings for CP0_CVMMEMCTL_REG */ | |
499 | cvmmemctl.u64 = read_c0_cvmmemctl(); | |
500 | /* R/W If set, marked write-buffer entries time out the same | |
501 | * as as other entries; if clear, marked write-buffer entries | |
502 | * use the maximum timeout. */ | |
503 | cvmmemctl.s.dismarkwblongto = 1; | |
504 | /* R/W If set, a merged store does not clear the write-buffer | |
505 | * entry timeout state. */ | |
506 | cvmmemctl.s.dismrgclrwbto = 0; | |
507 | /* R/W Two bits that are the MSBs of the resultant CVMSEG LM | |
508 | * word location for an IOBDMA. The other 8 bits come from the | |
509 | * SCRADDR field of the IOBDMA. */ | |
510 | cvmmemctl.s.iobdmascrmsb = 0; | |
511 | /* R/W If set, SYNCWS and SYNCS only order marked stores; if | |
512 | * clear, SYNCWS and SYNCS only order unmarked | |
513 | * stores. SYNCWSMARKED has no effect when DISSYNCWS is | |
514 | * set. */ | |
515 | cvmmemctl.s.syncwsmarked = 0; | |
516 | /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */ | |
517 | cvmmemctl.s.dissyncws = 0; | |
518 | /* R/W If set, no stall happens on write buffer full. */ | |
519 | if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) | |
520 | cvmmemctl.s.diswbfst = 1; | |
521 | else | |
522 | cvmmemctl.s.diswbfst = 0; | |
523 | /* R/W If set (and SX set), supervisor-level loads/stores can | |
524 | * use XKPHYS addresses with <48>==0 */ | |
525 | cvmmemctl.s.xkmemenas = 0; | |
526 | ||
527 | /* R/W If set (and UX set), user-level loads/stores can use | |
528 | * XKPHYS addresses with VA<48>==0 */ | |
529 | cvmmemctl.s.xkmemenau = 0; | |
530 | ||
531 | /* R/W If set (and SX set), supervisor-level loads/stores can | |
532 | * use XKPHYS addresses with VA<48>==1 */ | |
533 | cvmmemctl.s.xkioenas = 0; | |
534 | ||
535 | /* R/W If set (and UX set), user-level loads/stores can use | |
536 | * XKPHYS addresses with VA<48>==1 */ | |
537 | cvmmemctl.s.xkioenau = 0; | |
538 | ||
539 | /* R/W If set, all stores act as SYNCW (NOMERGE must be set | |
540 | * when this is set) RW, reset to 0. */ | |
541 | cvmmemctl.s.allsyncw = 0; | |
542 | ||
543 | /* R/W If set, no stores merge, and all stores reach the | |
544 | * coherent bus in order. */ | |
545 | cvmmemctl.s.nomerge = 0; | |
546 | /* R/W Selects the bit in the counter used for DID time-outs 0 | |
547 | * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is | |
548 | * between 1x and 2x this interval. For example, with | |
549 | * DIDTTO=3, expiration interval is between 16K and 32K. */ | |
550 | cvmmemctl.s.didtto = 0; | |
551 | /* R/W If set, the (mem) CSR clock never turns off. */ | |
552 | cvmmemctl.s.csrckalwys = 0; | |
553 | /* R/W If set, mclk never turns off. */ | |
554 | cvmmemctl.s.mclkalwys = 0; | |
555 | /* R/W Selects the bit in the counter used for write buffer | |
556 | * flush time-outs (WBFLT+11) is the bit position in an | |
557 | * internal counter used to determine expiration. The write | |
558 | * buffer expires between 1x and 2x this interval. For | |
559 | * example, with WBFLT = 0, a write buffer expires between 2K | |
560 | * and 4K cycles after the write buffer entry is allocated. */ | |
561 | cvmmemctl.s.wbfltime = 0; | |
562 | /* R/W If set, do not put Istream in the L2 cache. */ | |
563 | cvmmemctl.s.istrnol2 = 0; | |
c9941158 DD |
564 | |
565 | /* | |
566 | * R/W The write buffer threshold. As per erratum Core-14752 | |
567 | * for CN63XX, a sc/scd might fail if the write buffer is | |
568 | * full. Lowering WBTHRESH greatly lowers the chances of the | |
569 | * write buffer ever being full and triggering the erratum. | |
570 | */ | |
571 | if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) | |
572 | cvmmemctl.s.wbthresh = 4; | |
573 | else | |
574 | cvmmemctl.s.wbthresh = 10; | |
575 | ||
5b3b1688 DD |
576 | /* R/W If set, CVMSEG is available for loads/stores in |
577 | * kernel/debug mode. */ | |
578 | #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 | |
579 | cvmmemctl.s.cvmsegenak = 1; | |
580 | #else | |
581 | cvmmemctl.s.cvmsegenak = 0; | |
582 | #endif | |
583 | /* R/W If set, CVMSEG is available for loads/stores in | |
584 | * supervisor mode. */ | |
585 | cvmmemctl.s.cvmsegenas = 0; | |
586 | /* R/W If set, CVMSEG is available for loads/stores in user | |
587 | * mode. */ | |
588 | cvmmemctl.s.cvmsegenau = 0; | |
5b3b1688 | 589 | |
c9941158 | 590 | write_c0_cvmmemctl(cvmmemctl.u64); |
5b3b1688 | 591 | |
726da2f8 | 592 | /* Setup of CVMSEG is done in kernel-entry-init.h */ |
5b3b1688 DD |
593 | if (smp_processor_id() == 0) |
594 | pr_notice("CVMSEG size: %d cache lines (%d bytes)\n", | |
595 | CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE, | |
596 | CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128); | |
597 | ||
5b3b1688 DD |
598 | /* Set a default for the hardware timeouts */ |
599 | fau_timeout.u64 = 0; | |
600 | fau_timeout.s.tout_val = 0xfff; | |
601 | /* Disable tagwait FAU timeout */ | |
602 | fau_timeout.s.tout_enb = 0; | |
603 | cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64); | |
604 | ||
605 | nm_tim.u64 = 0; | |
606 | /* 4096 cycles */ | |
607 | nm_tim.s.nw_tim = 3; | |
608 | cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64); | |
609 | ||
610 | write_octeon_c0_icacheerr(0); | |
611 | write_c0_derraddr1(0); | |
612 | } | |
613 | ||
614 | /** | |
615 | * Early entry point for arch setup | |
616 | */ | |
617 | void __init prom_init(void) | |
618 | { | |
619 | struct cvmx_sysinfo *sysinfo; | |
abe77f90 RB |
620 | const char *arg; |
621 | char *p; | |
5b3b1688 | 622 | int i; |
ac655fb7 | 623 | u64 t; |
5b3b1688 | 624 | int argc; |
5b3b1688 DD |
625 | #ifdef CONFIG_CAVIUM_RESERVE32 |
626 | int64_t addr = -1; | |
627 | #endif | |
628 | /* | |
629 | * The bootloader passes a pointer to the boot descriptor in | |
630 | * $a3, this is available as fw_arg3. | |
631 | */ | |
632 | octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3; | |
633 | octeon_bootinfo = | |
634 | cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr); | |
635 | cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr)); | |
636 | ||
e195aa30 DD |
637 | sysinfo = cvmx_sysinfo_get(); |
638 | memset(sysinfo, 0, sizeof(*sysinfo)); | |
639 | sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20; | |
7d52ab16 DD |
640 | sysinfo->phy_mem_desc_addr = (u64)phys_to_virt(octeon_bootinfo->phy_mem_desc_addr); |
641 | ||
642 | if ((octeon_bootinfo->major_version > 1) || | |
643 | (octeon_bootinfo->major_version == 1 && | |
644 | octeon_bootinfo->minor_version >= 4)) | |
645 | cvmx_coremask_copy(&sysinfo->core_mask, | |
646 | &octeon_bootinfo->ext_core_mask); | |
647 | else | |
648 | cvmx_coremask_set64(&sysinfo->core_mask, | |
649 | octeon_bootinfo->core_mask); | |
650 | ||
651 | /* Some broken u-boot pass garbage in upper bits, clear them out */ | |
652 | if (!OCTEON_IS_MODEL(OCTEON_CN78XX)) | |
653 | for (i = 512; i < 1024; i++) | |
654 | cvmx_coremask_clear_core(&sysinfo->core_mask, i); | |
655 | ||
e195aa30 DD |
656 | sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr; |
657 | sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz; | |
658 | sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2; | |
659 | sysinfo->board_type = octeon_bootinfo->board_type; | |
660 | sysinfo->board_rev_major = octeon_bootinfo->board_rev_major; | |
661 | sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor; | |
662 | memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base, | |
663 | sizeof(sysinfo->mac_addr_base)); | |
664 | sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count; | |
665 | memcpy(sysinfo->board_serial_number, | |
666 | octeon_bootinfo->board_serial_number, | |
667 | sizeof(sysinfo->board_serial_number)); | |
668 | sysinfo->compact_flash_common_base_addr = | |
669 | octeon_bootinfo->compact_flash_common_base_addr; | |
670 | sysinfo->compact_flash_attribute_base_addr = | |
671 | octeon_bootinfo->compact_flash_attribute_base_addr; | |
672 | sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr; | |
673 | sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz; | |
674 | sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags; | |
675 | ||
ac6d9b3a | 676 | if (OCTEON_IS_OCTEON2()) { |
e195aa30 DD |
677 | /* I/O clock runs at a different rate than the CPU. */ |
678 | union cvmx_mio_rst_boot rst_boot; | |
679 | rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT); | |
680 | octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul; | |
ac6d9b3a CC |
681 | } else if (OCTEON_IS_OCTEON3()) { |
682 | /* I/O clock runs at a different rate than the CPU. */ | |
683 | union cvmx_rst_boot rst_boot; | |
684 | rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT); | |
685 | octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul; | |
e195aa30 DD |
686 | } else { |
687 | octeon_io_clock_rate = sysinfo->cpu_clock_hz; | |
688 | } | |
689 | ||
ac655fb7 DD |
690 | t = read_c0_cvmctl(); |
691 | if ((t & (1ull << 27)) == 0) { | |
692 | /* | |
693 | * Setup the multiplier save/restore code if | |
694 | * CvmCtl[NOMUL] clear. | |
695 | */ | |
696 | void *save; | |
697 | void *save_end; | |
698 | void *restore; | |
699 | void *restore_end; | |
700 | int save_len; | |
701 | int restore_len; | |
702 | int save_max = (char *)octeon_mult_save_end - | |
703 | (char *)octeon_mult_save; | |
704 | int restore_max = (char *)octeon_mult_restore_end - | |
705 | (char *)octeon_mult_restore; | |
706 | if (current_cpu_data.cputype == CPU_CAVIUM_OCTEON3) { | |
707 | save = octeon_mult_save3; | |
708 | save_end = octeon_mult_save3_end; | |
709 | restore = octeon_mult_restore3; | |
710 | restore_end = octeon_mult_restore3_end; | |
711 | } else { | |
712 | save = octeon_mult_save2; | |
713 | save_end = octeon_mult_save2_end; | |
714 | restore = octeon_mult_restore2; | |
715 | restore_end = octeon_mult_restore2_end; | |
716 | } | |
717 | save_len = (char *)save_end - (char *)save; | |
718 | restore_len = (char *)restore_end - (char *)restore; | |
719 | if (!WARN_ON(save_len > save_max || | |
720 | restore_len > restore_max)) { | |
721 | memcpy(octeon_mult_save, save, save_len); | |
722 | memcpy(octeon_mult_restore, restore, restore_len); | |
723 | } | |
724 | } | |
725 | ||
5b3b1688 DD |
726 | /* |
727 | * Only enable the LED controller if we're running on a CN38XX, CN58XX, | |
728 | * or CN56XX. The CN30XX and CN31XX don't have an LED controller. | |
729 | */ | |
730 | if (!octeon_is_simulation() && | |
731 | octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) { | |
732 | cvmx_write_csr(CVMX_LED_EN, 0); | |
733 | cvmx_write_csr(CVMX_LED_PRT, 0); | |
734 | cvmx_write_csr(CVMX_LED_DBG, 0); | |
735 | cvmx_write_csr(CVMX_LED_PRT_FMT, 0); | |
736 | cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32); | |
737 | cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32); | |
738 | cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0); | |
739 | cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0); | |
740 | cvmx_write_csr(CVMX_LED_EN, 1); | |
741 | } | |
742 | #ifdef CONFIG_CAVIUM_RESERVE32 | |
743 | /* | |
744 | * We need to temporarily allocate all memory in the reserve32 | |
745 | * region. This makes sure the kernel doesn't allocate this | |
746 | * memory when it is getting memory from the | |
747 | * bootloader. Later, after the memory allocations are | |
748 | * complete, the reserve32 will be freed. | |
1ef28870 | 749 | * |
5b3b1688 DD |
750 | * Allocate memory for RESERVED32 aligned on 2MB boundary. This |
751 | * is in case we later use hugetlb entries with it. | |
752 | */ | |
753 | addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20, | |
754 | 0, 0, 2 << 20, | |
755 | "CAVIUM_RESERVE32", 0); | |
5b3b1688 DD |
756 | if (addr < 0) |
757 | pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n"); | |
758 | else | |
759 | octeon_reserve32_memory = addr; | |
760 | #endif | |
761 | ||
762 | #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2 | |
763 | if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { | |
764 | pr_info("Skipping L2 locking due to reduced L2 cache size\n"); | |
765 | } else { | |
39205750 | 766 | uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000; |
5b3b1688 DD |
767 | #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB |
768 | /* TLB refill */ | |
769 | cvmx_l2c_lock_mem_region(ebase, 0x100); | |
770 | #endif | |
771 | #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION | |
772 | /* General exception */ | |
773 | cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80); | |
774 | #endif | |
775 | #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT | |
776 | /* Interrupt handler */ | |
777 | cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80); | |
778 | #endif | |
779 | #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT | |
780 | cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100); | |
781 | cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80); | |
782 | #endif | |
783 | #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY | |
784 | cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480); | |
785 | #endif | |
786 | } | |
787 | #endif | |
788 | ||
5b3b1688 DD |
789 | octeon_check_cpu_bist(); |
790 | ||
791 | octeon_uart = octeon_get_boot_uart(); | |
792 | ||
5b3b1688 DD |
793 | #ifdef CONFIG_SMP |
794 | octeon_write_lcd("LinuxSMP"); | |
795 | #else | |
796 | octeon_write_lcd("Linux"); | |
797 | #endif | |
798 | ||
70a26a21 DD |
799 | octeon_setup_delays(); |
800 | ||
5b3b1688 DD |
801 | /* |
802 | * BIST should always be enabled when doing a soft reset. L2 | |
803 | * Cache locking for instance is not cleared unless BIST is | |
804 | * enabled. Unfortunately due to a chip errata G-200 for | |
805 | * Cn38XX and CN31XX, BIST msut be disabled on these parts. | |
806 | */ | |
807 | if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) || | |
808 | OCTEON_IS_MODEL(OCTEON_CN31XX)) | |
809 | cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0); | |
810 | else | |
811 | cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1); | |
812 | ||
813 | /* Default to 64MB in the simulator to speed things up */ | |
814 | if (octeon_is_simulation()) | |
815 | MAX_MEMORY = 64ull << 20; | |
816 | ||
abe77f90 RB |
817 | arg = strstr(arcs_cmdline, "mem="); |
818 | if (arg) { | |
819 | MAX_MEMORY = memparse(arg + 4, &p); | |
820 | if (MAX_MEMORY == 0) | |
821 | MAX_MEMORY = 32ull << 30; | |
822 | if (*p == '@') | |
823 | RESERVE_LOW_MEM = memparse(p + 1, &p); | |
824 | } | |
825 | ||
5b3b1688 DD |
826 | arcs_cmdline[0] = 0; |
827 | argc = octeon_boot_desc_ptr->argc; | |
828 | for (i = 0; i < argc; i++) { | |
829 | const char *arg = | |
830 | cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]); | |
831 | if ((strncmp(arg, "MEM=", 4) == 0) || | |
832 | (strncmp(arg, "mem=", 4) == 0)) { | |
abe77f90 | 833 | MAX_MEMORY = memparse(arg + 4, &p); |
5b3b1688 DD |
834 | if (MAX_MEMORY == 0) |
835 | MAX_MEMORY = 32ull << 30; | |
abe77f90 RB |
836 | if (*p == '@') |
837 | RESERVE_LOW_MEM = memparse(p + 1, &p); | |
abe77f90 RB |
838 | #ifdef CONFIG_KEXEC |
839 | } else if (strncmp(arg, "crashkernel=", 12) == 0) { | |
840 | crashk_size = memparse(arg+12, &p); | |
841 | if (*p == '@') | |
842 | crashk_base = memparse(p+1, &p); | |
843 | strcat(arcs_cmdline, " "); | |
844 | strcat(arcs_cmdline, arg); | |
845 | /* | |
846 | * To do: switch parsing to new style, something like: | |
847 | * parse_crashkernel(arg, sysinfo->system_dram_size, | |
70342287 | 848 | * &crashk_size, &crashk_base); |
abe77f90 | 849 | */ |
5b3b1688 DD |
850 | #endif |
851 | } else if (strlen(arcs_cmdline) + strlen(arg) + 1 < | |
852 | sizeof(arcs_cmdline) - 1) { | |
853 | strcat(arcs_cmdline, " "); | |
854 | strcat(arcs_cmdline, arg); | |
855 | } | |
856 | } | |
857 | ||
858 | if (strstr(arcs_cmdline, "console=") == NULL) { | |
5b3b1688 DD |
859 | #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL |
860 | strcat(arcs_cmdline, " console=ttyS0,115200"); | |
861 | #else | |
862 | if (octeon_uart == 1) | |
863 | strcat(arcs_cmdline, " console=ttyS1,115200"); | |
864 | else | |
865 | strcat(arcs_cmdline, " console=ttyS0,115200"); | |
5b3b1688 DD |
866 | #endif |
867 | } | |
868 | ||
5b3b1688 DD |
869 | mips_hpt_frequency = octeon_get_clock_rate(); |
870 | ||
871 | octeon_init_cvmcount(); | |
872 | ||
873 | _machine_restart = octeon_restart; | |
874 | _machine_halt = octeon_halt; | |
875 | ||
abe77f90 RB |
876 | #ifdef CONFIG_KEXEC |
877 | _machine_kexec_shutdown = octeon_shutdown; | |
878 | _machine_crash_shutdown = octeon_crash_shutdown; | |
879 | _machine_kexec_prepare = octeon_kexec_prepare; | |
880 | #endif | |
881 | ||
5b3b1688 DD |
882 | octeon_user_io_init(); |
883 | register_smp_ops(&octeon_smp_ops); | |
884 | } | |
885 | ||
2b5987ab | 886 | /* Exclude a single page from the regions obtained in plat_mem_setup. */ |
abe77f90 | 887 | #ifndef CONFIG_CRASH_DUMP |
2b5987ab DD |
888 | static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size) |
889 | { | |
890 | if (addr > *mem && addr < *mem + *size) { | |
891 | u64 inc = addr - *mem; | |
892 | add_memory_region(*mem, inc, BOOT_MEM_RAM); | |
893 | *mem += inc; | |
894 | *size -= inc; | |
895 | } | |
896 | ||
897 | if (addr == *mem && *size > PAGE_SIZE) { | |
898 | *mem += PAGE_SIZE; | |
899 | *size -= PAGE_SIZE; | |
900 | } | |
901 | } | |
abe77f90 | 902 | #endif /* CONFIG_CRASH_DUMP */ |
2b5987ab | 903 | |
5b3b1688 DD |
904 | void __init plat_mem_setup(void) |
905 | { | |
906 | uint64_t mem_alloc_size; | |
907 | uint64_t total; | |
abe77f90 RB |
908 | uint64_t crashk_end; |
909 | #ifndef CONFIG_CRASH_DUMP | |
5b3b1688 | 910 | int64_t memory; |
abe77f90 RB |
911 | uint64_t kernel_start; |
912 | uint64_t kernel_size; | |
913 | #endif | |
5b3b1688 DD |
914 | |
915 | total = 0; | |
abe77f90 | 916 | crashk_end = 0; |
5b3b1688 | 917 | |
5b3b1688 DD |
918 | /* |
919 | * The Mips memory init uses the first memory location for | |
920 | * some memory vectors. When SPARSEMEM is in use, it doesn't | |
921 | * verify that the size is big enough for the final | |
922 | * vectors. Making the smallest chuck 4MB seems to be enough | |
25985edc | 923 | * to consistently work. |
5b3b1688 DD |
924 | */ |
925 | mem_alloc_size = 4 << 20; | |
926 | if (mem_alloc_size > MAX_MEMORY) | |
927 | mem_alloc_size = MAX_MEMORY; | |
928 | ||
abe77f90 RB |
929 | /* Crashkernel ignores bootmem list. It relies on mem=X@Y option */ |
930 | #ifdef CONFIG_CRASH_DUMP | |
931 | add_memory_region(RESERVE_LOW_MEM, MAX_MEMORY, BOOT_MEM_RAM); | |
932 | total += MAX_MEMORY; | |
933 | #else | |
934 | #ifdef CONFIG_KEXEC | |
935 | if (crashk_size > 0) { | |
936 | add_memory_region(crashk_base, crashk_size, BOOT_MEM_RAM); | |
937 | crashk_end = crashk_base + crashk_size; | |
938 | } | |
939 | #endif | |
5b3b1688 DD |
940 | /* |
941 | * When allocating memory, we want incrementing addresses from | |
942 | * bootmem_alloc so the code in add_memory_region can merge | |
943 | * regions next to each other. | |
944 | */ | |
945 | cvmx_bootmem_lock(); | |
946 | while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX) | |
947 | && (total < MAX_MEMORY)) { | |
5b3b1688 | 948 | memory = cvmx_bootmem_phy_alloc(mem_alloc_size, |
66803dd9 | 949 | __pa_symbol(&_end), -1, |
5b3b1688 DD |
950 | 0x100000, |
951 | CVMX_BOOTMEM_FLAG_NO_LOCKING); | |
5b3b1688 | 952 | if (memory >= 0) { |
2b5987ab | 953 | u64 size = mem_alloc_size; |
abe77f90 RB |
954 | #ifdef CONFIG_KEXEC |
955 | uint64_t end; | |
956 | #endif | |
2b5987ab DD |
957 | |
958 | /* | |
959 | * exclude a page at the beginning and end of | |
960 | * the 256MB PCIe 'hole' so the kernel will not | |
961 | * try to allocate multi-page buffers that | |
962 | * span the discontinuity. | |
963 | */ | |
964 | memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE, | |
965 | &memory, &size); | |
966 | memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE + | |
967 | CVMX_PCIE_BAR1_PHYS_SIZE, | |
968 | &memory, &size); | |
abe77f90 RB |
969 | #ifdef CONFIG_KEXEC |
970 | end = memory + mem_alloc_size; | |
2b5987ab | 971 | |
5b3b1688 | 972 | /* |
abe77f90 RB |
973 | * This function automatically merges address regions |
974 | * next to each other if they are received in | |
975 | * incrementing order | |
5b3b1688 | 976 | */ |
abe77f90 RB |
977 | if (memory < crashk_base && end > crashk_end) { |
978 | /* region is fully in */ | |
979 | add_memory_region(memory, | |
980 | crashk_base - memory, | |
981 | BOOT_MEM_RAM); | |
982 | total += crashk_base - memory; | |
983 | add_memory_region(crashk_end, | |
984 | end - crashk_end, | |
985 | BOOT_MEM_RAM); | |
986 | total += end - crashk_end; | |
987 | continue; | |
988 | } | |
989 | ||
990 | if (memory >= crashk_base && end <= crashk_end) | |
991 | /* | |
992 | * Entire memory region is within the new | |
993 | * kernel's memory, ignore it. | |
994 | */ | |
995 | continue; | |
996 | ||
997 | if (memory > crashk_base && memory < crashk_end && | |
998 | end > crashk_end) { | |
999 | /* | |
1000 | * Overlap with the beginning of the region, | |
1001 | * reserve the beginning. | |
1002 | */ | |
1003 | mem_alloc_size -= crashk_end - memory; | |
1004 | memory = crashk_end; | |
1005 | } else if (memory < crashk_base && end > crashk_base && | |
1006 | end < crashk_end) | |
1007 | /* | |
1008 | * Overlap with the beginning of the region, | |
1009 | * chop of end. | |
1010 | */ | |
1011 | mem_alloc_size -= end - crashk_base; | |
1012 | #endif | |
1013 | add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM); | |
5b3b1688 | 1014 | total += mem_alloc_size; |
abe77f90 RB |
1015 | /* Recovering mem_alloc_size */ |
1016 | mem_alloc_size = 4 << 20; | |
5b3b1688 DD |
1017 | } else { |
1018 | break; | |
1019 | } | |
1020 | } | |
1021 | cvmx_bootmem_unlock(); | |
abe77f90 RB |
1022 | /* Add the memory region for the kernel. */ |
1023 | kernel_start = (unsigned long) _text; | |
d949b4fe | 1024 | kernel_size = _end - _text; |
abe77f90 RB |
1025 | |
1026 | /* Adjust for physical offset. */ | |
1027 | kernel_start &= ~0xffffffff80000000ULL; | |
1028 | add_memory_region(kernel_start, kernel_size, BOOT_MEM_RAM); | |
1029 | #endif /* CONFIG_CRASH_DUMP */ | |
5b3b1688 DD |
1030 | |
1031 | #ifdef CONFIG_CAVIUM_RESERVE32 | |
1032 | /* | |
1033 | * Now that we've allocated the kernel memory it is safe to | |
1034 | * free the reserved region. We free it here so that builtin | |
1035 | * drivers can use the memory. | |
1036 | */ | |
1037 | if (octeon_reserve32_memory) | |
1038 | cvmx_bootmem_free_named("CAVIUM_RESERVE32"); | |
1039 | #endif /* CONFIG_CAVIUM_RESERVE32 */ | |
1040 | ||
1041 | if (total == 0) | |
1042 | panic("Unable to allocate memory from " | |
f7777dcc | 1043 | "cvmx_bootmem_phy_alloc"); |
5b3b1688 DD |
1044 | } |
1045 | ||
ea435464 | 1046 | /* |
70342287 | 1047 | * Emit one character to the boot UART. Exported for use by the |
ea435464 DD |
1048 | * watchdog timer. |
1049 | */ | |
5b3b1688 DD |
1050 | int prom_putchar(char c) |
1051 | { | |
1052 | uint64_t lsrval; | |
1053 | ||
1054 | /* Spin until there is room */ | |
1055 | do { | |
1056 | lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart)); | |
1057 | } while ((lsrval & 0x20) == 0); | |
1058 | ||
1059 | /* Write the byte */ | |
606c958e | 1060 | cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull); |
5b3b1688 DD |
1061 | return 1; |
1062 | } | |
ea435464 | 1063 | EXPORT_SYMBOL(prom_putchar); |
5b3b1688 | 1064 | |
aa816c1b | 1065 | void __init prom_free_prom_memory(void) |
5b3b1688 | 1066 | { |
e3d0ead5 | 1067 | if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR) { |
c9941158 DD |
1068 | /* Check for presence of Core-14449 fix. */ |
1069 | u32 insn; | |
1070 | u32 *foo; | |
1071 | ||
1072 | foo = &insn; | |
1073 | ||
1074 | asm volatile("# before" : : : "memory"); | |
1075 | prefetch(foo); | |
1076 | asm volatile( | |
1077 | ".set push\n\t" | |
1078 | ".set noreorder\n\t" | |
1079 | "bal 1f\n\t" | |
1080 | "nop\n" | |
1081 | "1:\tlw %0,-12($31)\n\t" | |
1082 | ".set pop\n\t" | |
1083 | : "=r" (insn) : : "$31", "memory"); | |
1084 | ||
1085 | if ((insn >> 26) != 0x33) | |
ab75dc02 | 1086 | panic("No PREF instruction at Core-14449 probe point."); |
c9941158 DD |
1087 | |
1088 | if (((insn >> 16) & 0x1f) != 28) | |
e3d0ead5 DD |
1089 | panic("OCTEON II DCache prefetch workaround not in place (%04x).\n" |
1090 | "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", | |
1091 | insn); | |
c9941158 | 1092 | } |
5b3b1688 | 1093 | } |
7ed18152 DD |
1094 | |
1095 | int octeon_prune_device_tree(void); | |
1096 | ||
651d19fb | 1097 | extern const char __appended_dtb; |
7ed18152 | 1098 | extern const char __dtb_octeon_3xxx_begin; |
7ed18152 | 1099 | extern const char __dtb_octeon_68xx_begin; |
7ed18152 DD |
1100 | void __init device_tree_init(void) |
1101 | { | |
8c97cec9 | 1102 | const void *fdt; |
7ed18152 DD |
1103 | bool do_prune; |
1104 | ||
651d19fb AK |
1105 | #ifdef CONFIG_MIPS_ELF_APPENDED_DTB |
1106 | if (!fdt_check_header(&__appended_dtb)) { | |
1107 | fdt = &__appended_dtb; | |
1108 | do_prune = false; | |
1109 | pr_info("Using appended Device Tree.\n"); | |
1110 | } else | |
1111 | #endif | |
7ed18152 DD |
1112 | if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) { |
1113 | fdt = phys_to_virt(octeon_bootinfo->fdt_addr); | |
1114 | if (fdt_check_header(fdt)) | |
1115 | panic("Corrupt Device Tree passed to kernel."); | |
7ed18152 | 1116 | do_prune = false; |
651d19fb | 1117 | pr_info("Using passed Device Tree.\n"); |
7ed18152 | 1118 | } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) { |
8c97cec9 | 1119 | fdt = &__dtb_octeon_68xx_begin; |
7ed18152 DD |
1120 | do_prune = true; |
1121 | } else { | |
8c97cec9 | 1122 | fdt = &__dtb_octeon_3xxx_begin; |
7ed18152 DD |
1123 | do_prune = true; |
1124 | } | |
1125 | ||
8c97cec9 | 1126 | initial_boot_params = (void *)fdt; |
7ed18152 DD |
1127 | |
1128 | if (do_prune) { | |
1129 | octeon_prune_device_tree(); | |
1130 | pr_info("Using internal Device Tree.\n"); | |
7ed18152 | 1131 | } |
8c97cec9 | 1132 | unflatten_and_copy_device_tree(); |
7ed18152 | 1133 | } |
f65aad41 | 1134 | |
e1ced097 DD |
1135 | static int __initdata disable_octeon_edac_p; |
1136 | ||
1137 | static int __init disable_octeon_edac(char *str) | |
1138 | { | |
1139 | disable_octeon_edac_p = 1; | |
1140 | return 0; | |
1141 | } | |
1142 | early_param("disable_octeon_edac", disable_octeon_edac); | |
1143 | ||
f65aad41 | 1144 | static char *edac_device_names[] = { |
e1ced097 DD |
1145 | "octeon_l2c_edac", |
1146 | "octeon_pc_edac", | |
f65aad41 RB |
1147 | }; |
1148 | ||
1149 | static int __init edac_devinit(void) | |
1150 | { | |
1151 | struct platform_device *dev; | |
1152 | int i, err = 0; | |
e1ced097 | 1153 | int num_lmc; |
f65aad41 RB |
1154 | char *name; |
1155 | ||
e1ced097 DD |
1156 | if (disable_octeon_edac_p) |
1157 | return 0; | |
1158 | ||
f65aad41 RB |
1159 | for (i = 0; i < ARRAY_SIZE(edac_device_names); i++) { |
1160 | name = edac_device_names[i]; | |
1161 | dev = platform_device_register_simple(name, -1, NULL, 0); | |
1162 | if (IS_ERR(dev)) { | |
6774def6 | 1163 | pr_err("Registration of %s failed!\n", name); |
f65aad41 RB |
1164 | err = PTR_ERR(dev); |
1165 | } | |
1166 | } | |
1167 | ||
e1ced097 DD |
1168 | num_lmc = OCTEON_IS_MODEL(OCTEON_CN68XX) ? 4 : |
1169 | (OCTEON_IS_MODEL(OCTEON_CN56XX) ? 2 : 1); | |
1170 | for (i = 0; i < num_lmc; i++) { | |
1171 | dev = platform_device_register_simple("octeon_lmc_edac", | |
1172 | i, NULL, 0); | |
1173 | if (IS_ERR(dev)) { | |
6774def6 | 1174 | pr_err("Registration of octeon_lmc_edac %d failed!\n", i); |
e1ced097 DD |
1175 | err = PTR_ERR(dev); |
1176 | } | |
1177 | } | |
1178 | ||
f65aad41 RB |
1179 | return err; |
1180 | } | |
f65aad41 | 1181 | device_initcall(edac_devinit); |
d8b74276 AK |
1182 | |
1183 | static void __initdata *octeon_dummy_iospace; | |
1184 | ||
1185 | static int __init octeon_no_pci_init(void) | |
1186 | { | |
1187 | /* | |
1188 | * Initially assume there is no PCI. The PCI/PCIe platform code will | |
1189 | * later re-initialize these to correct values if they are present. | |
1190 | */ | |
1191 | octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT); | |
1192 | set_io_port_base((unsigned long)octeon_dummy_iospace); | |
1193 | ioport_resource.start = MAX_RESOURCE; | |
1194 | ioport_resource.end = 0; | |
1195 | return 0; | |
1196 | } | |
1197 | core_initcall(octeon_no_pci_init); | |
1198 | ||
1199 | static int __init octeon_no_pci_release(void) | |
1200 | { | |
1201 | /* | |
1202 | * Release the allocated memory if a real IO space is there. | |
1203 | */ | |
1204 | if ((unsigned long)octeon_dummy_iospace != mips_io_port_base) | |
1205 | vfree(octeon_dummy_iospace); | |
1206 | return 0; | |
1207 | } | |
1208 | late_initcall(octeon_no_pci_release); |