projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 69c75fb4 | 1 | /* |
| 69c75fb4 MR |
2 | * Bus error event handling code for 5000-series systems equipped |
| 3 | * with parity error detection logic, i.e. DECstation/DECsystem | |
| 4 | * 5000/120, /125, /133 (KN02-BA), 5000/150 (KN04-BA) and Personal | |
| 5 | * DECstation/DECsystem 5000/20, /25, /33 (KN02-CA), 5000/50 | |
| 6 | * (KN04-CA) systems. | |
| 7 | * | |
| 8 | * Copyright (c) 2005 Maciej W. Rozycki | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or | |
| 11 | * modify it under the terms of the GNU General Public License | |
| 12 | * as published by the Free Software Foundation; either version | |
| 13 | * 2 of the License, or (at your option) any later version. | |
| 14 | */ | |
| 15 | ||
| 16 | #include <linux/init.h> | |
| 17 | #include <linux/interrupt.h> | |
| 18 | #include <linux/kernel.h> | |
| 19 | #include <linux/types.h> | |
| 20 | ||
| a5fc9c0b | 21 | #include <asm/addrspace.h> |
| 6dab2f45 RB |
22 | #include <asm/irq_regs.h> |
| 23 | #include <asm/ptrace.h> | |
| 69c75fb4 MR |
24 | #include <asm/traps.h> |
| 25 | ||
| 26 | #include <asm/dec/kn02ca.h> | |
| 27 | #include <asm/dec/kn02xa.h> | |
| 28 | #include <asm/dec/kn05.h> | |
| 29 | ||
| 30 | static inline void dec_kn02xa_be_ack(void) | |
| 31 | { | |
| a5fc9c0b MR |
32 | volatile u32 *mer = (void *)CKSEG1ADDR(KN02XA_MER); |
| 33 | volatile u32 *mem_intr = (void *)CKSEG1ADDR(KN02XA_MEM_INTR); | |
| 69c75fb4 MR |
34 | |
| 35 | *mer = KN02CA_MER_INTR; /* Clear errors; keep the ARC IRQ. */ | |
| 36 | *mem_intr = 0; /* Any write clears the bus IRQ. */ | |
| 37 | iob(); | |
| 38 | } | |
| 39 | ||
| 40 | static int dec_kn02xa_be_backend(struct pt_regs *regs, int is_fixup, | |
| 41 | int invoker) | |
| 42 | { | |
| a5fc9c0b MR |
43 | volatile u32 *kn02xa_mer = (void *)CKSEG1ADDR(KN02XA_MER); |
| 44 | volatile u32 *kn02xa_ear = (void *)CKSEG1ADDR(KN02XA_EAR); | |
| 69c75fb4 MR |
45 | |
| 46 | static const char excstr[] = "exception"; | |
| 47 | static const char intstr[] = "interrupt"; | |
| 48 | static const char cpustr[] = "CPU"; | |
| 49 | static const char mreadstr[] = "memory read"; | |
| 50 | static const char readstr[] = "read"; | |
| 51 | static const char writestr[] = "write"; | |
| 52 | static const char timestr[] = "timeout"; | |
| 53 | static const char paritystr[] = "parity error"; | |
| 54 | static const char lanestat[][4] = { " OK", "BAD" }; | |
| 55 | ||
| 56 | const char *kind, *agent, *cycle, *event; | |
| 57 | unsigned long address; | |
| 58 | ||
| 59 | u32 mer = *kn02xa_mer; | |
| 60 | u32 ear = *kn02xa_ear; | |
| 61 | int action = MIPS_BE_FATAL; | |
| 62 | ||
| 63 | /* Ack ASAP, so that any subsequent errors get caught. */ | |
| 64 | dec_kn02xa_be_ack(); | |
| 65 | ||
| 66 | kind = invoker ? intstr : excstr; | |
| 67 | ||
| 68 | /* No DMA errors? */ | |
| 69 | agent = cpustr; | |
| 70 | ||
| 71 | address = ear & KN02XA_EAR_ADDRESS; | |
| 72 | ||
| 73 | /* Low 256MB is decoded as memory, high -- as TC. */ | |
| 74 | if (address < 0x10000000) { | |
| 75 | cycle = mreadstr; | |
| 76 | event = paritystr; | |
| 77 | } else { | |
| 78 | cycle = invoker ? writestr : readstr; | |
| 79 | event = timestr; | |
| 80 | } | |
| 81 | ||
| 82 | if (is_fixup) | |
| 83 | action = MIPS_BE_FIXUP; | |
| 84 | ||
| 85 | if (action != MIPS_BE_FIXUP) | |
| 86 | printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n", | |
| 87 | kind, agent, cycle, event, address); | |
| 88 | ||
| 89 | if (action != MIPS_BE_FIXUP && address < 0x10000000) | |
| 90 | printk(KERN_ALERT " Byte lane status %#3x -- " | |
| 91 | "#3: %s, #2: %s, #1: %s, #0: %s\n", | |
| 92 | (mer & KN02XA_MER_BYTERR) >> 8, | |
| 93 | lanestat[(mer & KN02XA_MER_BYTERR_3) != 0], | |
| 94 | lanestat[(mer & KN02XA_MER_BYTERR_2) != 0], | |
| 95 | lanestat[(mer & KN02XA_MER_BYTERR_1) != 0], | |
| 96 | lanestat[(mer & KN02XA_MER_BYTERR_0) != 0]); | |
| 97 | ||
| 98 | return action; | |
| 99 | } | |
| 100 | ||
| 101 | int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup) | |
| 102 | { | |
| 103 | return dec_kn02xa_be_backend(regs, is_fixup, 0); | |
| 104 | } | |
| 105 | ||
| 6dab2f45 | 106 | irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id) |
| 69c75fb4 | 107 | { |
| 6dab2f45 | 108 | struct pt_regs *regs = get_irq_regs(); |
| 69c75fb4 MR |
109 | int action = dec_kn02xa_be_backend(regs, 0, 1); |
| 110 | ||
| 111 | if (action == MIPS_BE_DISCARD) | |
| 112 | return IRQ_HANDLED; | |
| 113 | ||
| 114 | /* | |
| 115 | * FIXME: Find the affected processes and kill them, otherwise | |
| 116 | * we must die. | |
| 117 | * | |
| 118 | * The interrupt is asynchronously delivered thus EPC and RA | |
| 119 | * may be irrelevant, but are printed for a reference. | |
| 120 | */ | |
| 121 | printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n", | |
| 122 | regs->cp0_epc, regs->regs[31]); | |
| 123 | die("Unrecoverable bus error", regs); | |
| 124 | } | |
| 125 | ||
| 126 | ||
| 127 | void __init dec_kn02xa_be_init(void) | |
| 128 | { | |
| a5fc9c0b | 129 | volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR); |
| 69c75fb4 MR |
130 | |
| 131 | /* For KN04 we need to make sure EE (?) is enabled in the MB. */ | |
| 10cc3529 | 132 | if (current_cpu_type() == CPU_R4000SC) |
| 69c75fb4 MR |
133 | *mbcs |= KN4K_MB_CSR_EE; |
| 134 | fast_iob(); | |
| 135 | ||
| 136 | /* Clear any leftover errors from the firmware. */ | |
| 137 | dec_kn02xa_be_ack(); | |
| 138 | } |