[deliverable/linux.git] / arch / mips / include / asm / asmmacro.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2003 Ralf Baechle
 */
#ifndef _ASM_ASMMACRO_H
#define _ASM_ASMMACRO_H

#include <asm/hazards.h>
#include <asm/asm-offsets.h>
#include <asm/msa.h>

#ifdef CONFIG_32BIT
#include <asm/asmmacro-32.h>
#endif
#ifdef CONFIG_64BIT
#include <asm/asmmacro-64.h>
#endif

/*
 * Helper macros for generating raw instruction encodings.
 */
#ifdef CONFIG_CPU_MICROMIPS
	.macro	insn32_if_mm enc
	.insn
	.hword ((\enc) >> 16)
	.hword ((\enc) & 0xffff)
	.endm

	.macro	insn_if_mips enc
	.endm
#else
	.macro	insn32_if_mm enc
	.endm

	.macro	insn_if_mips enc
	.insn
	.word (\enc)
	.endm
#endif

#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
	.macro	local_irq_enable reg=t0
	ei
	irq_enable_hazard
	.endm

	.macro	local_irq_disable reg=t0
	di
	irq_disable_hazard
	.endm
#else
	.macro	local_irq_enable reg=t0
	mfc0	\reg, CP0_STATUS
	ori	\reg, \reg, 1
	mtc0	\reg, CP0_STATUS
	irq_enable_hazard
	.endm

	.macro	local_irq_disable reg=t0
#ifdef CONFIG_PREEMPT
	lw      \reg, TI_PRE_COUNT($28)
	addi    \reg, \reg, 1
	sw      \reg, TI_PRE_COUNT($28)
#endif
	mfc0	\reg, CP0_STATUS
	ori	\reg, \reg, 1
	xori	\reg, \reg, 1
	mtc0	\reg, CP0_STATUS
	irq_disable_hazard
#ifdef CONFIG_PREEMPT
	lw      \reg, TI_PRE_COUNT($28)
	addi    \reg, \reg, -1
	sw      \reg, TI_PRE_COUNT($28)
#endif
	.endm
#endif /* CONFIG_CPU_MIPSR2 */

	.macro	fpu_save_16even thread tmp=t0
	.set	push
	SET_HARDFLOAT
	cfc1	\tmp, fcr31
	sdc1	$f0,  THREAD_FPR0(\thread)
	sdc1	$f2,  THREAD_FPR2(\thread)
	sdc1	$f4,  THREAD_FPR4(\thread)
	sdc1	$f6,  THREAD_FPR6(\thread)
	sdc1	$f8,  THREAD_FPR8(\thread)
	sdc1	$f10, THREAD_FPR10(\thread)
	sdc1	$f12, THREAD_FPR12(\thread)
	sdc1	$f14, THREAD_FPR14(\thread)
	sdc1	$f16, THREAD_FPR16(\thread)
	sdc1	$f18, THREAD_FPR18(\thread)
	sdc1	$f20, THREAD_FPR20(\thread)
	sdc1	$f22, THREAD_FPR22(\thread)
	sdc1	$f24, THREAD_FPR24(\thread)
	sdc1	$f26, THREAD_FPR26(\thread)
	sdc1	$f28, THREAD_FPR28(\thread)
	sdc1	$f30, THREAD_FPR30(\thread)
	sw	\tmp, THREAD_FCR31(\thread)
	.set	pop
	.endm

	.macro	fpu_save_16odd thread
	.set	push
	.set	mips64r2
	SET_HARDFLOAT
	sdc1	$f1,  THREAD_FPR1(\thread)
	sdc1	$f3,  THREAD_FPR3(\thread)
	sdc1	$f5,  THREAD_FPR5(\thread)
	sdc1	$f7,  THREAD_FPR7(\thread)
	sdc1	$f9,  THREAD_FPR9(\thread)
	sdc1	$f11, THREAD_FPR11(\thread)
	sdc1	$f13, THREAD_FPR13(\thread)
	sdc1	$f15, THREAD_FPR15(\thread)
	sdc1	$f17, THREAD_FPR17(\thread)
	sdc1	$f19, THREAD_FPR19(\thread)
	sdc1	$f21, THREAD_FPR21(\thread)
	sdc1	$f23, THREAD_FPR23(\thread)
	sdc1	$f25, THREAD_FPR25(\thread)
	sdc1	$f27, THREAD_FPR27(\thread)
	sdc1	$f29, THREAD_FPR29(\thread)
	sdc1	$f31, THREAD_FPR31(\thread)
	.set	pop
	.endm

	.macro	fpu_save_double thread status tmp
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
		defined(CONFIG_CPU_MIPS32_R6)
	sll	\tmp, \status, 5
	bgez	\tmp, 10f
	fpu_save_16odd \thread
10:
#endif
	fpu_save_16even \thread \tmp
	.endm

	.macro	fpu_restore_16even thread tmp=t0
	.set	push
	SET_HARDFLOAT
	lw	\tmp, THREAD_FCR31(\thread)
	ldc1	$f0,  THREAD_FPR0(\thread)
	ldc1	$f2,  THREAD_FPR2(\thread)
	ldc1	$f4,  THREAD_FPR4(\thread)
	ldc1	$f6,  THREAD_FPR6(\thread)
	ldc1	$f8,  THREAD_FPR8(\thread)
	ldc1	$f10, THREAD_FPR10(\thread)
	ldc1	$f12, THREAD_FPR12(\thread)
	ldc1	$f14, THREAD_FPR14(\thread)
	ldc1	$f16, THREAD_FPR16(\thread)
	ldc1	$f18, THREAD_FPR18(\thread)
	ldc1	$f20, THREAD_FPR20(\thread)
	ldc1	$f22, THREAD_FPR22(\thread)
	ldc1	$f24, THREAD_FPR24(\thread)
	ldc1	$f26, THREAD_FPR26(\thread)
	ldc1	$f28, THREAD_FPR28(\thread)
	ldc1	$f30, THREAD_FPR30(\thread)
	ctc1	\tmp, fcr31
	.endm

	.macro	fpu_restore_16odd thread
	.set	push
	.set	mips64r2
	SET_HARDFLOAT
	ldc1	$f1,  THREAD_FPR1(\thread)
	ldc1	$f3,  THREAD_FPR3(\thread)
	ldc1	$f5,  THREAD_FPR5(\thread)
	ldc1	$f7,  THREAD_FPR7(\thread)
	ldc1	$f9,  THREAD_FPR9(\thread)
	ldc1	$f11, THREAD_FPR11(\thread)
	ldc1	$f13, THREAD_FPR13(\thread)
	ldc1	$f15, THREAD_FPR15(\thread)
	ldc1	$f17, THREAD_FPR17(\thread)
	ldc1	$f19, THREAD_FPR19(\thread)
	ldc1	$f21, THREAD_FPR21(\thread)
	ldc1	$f23, THREAD_FPR23(\thread)
	ldc1	$f25, THREAD_FPR25(\thread)
	ldc1	$f27, THREAD_FPR27(\thread)
	ldc1	$f29, THREAD_FPR29(\thread)
	ldc1	$f31, THREAD_FPR31(\thread)
	.set	pop
	.endm

	.macro	fpu_restore_double thread status tmp
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
		defined(CONFIG_CPU_MIPS32_R6)
	sll	\tmp, \status, 5
	bgez	\tmp, 10f				# 16 register mode?

	fpu_restore_16odd \thread
10:
#endif
	fpu_restore_16even \thread \tmp
	.endm

#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
	.macro	_EXT	rd, rs, p, s
	ext	\rd, \rs, \p, \s
	.endm
#else /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */
	.macro	_EXT	rd, rs, p, s
	srl	\rd, \rs, \p
	andi	\rd, \rd, (1 << \s) - 1
	.endm
#endif /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */

/*
 * Temporary until all gas have MT ASE support
 */
	.macro	DMT	reg=0
	.word	0x41600bc1 | (\reg << 16)
	.endm

	.macro	EMT	reg=0
	.word	0x41600be1 | (\reg << 16)
	.endm

	.macro	DVPE	reg=0
	.word	0x41600001 | (\reg << 16)
	.endm

	.macro	EVPE	reg=0
	.word	0x41600021 | (\reg << 16)
	.endm

	.macro	MFTR	rt=0, rd=0, u=0, sel=0
	 .word	0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
	.endm

	.macro	MTTR	rt=0, rd=0, u=0, sel=0
	 .word	0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
	.endm

#ifdef TOOLCHAIN_SUPPORTS_MSA
/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
#undef fp

	.macro	_cfcmsa	rd, cs
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	cfcmsa	\rd, $\cs
	.set	pop
	.endm

	.macro	_ctcmsa	cd, rs
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	ctcmsa	$\cd, \rs
	.set	pop
	.endm

	.macro	ld_b	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	ld.b	$w\wd, \off(\base)
	.set	pop
	.endm

	.macro	ld_h	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	ld.h	$w\wd, \off(\base)
	.set	pop
	.endm

	.macro	ld_w	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	ld.w	$w\wd, \off(\base)
	.set	pop
	.endm

	.macro	ld_d	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	ld.d	$w\wd, \off(\base)
	.set	pop
	.endm

	.macro	st_b	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	st.b	$w\wd, \off(\base)
	.set	pop
	.endm

	.macro	st_h	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	st.h	$w\wd, \off(\base)
	.set	pop
	.endm

	.macro	st_w	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	st.w	$w\wd, \off(\base)
	.set	pop
	.endm

	.macro	st_d	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	st.d	$w\wd, \off(\base)
	.set	pop
	.endm

	.macro	copy_s_w	ws, n
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	copy_s.w $1, $w\ws[\n]
	.set	pop
	.endm

	.macro	copy_s_d	ws, n
	.set	push
	.set	mips64r2
	.set	fp=64
	.set	msa
	copy_s.d $1, $w\ws[\n]
	.set	pop
	.endm

	.macro	insert_w	wd, n
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	insert.w $w\wd[\n], $1
	.set	pop
	.endm

	.macro	insert_d	wd, n
	.set	push
	.set	mips64r2
	.set	fp=64
	.set	msa
	insert.d $w\wd[\n], $1
	.set	pop
	.endm
#else

	/*
	 * Temporary until all toolchains in use include MSA support.
	 */
	.macro	_cfcmsa	rd, cs
	.set	push
	.set	noat
	SET_HARDFLOAT
	insn_if_mips 0x787e0059 | (\cs << 11)
	insn32_if_mm 0x587e0056 | (\cs << 11)
	move	\rd, $1
	.set	pop
	.endm

	.macro	_ctcmsa	cd, rs
	.set	push
	.set	noat
	SET_HARDFLOAT
	move	$1, \rs
	insn_if_mips 0x783e0819 | (\cd << 6)
	insn32_if_mm 0x583e0816 | (\cd << 6)
	.set	pop
	.endm

	.macro	ld_b	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	insn_if_mips 0x78000820 | (\wd << 6)
	insn32_if_mm 0x58000807 | (\wd << 6)
	.set	pop
	.endm

	.macro	ld_h	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	insn_if_mips 0x78000821 | (\wd << 6)
	insn32_if_mm 0x58000817 | (\wd << 6)
	.set	pop
	.endm

	.macro	ld_w	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	insn_if_mips 0x78000822 | (\wd << 6)
	insn32_if_mm 0x58000827 | (\wd << 6)
	.set	pop
	.endm

	.macro	ld_d	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	insn_if_mips 0x78000823 | (\wd << 6)
	insn32_if_mm 0x58000837 | (\wd << 6)
	.set	pop
	.endm

	.macro	st_b	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	insn_if_mips 0x78000824 | (\wd << 6)
	insn32_if_mm 0x5800080f | (\wd << 6)
	.set	pop
	.endm

	.macro	st_h	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	insn_if_mips 0x78000825 | (\wd << 6)
	insn32_if_mm 0x5800081f | (\wd << 6)
	.set	pop
	.endm

	.macro	st_w	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	insn_if_mips 0x78000826 | (\wd << 6)
	insn32_if_mm 0x5800082f | (\wd << 6)
	.set	pop
	.endm

	.macro	st_d	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	insn_if_mips 0x78000827 | (\wd << 6)
	insn32_if_mm 0x5800083f | (\wd << 6)
	.set	pop
	.endm

	.macro	copy_s_w	ws, n
	.set	push
	.set	noat
	SET_HARDFLOAT
	insn_if_mips 0x78b00059 | (\n << 16) | (\ws << 11)
	insn32_if_mm 0x58b00056 | (\n << 16) | (\ws << 11)
	.set	pop
	.endm

	.macro	copy_s_d	ws, n
	.set	push
	.set	noat
	SET_HARDFLOAT
	insn_if_mips 0x78b80059 | (\n << 16) | (\ws << 11)
	insn32_if_mm 0x58b80056 | (\n << 16) | (\ws << 11)
	.set	pop
	.endm

	.macro	insert_w	wd, n
	.set	push
	.set	noat
	SET_HARDFLOAT
	insn_if_mips 0x79300819 | (\n << 16) | (\wd << 6)
	insn32_if_mm 0x59300816 | (\n << 16) | (\wd << 6)
	.set	pop
	.endm

	.macro	insert_d	wd, n
	.set	push
	.set	noat
	SET_HARDFLOAT
	insn_if_mips 0x79380819 | (\n << 16) | (\wd << 6)
	insn32_if_mm 0x59380816 | (\n << 16) | (\wd << 6)
	.set	pop
	.endm
#endif

#ifdef TOOLCHAIN_SUPPORTS_MSA
#define FPR_BASE_OFFS	THREAD_FPR0
#define FPR_BASE	$1
#else
#define FPR_BASE_OFFS	0
#define FPR_BASE	\thread
#endif

	.macro	msa_save_all	thread
	.set	push
	.set	noat
#ifdef TOOLCHAIN_SUPPORTS_MSA
	PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
#endif
	st_d	 0, THREAD_FPR0  - FPR_BASE_OFFS, FPR_BASE
	st_d	 1, THREAD_FPR1  - FPR_BASE_OFFS, FPR_BASE
	st_d	 2, THREAD_FPR2  - FPR_BASE_OFFS, FPR_BASE
	st_d	 3, THREAD_FPR3  - FPR_BASE_OFFS, FPR_BASE
	st_d	 4, THREAD_FPR4  - FPR_BASE_OFFS, FPR_BASE
	st_d	 5, THREAD_FPR5  - FPR_BASE_OFFS, FPR_BASE
	st_d	 6, THREAD_FPR6  - FPR_BASE_OFFS, FPR_BASE
	st_d	 7, THREAD_FPR7  - FPR_BASE_OFFS, FPR_BASE
	st_d	 8, THREAD_FPR8  - FPR_BASE_OFFS, FPR_BASE
	st_d	 9, THREAD_FPR9  - FPR_BASE_OFFS, FPR_BASE
	st_d	10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
	st_d	11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
	st_d	12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
	st_d	13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
	st_d	14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
	st_d	15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
	st_d	16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
	st_d	17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
	st_d	18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
	st_d	19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
	st_d	20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
	st_d	21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
	st_d	22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
	st_d	23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
	st_d	24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
	st_d	25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
	st_d	26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
	st_d	27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
	st_d	28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
	st_d	29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
	st_d	30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
	st_d	31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
	SET_HARDFLOAT
	_cfcmsa	$1, MSA_CSR
	sw	$1, THREAD_MSA_CSR(\thread)
	.set	pop
	.endm

	.macro	msa_restore_all	thread
	.set	push
	.set	noat
	SET_HARDFLOAT
	lw	$1, THREAD_MSA_CSR(\thread)
	_ctcmsa	MSA_CSR, $1
#ifdef TOOLCHAIN_SUPPORTS_MSA
	PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
#endif
	ld_d	 0, THREAD_FPR0  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 1, THREAD_FPR1  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 2, THREAD_FPR2  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 3, THREAD_FPR3  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 4, THREAD_FPR4  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 5, THREAD_FPR5  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 6, THREAD_FPR6  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 7, THREAD_FPR7  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 8, THREAD_FPR8  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 9, THREAD_FPR9  - FPR_BASE_OFFS, FPR_BASE
	ld_d	10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
	ld_d	11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
	ld_d	12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
	ld_d	13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
	ld_d	14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
	ld_d	15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
	ld_d	16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
	ld_d	17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
	ld_d	18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
	ld_d	19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
	ld_d	20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
	ld_d	21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
	ld_d	22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
	ld_d	23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
	ld_d	24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
	ld_d	25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
	ld_d	26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
	ld_d	27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
	ld_d	28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
	ld_d	29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
	ld_d	30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
	ld_d	31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
	.set pop
	.endm

#undef FPR_BASE_OFFS
#undef FPR_BASE

	.macro	msa_init_upper wd
#ifdef CONFIG_64BIT
	insert_d \wd, 1
#else
	insert_w \wd, 2
	insert_w \wd, 3
#endif
	.endm

	.macro	msa_init_all_upper
	.set	push
	.set	noat
	SET_HARDFLOAT
	not	$1, zero
	msa_init_upper	0
	msa_init_upper	1
	msa_init_upper	2
	msa_init_upper	3
	msa_init_upper	4
	msa_init_upper	5
	msa_init_upper	6
	msa_init_upper	7
	msa_init_upper	8
	msa_init_upper	9
	msa_init_upper	10
	msa_init_upper	11
	msa_init_upper	12
	msa_init_upper	13
	msa_init_upper	14
	msa_init_upper	15
	msa_init_upper	16
	msa_init_upper	17
	msa_init_upper	18
	msa_init_upper	19
	msa_init_upper	20
	msa_init_upper	21
	msa_init_upper	22
	msa_init_upper	23
	msa_init_upper	24
	msa_init_upper	25
	msa_init_upper	26
	msa_init_upper	27
	msa_init_upper	28
	msa_init_upper	29
	msa_init_upper	30
	msa_init_upper	31
	.set	pop
	.endm

#endif /* _ASM_ASMMACRO_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2003 Ralf Baechle
	7	*/
	8	#ifndef _ASM_ASMMACRO_H
	9	#define _ASM_ASMMACRO_H
42a3b4f2	10
1da177e4	11	#include <asm/hazards.h>
71ca7588	12	#include <asm/asm-offsets.h>
f7a46fa7	13	#include <asm/msa.h>
42a3b4f2	14
875d43e7	15	#ifdef CONFIG_32BIT
1da177e4 LT	16	#include <asm/asmmacro-32.h>
1da177e4 LT	17	#endif
875d43e7	18	#ifdef CONFIG_64BIT
1da177e4 LT	19	#include <asm/asmmacro-64.h>
1da177e4 LT	20	#endif
41c594ab	21
6e1b29c3 JH	22	/*
	23	* Helper macros for generating raw instruction encodings.
	24	*/
	25	#ifdef CONFIG_CPU_MICROMIPS
	26	.macro insn32_if_mm enc
	27	.insn
	28	.hword ((\enc) >> 16)
	29	.hword ((\enc) & 0xffff)
	30	.endm
	31
	32	.macro insn_if_mips enc
	33	.endm
	34	#else
	35	.macro insn32_if_mm enc
	36	.endm
	37
	38	.macro insn_if_mips enc
	39	.insn
	40	.word (\enc)
	41	.endm
	42	#endif
	43
226da55f	44	#if defined(CONFIG_CPU_MIPSR2) \|\| defined(CONFIG_CPU_MIPSR6)
b6354db5 DD	45	.macro local_irq_enable reg=t0
	46	ei
	47	irq_enable_hazard
	48	.endm
	49
	50	.macro local_irq_disable reg=t0
	51	di
	52	irq_disable_hazard
	53	.endm
41c594ab	54	#else
1da177e4 LT	55	.macro local_irq_enable reg=t0
	56	mfc0 \reg, CP0_STATUS
	57	ori \reg, \reg, 1
	58	mtc0 \reg, CP0_STATUS
	59	irq_enable_hazard
	60	.endm
	61
	62	.macro local_irq_disable reg=t0
71ca7588 JQ	63	#ifdef CONFIG_PREEMPT
	64	lw \reg, TI_PRE_COUNT($28)
	65	addi \reg, \reg, 1
	66	sw \reg, TI_PRE_COUNT($28)
	67	#endif
1da177e4 LT	68	mfc0 \reg, CP0_STATUS
	69	ori \reg, \reg, 1
	70	xori \reg, \reg, 1
	71	mtc0 \reg, CP0_STATUS
	72	irq_disable_hazard
71ca7588 JQ	73	#ifdef CONFIG_PREEMPT
	74	lw \reg, TI_PRE_COUNT($28)
	75	addi \reg, \reg, -1
	76	sw \reg, TI_PRE_COUNT($28)
	77	#endif
1da177e4	78	.endm
b633648c	79	#endif /* CONFIG_CPU_MIPSR2 */
1da177e4	80
597ce172	81	.macro fpu_save_16even thread tmp=t0
842dfc11 ML	82	.set push
842dfc11 ML	83	SET_HARDFLOAT
597ce172	84	cfc1 \tmp, fcr31
466aec5f JH	85	sdc1 $f0, THREAD_FPR0(\thread)
	86	sdc1 $f2, THREAD_FPR2(\thread)
	87	sdc1 $f4, THREAD_FPR4(\thread)
	88	sdc1 $f6, THREAD_FPR6(\thread)
	89	sdc1 $f8, THREAD_FPR8(\thread)
	90	sdc1 $f10, THREAD_FPR10(\thread)
	91	sdc1 $f12, THREAD_FPR12(\thread)
	92	sdc1 $f14, THREAD_FPR14(\thread)
	93	sdc1 $f16, THREAD_FPR16(\thread)
	94	sdc1 $f18, THREAD_FPR18(\thread)
	95	sdc1 $f20, THREAD_FPR20(\thread)
	96	sdc1 $f22, THREAD_FPR22(\thread)
	97	sdc1 $f24, THREAD_FPR24(\thread)
	98	sdc1 $f26, THREAD_FPR26(\thread)
	99	sdc1 $f28, THREAD_FPR28(\thread)
	100	sdc1 $f30, THREAD_FPR30(\thread)
597ce172	101	sw \tmp, THREAD_FCR31(\thread)
842dfc11	102	.set pop
597ce172 PB	103	.endm
	104
	105	.macro fpu_save_16odd thread
	106	.set push
	107	.set mips64r2
842dfc11	108	SET_HARDFLOAT
466aec5f JH	109	sdc1 $f1, THREAD_FPR1(\thread)
	110	sdc1 $f3, THREAD_FPR3(\thread)
	111	sdc1 $f5, THREAD_FPR5(\thread)
	112	sdc1 $f7, THREAD_FPR7(\thread)
	113	sdc1 $f9, THREAD_FPR9(\thread)
	114	sdc1 $f11, THREAD_FPR11(\thread)
	115	sdc1 $f13, THREAD_FPR13(\thread)
	116	sdc1 $f15, THREAD_FPR15(\thread)
	117	sdc1 $f17, THREAD_FPR17(\thread)
	118	sdc1 $f19, THREAD_FPR19(\thread)
	119	sdc1 $f21, THREAD_FPR21(\thread)
	120	sdc1 $f23, THREAD_FPR23(\thread)
	121	sdc1 $f25, THREAD_FPR25(\thread)
	122	sdc1 $f27, THREAD_FPR27(\thread)
	123	sdc1 $f29, THREAD_FPR29(\thread)
	124	sdc1 $f31, THREAD_FPR31(\thread)
597ce172 PB	125	.set pop
	126	.endm
	127
	128	.macro fpu_save_double thread status tmp
207083b1 LY	129	#if defined(CONFIG_64BIT) \|\| defined(CONFIG_CPU_MIPS32_R2) \|\| \
207083b1 LY	130	defined(CONFIG_CPU_MIPS32_R6)
597ce172 PB	131	sll \tmp, \status, 5
	132	bgez \tmp, 10f
	133	fpu_save_16odd \thread
	134	10:
	135	#endif
	136	fpu_save_16even \thread \tmp
	137	.endm
	138
	139	.macro fpu_restore_16even thread tmp=t0
842dfc11 ML	140	.set push
842dfc11 ML	141	SET_HARDFLOAT
597ce172	142	lw \tmp, THREAD_FCR31(\thread)
466aec5f JH	143	ldc1 $f0, THREAD_FPR0(\thread)
	144	ldc1 $f2, THREAD_FPR2(\thread)
	145	ldc1 $f4, THREAD_FPR4(\thread)
	146	ldc1 $f6, THREAD_FPR6(\thread)
	147	ldc1 $f8, THREAD_FPR8(\thread)
	148	ldc1 $f10, THREAD_FPR10(\thread)
	149	ldc1 $f12, THREAD_FPR12(\thread)
	150	ldc1 $f14, THREAD_FPR14(\thread)
	151	ldc1 $f16, THREAD_FPR16(\thread)
	152	ldc1 $f18, THREAD_FPR18(\thread)
	153	ldc1 $f20, THREAD_FPR20(\thread)
	154	ldc1 $f22, THREAD_FPR22(\thread)
	155	ldc1 $f24, THREAD_FPR24(\thread)
	156	ldc1 $f26, THREAD_FPR26(\thread)
	157	ldc1 $f28, THREAD_FPR28(\thread)
	158	ldc1 $f30, THREAD_FPR30(\thread)
597ce172 PB	159	ctc1 \tmp, fcr31
	160	.endm
	161
	162	.macro fpu_restore_16odd thread
	163	.set push
	164	.set mips64r2
842dfc11	165	SET_HARDFLOAT
466aec5f JH	166	ldc1 $f1, THREAD_FPR1(\thread)
	167	ldc1 $f3, THREAD_FPR3(\thread)
	168	ldc1 $f5, THREAD_FPR5(\thread)
	169	ldc1 $f7, THREAD_FPR7(\thread)
	170	ldc1 $f9, THREAD_FPR9(\thread)
	171	ldc1 $f11, THREAD_FPR11(\thread)
	172	ldc1 $f13, THREAD_FPR13(\thread)
	173	ldc1 $f15, THREAD_FPR15(\thread)
	174	ldc1 $f17, THREAD_FPR17(\thread)
	175	ldc1 $f19, THREAD_FPR19(\thread)
	176	ldc1 $f21, THREAD_FPR21(\thread)
	177	ldc1 $f23, THREAD_FPR23(\thread)
	178	ldc1 $f25, THREAD_FPR25(\thread)
	179	ldc1 $f27, THREAD_FPR27(\thread)
	180	ldc1 $f29, THREAD_FPR29(\thread)
	181	ldc1 $f31, THREAD_FPR31(\thread)
597ce172 PB	182	.set pop
	183	.endm
	184
	185	.macro fpu_restore_double thread status tmp
207083b1 LY	186	#if defined(CONFIG_64BIT) \|\| defined(CONFIG_CPU_MIPS32_R2) \|\| \
207083b1 LY	187	defined(CONFIG_CPU_MIPS32_R6)
597ce172 PB	188	sll \tmp, \status, 5
	189	bgez \tmp, 10f # 16 register mode?
	190
	191	fpu_restore_16odd \thread
	192	10:
	193	#endif
	194	fpu_restore_16even \thread \tmp
	195	.endm
	196
207083b1	197	#if defined(CONFIG_CPU_MIPSR2) \|\| defined(CONFIG_CPU_MIPSR6)
1d688087 PB	198	.macro _EXT rd, rs, p, s
	199	ext \rd, \rs, \p, \s
	200	.endm
207083b1	201	#else /* !CONFIG_CPU_MIPSR2 \|\| !CONFIG_CPU_MIPSR6 */
1d688087 PB	202	.macro _EXT rd, rs, p, s
	203	srl \rd, \rs, \p
	204	andi \rd, \rd, (1 << \s) - 1
	205	.endm
207083b1	206	#endif /* !CONFIG_CPU_MIPSR2 \|\| !CONFIG_CPU_MIPSR6 */
1d688087	207
41c594ab RB	208	/*
	209	* Temporary until all gas have MT ASE support
	210	*/
	211	.macro DMT reg=0
49a89efb	212	.word 0x41600bc1 \| (\reg << 16)
41c594ab RB	213	.endm
	214
	215	.macro EMT reg=0
49a89efb	216	.word 0x41600be1 \| (\reg << 16)
41c594ab RB	217	.endm
	218
	219	.macro DVPE reg=0
49a89efb	220	.word 0x41600001 \| (\reg << 16)
41c594ab RB	221	.endm
	222
	223	.macro EVPE reg=0
49a89efb	224	.word 0x41600021 \| (\reg << 16)
41c594ab RB	225	.endm
	226
	227	.macro MFTR rt=0, rd=0, u=0, sel=0
49a89efb	228	.word 0x41000000 \| (\rt << 16) \| (\rd << 11) \| (\u << 5) \| (\sel)
41c594ab RB	229	.endm
	230
	231	.macro MTTR rt=0, rd=0, u=0, sel=0
49a89efb	232	.word 0x41800000 \| (\rt << 16) \| (\rd << 11) \| (\u << 5) \| (\sel)
41c594ab RB	233	.endm
41c594ab RB	234
7f65afb9	235	#ifdef TOOLCHAIN_SUPPORTS_MSA
2bd7bc25 MC	236	/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
	237	#undef fp
	238
e1bebbab PB	239	.macro _cfcmsa rd, cs
	240	.set push
	241	.set mips32r2
2bd7bc25	242	.set fp=64
e1bebbab PB	243	.set msa
	244	cfcmsa \rd, $\cs
	245	.set pop
	246	.endm
	247
	248	.macro _ctcmsa cd, rs
	249	.set push
	250	.set mips32r2
2bd7bc25	251	.set fp=64
e1bebbab PB	252	.set msa
	253	ctcmsa $\cd, \rs
	254	.set pop
	255	.endm
	256
6b35e114 PB	257	.macro ld_b wd, off, base
	258	.set push
	259	.set mips32r2
92e9953c	260	.set fp=64
6b35e114 PB	261	.set msa
	262	ld.b $w\wd, \off(\base)
	263	.set pop
	264	.endm
	265
	266	.macro ld_h wd, off, base
	267	.set push
	268	.set mips32r2
92e9953c	269	.set fp=64
6b35e114 PB	270	.set msa
	271	ld.h $w\wd, \off(\base)
	272	.set pop
	273	.endm
	274
	275	.macro ld_w wd, off, base
	276	.set push
	277	.set mips32r2
92e9953c	278	.set fp=64
6b35e114 PB	279	.set msa
	280	ld.w $w\wd, \off(\base)
	281	.set pop
	282	.endm
	283
7f65afb9 PB	284	.macro ld_d wd, off, base
	285	.set push
	286	.set mips32r2
2bd7bc25	287	.set fp=64
7f65afb9 PB	288	.set msa
	289	ld.d $w\wd, \off(\base)
	290	.set pop
	291	.endm
	292
6b35e114 PB	293	.macro st_b wd, off, base
	294	.set push
	295	.set mips32r2
92e9953c	296	.set fp=64
6b35e114 PB	297	.set msa
	298	st.b $w\wd, \off(\base)
	299	.set pop
	300	.endm
	301
	302	.macro st_h wd, off, base
	303	.set push
	304	.set mips32r2
92e9953c	305	.set fp=64
6b35e114 PB	306	.set msa
	307	st.h $w\wd, \off(\base)
	308	.set pop
	309	.endm
	310
	311	.macro st_w wd, off, base
	312	.set push
	313	.set mips32r2
92e9953c	314	.set fp=64
6b35e114 PB	315	.set msa
	316	st.w $w\wd, \off(\base)
	317	.set pop
	318	.endm
	319
7f65afb9 PB	320	.macro st_d wd, off, base
	321	.set push
	322	.set mips32r2
2bd7bc25	323	.set fp=64
7f65afb9 PB	324	.set msa
	325	st.d $w\wd, \off(\base)
	326	.set pop
	327	.endm
	328
8a3c8b48	329	.macro copy_s_w ws, n
7f65afb9 PB	330	.set push
7f65afb9 PB	331	.set mips32r2
2bd7bc25	332	.set fp=64
7f65afb9	333	.set msa
8a3c8b48	334	copy_s.w $1, $w\ws[\n]
7f65afb9 PB	335	.set pop
	336	.endm
	337
8a3c8b48	338	.macro copy_s_d ws, n
7f65afb9 PB	339	.set push
7f65afb9 PB	340	.set mips64r2
2bd7bc25	341	.set fp=64
7f65afb9	342	.set msa
8a3c8b48	343	copy_s.d $1, $w\ws[\n]
7f65afb9 PB	344	.set pop
	345	.endm
	346
f23ce388	347	.macro insert_w wd, n
7f65afb9 PB	348	.set push
7f65afb9 PB	349	.set mips32r2
2bd7bc25	350	.set fp=64
7f65afb9	351	.set msa
f23ce388	352	insert.w $w\wd[\n], $1
7f65afb9 PB	353	.set pop
	354	.endm
	355
f23ce388	356	.macro insert_d wd, n
7f65afb9 PB	357	.set push
7f65afb9 PB	358	.set mips64r2
2bd7bc25	359	.set fp=64
7f65afb9	360	.set msa
f23ce388	361	insert.d $w\wd[\n], $1
7f65afb9 PB	362	.set pop
	363	.endm
	364	#else
d96cc3d1	365
7f65afb9 PB	366	/*
	367	* Temporary until all toolchains in use include MSA support.
	368	*/
e1bebbab	369	.macro _cfcmsa rd, cs
7f65afb9 PB	370	.set push
7f65afb9 PB	371	.set noat
842dfc11	372	SET_HARDFLOAT
6e1b29c3 JH	373	insn_if_mips 0x787e0059 \| (\cs << 11)
6e1b29c3 JH	374	insn32_if_mm 0x587e0056 \| (\cs << 11)
7f65afb9 PB	375	move \rd, $1
	376	.set pop
	377	.endm
	378
e1bebbab	379	.macro _ctcmsa cd, rs
7f65afb9 PB	380	.set push
7f65afb9 PB	381	.set noat
842dfc11	382	SET_HARDFLOAT
7f65afb9	383	move $1, \rs
6e1b29c3 JH	384	insn_if_mips 0x783e0819 \| (\cd << 6)
6e1b29c3 JH	385	insn32_if_mm 0x583e0816 \| (\cd << 6)
7f65afb9 PB	386	.set pop
	387	.endm
	388
6b35e114 PB	389	.macro ld_b wd, off, base
	390	.set push
	391	.set noat
	392	SET_HARDFLOAT
ea168857	393	PTR_ADDU $1, \base, \off
6e1b29c3 JH	394	insn_if_mips 0x78000820 \| (\wd << 6)
6e1b29c3 JH	395	insn32_if_mm 0x58000807 \| (\wd << 6)
6b35e114 PB	396	.set pop
	397	.endm
	398
	399	.macro ld_h wd, off, base
	400	.set push
	401	.set noat
	402	SET_HARDFLOAT
ea168857	403	PTR_ADDU $1, \base, \off
6e1b29c3 JH	404	insn_if_mips 0x78000821 \| (\wd << 6)
6e1b29c3 JH	405	insn32_if_mm 0x58000817 \| (\wd << 6)
6b35e114 PB	406	.set pop
	407	.endm
	408
	409	.macro ld_w wd, off, base
	410	.set push
	411	.set noat
	412	SET_HARDFLOAT
ea168857	413	PTR_ADDU $1, \base, \off
6e1b29c3 JH	414	insn_if_mips 0x78000822 \| (\wd << 6)
6e1b29c3 JH	415	insn32_if_mm 0x58000827 \| (\wd << 6)
6b35e114 PB	416	.set pop
	417	.endm
	418
7f65afb9 PB	419	.macro ld_d wd, off, base
	420	.set push
	421	.set noat
842dfc11	422	SET_HARDFLOAT
ea168857	423	PTR_ADDU $1, \base, \off
6e1b29c3 JH	424	insn_if_mips 0x78000823 \| (\wd << 6)
6e1b29c3 JH	425	insn32_if_mm 0x58000837 \| (\wd << 6)
7f65afb9 PB	426	.set pop
	427	.endm
	428
6b35e114 PB	429	.macro st_b wd, off, base
	430	.set push
	431	.set noat
	432	SET_HARDFLOAT
ea168857	433	PTR_ADDU $1, \base, \off
6e1b29c3 JH	434	insn_if_mips 0x78000824 \| (\wd << 6)
6e1b29c3 JH	435	insn32_if_mm 0x5800080f \| (\wd << 6)
6b35e114 PB	436	.set pop
	437	.endm
	438
	439	.macro st_h wd, off, base
	440	.set push
	441	.set noat
	442	SET_HARDFLOAT
ea168857	443	PTR_ADDU $1, \base, \off
6e1b29c3 JH	444	insn_if_mips 0x78000825 \| (\wd << 6)
6e1b29c3 JH	445	insn32_if_mm 0x5800081f \| (\wd << 6)
6b35e114 PB	446	.set pop
	447	.endm
	448
	449	.macro st_w wd, off, base
	450	.set push
	451	.set noat
	452	SET_HARDFLOAT
ea168857	453	PTR_ADDU $1, \base, \off
6e1b29c3 JH	454	insn_if_mips 0x78000826 \| (\wd << 6)
6e1b29c3 JH	455	insn32_if_mm 0x5800082f \| (\wd << 6)
6b35e114 PB	456	.set pop
	457	.endm
	458
7f65afb9 PB	459	.macro st_d wd, off, base
	460	.set push
	461	.set noat
842dfc11	462	SET_HARDFLOAT
ea168857	463	PTR_ADDU $1, \base, \off
6e1b29c3 JH	464	insn_if_mips 0x78000827 \| (\wd << 6)
6e1b29c3 JH	465	insn32_if_mm 0x5800083f \| (\wd << 6)
7f65afb9 PB	466	.set pop
	467	.endm
	468
8a3c8b48	469	.macro copy_s_w ws, n
7f65afb9 PB	470	.set push
7f65afb9 PB	471	.set noat
842dfc11	472	SET_HARDFLOAT
6e1b29c3 JH	473	insn_if_mips 0x78b00059 \| (\n << 16) \| (\ws << 11)
6e1b29c3 JH	474	insn32_if_mm 0x58b00056 \| (\n << 16) \| (\ws << 11)
7f65afb9 PB	475	.set pop
	476	.endm
	477
8a3c8b48	478	.macro copy_s_d ws, n
7f65afb9 PB	479	.set push
7f65afb9 PB	480	.set noat
842dfc11	481	SET_HARDFLOAT
6e1b29c3 JH	482	insn_if_mips 0x78b80059 \| (\n << 16) \| (\ws << 11)
6e1b29c3 JH	483	insn32_if_mm 0x58b80056 \| (\n << 16) \| (\ws << 11)
7f65afb9 PB	484	.set pop
	485	.endm
	486
f23ce388	487	.macro insert_w wd, n
7f65afb9 PB	488	.set push
7f65afb9 PB	489	.set noat
842dfc11	490	SET_HARDFLOAT
6e1b29c3 JH	491	insn_if_mips 0x79300819 \| (\n << 16) \| (\wd << 6)
6e1b29c3 JH	492	insn32_if_mm 0x59300816 \| (\n << 16) \| (\wd << 6)
7f65afb9 PB	493	.set pop
	494	.endm
	495
f23ce388	496	.macro insert_d wd, n
7f65afb9 PB	497	.set push
7f65afb9 PB	498	.set noat
842dfc11	499	SET_HARDFLOAT
6e1b29c3 JH	500	insn_if_mips 0x79380819 \| (\n << 16) \| (\wd << 6)
6e1b29c3 JH	501	insn32_if_mm 0x59380816 \| (\n << 16) \| (\wd << 6)
7f65afb9 PB	502	.set pop
	503	.endm
	504	#endif
	505
143e93d7 JH	506	#ifdef TOOLCHAIN_SUPPORTS_MSA
	507	#define FPR_BASE_OFFS THREAD_FPR0
	508	#define FPR_BASE $1
	509	#else
	510	#define FPR_BASE_OFFS 0
	511	#define FPR_BASE \thread
	512	#endif
	513
1db1af84	514	.macro msa_save_all thread
f7a46fa7 PB	515	.set push
f7a46fa7 PB	516	.set noat
143e93d7 JH	517	#ifdef TOOLCHAIN_SUPPORTS_MSA
	518	PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
	519	#endif
	520	st_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE
	521	st_d 1, THREAD_FPR1 - FPR_BASE_OFFS, FPR_BASE
	522	st_d 2, THREAD_FPR2 - FPR_BASE_OFFS, FPR_BASE
	523	st_d 3, THREAD_FPR3 - FPR_BASE_OFFS, FPR_BASE
	524	st_d 4, THREAD_FPR4 - FPR_BASE_OFFS, FPR_BASE
	525	st_d 5, THREAD_FPR5 - FPR_BASE_OFFS, FPR_BASE
	526	st_d 6, THREAD_FPR6 - FPR_BASE_OFFS, FPR_BASE
	527	st_d 7, THREAD_FPR7 - FPR_BASE_OFFS, FPR_BASE
	528	st_d 8, THREAD_FPR8 - FPR_BASE_OFFS, FPR_BASE
	529	st_d 9, THREAD_FPR9 - FPR_BASE_OFFS, FPR_BASE
	530	st_d 10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
	531	st_d 11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
	532	st_d 12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
	533	st_d 13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
	534	st_d 14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
	535	st_d 15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
	536	st_d 16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
	537	st_d 17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
	538	st_d 18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
	539	st_d 19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
	540	st_d 20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
	541	st_d 21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
	542	st_d 22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
	543	st_d 23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
	544	st_d 24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
	545	st_d 25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
	546	st_d 26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
	547	st_d 27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
	548	st_d 28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
	549	st_d 29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
	550	st_d 30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
	551	st_d 31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
842dfc11	552	SET_HARDFLOAT
e1bebbab	553	_cfcmsa $1, MSA_CSR
f7a46fa7 PB	554	sw $1, THREAD_MSA_CSR(\thread)
f7a46fa7 PB	555	.set pop
1db1af84 PB	556	.endm
	557
	558	.macro msa_restore_all thread
f7a46fa7 PB	559	.set push
f7a46fa7 PB	560	.set noat
842dfc11	561	SET_HARDFLOAT
f7a46fa7	562	lw $1, THREAD_MSA_CSR(\thread)
e1bebbab	563	_ctcmsa MSA_CSR, $1
143e93d7 JH	564	#ifdef TOOLCHAIN_SUPPORTS_MSA
	565	PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
	566	#endif
	567	ld_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE
	568	ld_d 1, THREAD_FPR1 - FPR_BASE_OFFS, FPR_BASE
	569	ld_d 2, THREAD_FPR2 - FPR_BASE_OFFS, FPR_BASE
	570	ld_d 3, THREAD_FPR3 - FPR_BASE_OFFS, FPR_BASE
	571	ld_d 4, THREAD_FPR4 - FPR_BASE_OFFS, FPR_BASE
	572	ld_d 5, THREAD_FPR5 - FPR_BASE_OFFS, FPR_BASE
	573	ld_d 6, THREAD_FPR6 - FPR_BASE_OFFS, FPR_BASE
	574	ld_d 7, THREAD_FPR7 - FPR_BASE_OFFS, FPR_BASE
	575	ld_d 8, THREAD_FPR8 - FPR_BASE_OFFS, FPR_BASE
	576	ld_d 9, THREAD_FPR9 - FPR_BASE_OFFS, FPR_BASE
	577	ld_d 10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
	578	ld_d 11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
	579	ld_d 12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
	580	ld_d 13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
	581	ld_d 14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
	582	ld_d 15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
	583	ld_d 16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
	584	ld_d 17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
	585	ld_d 18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
	586	ld_d 19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
	587	ld_d 20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
	588	ld_d 21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
	589	ld_d 22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
	590	ld_d 23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
	591	ld_d 24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
	592	ld_d 25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
	593	ld_d 26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
	594	ld_d 27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
	595	ld_d 28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
	596	ld_d 29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
	597	ld_d 30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
	598	ld_d 31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
	599	.set pop
	600	.endm
	601
	602	#undef FPR_BASE_OFFS
	603	#undef FPR_BASE
1db1af84	604
c9017757 PB	605	.macro msa_init_upper wd
	606	#ifdef CONFIG_64BIT
	607	insert_d \wd, 1
	608	#else
	609	insert_w \wd, 2
	610	insert_w \wd, 3
	611	#endif
c9017757 PB	612	.endm
	613
	614	.macro msa_init_all_upper
	615	.set push
	616	.set noat
842dfc11	617	SET_HARDFLOAT
c9017757 PB	618	not $1, zero
c9017757 PB	619	msa_init_upper 0
a3a49810 PB	620	msa_init_upper 1
	621	msa_init_upper 2
	622	msa_init_upper 3
	623	msa_init_upper 4
	624	msa_init_upper 5
	625	msa_init_upper 6
	626	msa_init_upper 7
	627	msa_init_upper 8
	628	msa_init_upper 9
	629	msa_init_upper 10
	630	msa_init_upper 11
	631	msa_init_upper 12
	632	msa_init_upper 13
	633	msa_init_upper 14
	634	msa_init_upper 15
	635	msa_init_upper 16
	636	msa_init_upper 17
	637	msa_init_upper 18
	638	msa_init_upper 19
	639	msa_init_upper 20
	640	msa_init_upper 21
	641	msa_init_upper 22
	642	msa_init_upper 23
	643	msa_init_upper 24
	644	msa_init_upper 25
	645	msa_init_upper 26
	646	msa_init_upper 27
	647	msa_init_upper 28
	648	msa_init_upper 29
	649	msa_init_upper 30
	650	msa_init_upper 31
c9017757 PB	651	.set pop
	652	.endm
	653
1da177e4	654	#endif /* _ASM_ASMMACRO_H */