[deliverable/linux.git] / arch / mips / include / asm / asmmacro.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2003 Ralf Baechle
 */
#ifndef _ASM_ASMMACRO_H
#define _ASM_ASMMACRO_H

#include <asm/hazards.h>
#include <asm/asm-offsets.h>
#include <asm/msa.h>

#ifdef CONFIG_32BIT
#include <asm/asmmacro-32.h>
#endif
#ifdef CONFIG_64BIT
#include <asm/asmmacro-64.h>
#endif

#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
	.macro	local_irq_enable reg=t0
	ei
	irq_enable_hazard
	.endm

	.macro	local_irq_disable reg=t0
	di
	irq_disable_hazard
	.endm
#else
	.macro	local_irq_enable reg=t0
	mfc0	\reg, CP0_STATUS
	ori	\reg, \reg, 1
	mtc0	\reg, CP0_STATUS
	irq_enable_hazard
	.endm

	.macro	local_irq_disable reg=t0
#ifdef CONFIG_PREEMPT
	lw      \reg, TI_PRE_COUNT($28)
	addi    \reg, \reg, 1
	sw      \reg, TI_PRE_COUNT($28)
#endif
	mfc0	\reg, CP0_STATUS
	ori	\reg, \reg, 1
	xori	\reg, \reg, 1
	mtc0	\reg, CP0_STATUS
	irq_disable_hazard
#ifdef CONFIG_PREEMPT
	lw      \reg, TI_PRE_COUNT($28)
	addi    \reg, \reg, -1
	sw      \reg, TI_PRE_COUNT($28)
#endif
	.endm
#endif /* CONFIG_CPU_MIPSR2 */

	.macro	fpu_save_16even thread tmp=t0
	.set	push
	SET_HARDFLOAT
	cfc1	\tmp, fcr31
	sdc1	$f0,  THREAD_FPR0(\thread)
	sdc1	$f2,  THREAD_FPR2(\thread)
	sdc1	$f4,  THREAD_FPR4(\thread)
	sdc1	$f6,  THREAD_FPR6(\thread)
	sdc1	$f8,  THREAD_FPR8(\thread)
	sdc1	$f10, THREAD_FPR10(\thread)
	sdc1	$f12, THREAD_FPR12(\thread)
	sdc1	$f14, THREAD_FPR14(\thread)
	sdc1	$f16, THREAD_FPR16(\thread)
	sdc1	$f18, THREAD_FPR18(\thread)
	sdc1	$f20, THREAD_FPR20(\thread)
	sdc1	$f22, THREAD_FPR22(\thread)
	sdc1	$f24, THREAD_FPR24(\thread)
	sdc1	$f26, THREAD_FPR26(\thread)
	sdc1	$f28, THREAD_FPR28(\thread)
	sdc1	$f30, THREAD_FPR30(\thread)
	sw	\tmp, THREAD_FCR31(\thread)
	.set	pop
	.endm

	.macro	fpu_save_16odd thread
	.set	push
	.set	mips64r2
	SET_HARDFLOAT
	sdc1	$f1,  THREAD_FPR1(\thread)
	sdc1	$f3,  THREAD_FPR3(\thread)
	sdc1	$f5,  THREAD_FPR5(\thread)
	sdc1	$f7,  THREAD_FPR7(\thread)
	sdc1	$f9,  THREAD_FPR9(\thread)
	sdc1	$f11, THREAD_FPR11(\thread)
	sdc1	$f13, THREAD_FPR13(\thread)
	sdc1	$f15, THREAD_FPR15(\thread)
	sdc1	$f17, THREAD_FPR17(\thread)
	sdc1	$f19, THREAD_FPR19(\thread)
	sdc1	$f21, THREAD_FPR21(\thread)
	sdc1	$f23, THREAD_FPR23(\thread)
	sdc1	$f25, THREAD_FPR25(\thread)
	sdc1	$f27, THREAD_FPR27(\thread)
	sdc1	$f29, THREAD_FPR29(\thread)
	sdc1	$f31, THREAD_FPR31(\thread)
	.set	pop
	.endm

	.macro	fpu_save_double thread status tmp
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
		defined(CONFIG_CPU_MIPS32_R6)
	sll	\tmp, \status, 5
	bgez	\tmp, 10f
	fpu_save_16odd \thread
10:
#endif
	fpu_save_16even \thread \tmp
	.endm

	.macro	fpu_restore_16even thread tmp=t0
	.set	push
	SET_HARDFLOAT
	lw	\tmp, THREAD_FCR31(\thread)
	ldc1	$f0,  THREAD_FPR0(\thread)
	ldc1	$f2,  THREAD_FPR2(\thread)
	ldc1	$f4,  THREAD_FPR4(\thread)
	ldc1	$f6,  THREAD_FPR6(\thread)
	ldc1	$f8,  THREAD_FPR8(\thread)
	ldc1	$f10, THREAD_FPR10(\thread)
	ldc1	$f12, THREAD_FPR12(\thread)
	ldc1	$f14, THREAD_FPR14(\thread)
	ldc1	$f16, THREAD_FPR16(\thread)
	ldc1	$f18, THREAD_FPR18(\thread)
	ldc1	$f20, THREAD_FPR20(\thread)
	ldc1	$f22, THREAD_FPR22(\thread)
	ldc1	$f24, THREAD_FPR24(\thread)
	ldc1	$f26, THREAD_FPR26(\thread)
	ldc1	$f28, THREAD_FPR28(\thread)
	ldc1	$f30, THREAD_FPR30(\thread)
	ctc1	\tmp, fcr31
	.endm

	.macro	fpu_restore_16odd thread
	.set	push
	.set	mips64r2
	SET_HARDFLOAT
	ldc1	$f1,  THREAD_FPR1(\thread)
	ldc1	$f3,  THREAD_FPR3(\thread)
	ldc1	$f5,  THREAD_FPR5(\thread)
	ldc1	$f7,  THREAD_FPR7(\thread)
	ldc1	$f9,  THREAD_FPR9(\thread)
	ldc1	$f11, THREAD_FPR11(\thread)
	ldc1	$f13, THREAD_FPR13(\thread)
	ldc1	$f15, THREAD_FPR15(\thread)
	ldc1	$f17, THREAD_FPR17(\thread)
	ldc1	$f19, THREAD_FPR19(\thread)
	ldc1	$f21, THREAD_FPR21(\thread)
	ldc1	$f23, THREAD_FPR23(\thread)
	ldc1	$f25, THREAD_FPR25(\thread)
	ldc1	$f27, THREAD_FPR27(\thread)
	ldc1	$f29, THREAD_FPR29(\thread)
	ldc1	$f31, THREAD_FPR31(\thread)
	.set	pop
	.endm

	.macro	fpu_restore_double thread status tmp
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
		defined(CONFIG_CPU_MIPS32_R6)
	sll	\tmp, \status, 5
	bgez	\tmp, 10f				# 16 register mode?

	fpu_restore_16odd \thread
10:
#endif
	fpu_restore_16even \thread \tmp
	.endm

#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
	.macro	_EXT	rd, rs, p, s
	ext	\rd, \rs, \p, \s
	.endm
#else /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */
	.macro	_EXT	rd, rs, p, s
	srl	\rd, \rs, \p
	andi	\rd, \rd, (1 << \s) - 1
	.endm
#endif /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */

/*
 * Temporary until all gas have MT ASE support
 */
	.macro	DMT	reg=0
	.word	0x41600bc1 | (\reg << 16)
	.endm

	.macro	EMT	reg=0
	.word	0x41600be1 | (\reg << 16)
	.endm

	.macro	DVPE	reg=0
	.word	0x41600001 | (\reg << 16)
	.endm

	.macro	EVPE	reg=0
	.word	0x41600021 | (\reg << 16)
	.endm

	.macro	MFTR	rt=0, rd=0, u=0, sel=0
	 .word	0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
	.endm

	.macro	MTTR	rt=0, rd=0, u=0, sel=0
	 .word	0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
	.endm

#ifdef TOOLCHAIN_SUPPORTS_MSA
/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
#undef fp

	.macro	_cfcmsa	rd, cs
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	cfcmsa	\rd, $\cs
	.set	pop
	.endm

	.macro	_ctcmsa	cd, rs
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	ctcmsa	$\cd, \rs
	.set	pop
	.endm

	.macro	ld_b	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	ld.b	$w\wd, \off(\base)
	.set	pop
	.endm

	.macro	ld_h	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	ld.h	$w\wd, \off(\base)
	.set	pop
	.endm

	.macro	ld_w	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	ld.w	$w\wd, \off(\base)
	.set	pop
	.endm

	.macro	ld_d	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	ld.d	$w\wd, \off(\base)
	.set	pop
	.endm

	.macro	st_b	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	st.b	$w\wd, \off(\base)
	.set	pop
	.endm

	.macro	st_h	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	st.h	$w\wd, \off(\base)
	.set	pop
	.endm

	.macro	st_w	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	st.w	$w\wd, \off(\base)
	.set	pop
	.endm

	.macro	st_d	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	st.d	$w\wd, \off(\base)
	.set	pop
	.endm

	.macro	copy_s_w	ws, n
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	copy_s.w $1, $w\ws[\n]
	.set	pop
	.endm

	.macro	copy_s_d	ws, n
	.set	push
	.set	mips64r2
	.set	fp=64
	.set	msa
	copy_s.d $1, $w\ws[\n]
	.set	pop
	.endm

	.macro	insert_w	wd, n
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	insert.w $w\wd[\n], $1
	.set	pop
	.endm

	.macro	insert_d	wd, n
	.set	push
	.set	mips64r2
	.set	fp=64
	.set	msa
	insert.d $w\wd[\n], $1
	.set	pop
	.endm
#else

#ifdef CONFIG_CPU_MICROMIPS
#define CFC_MSA_INSN		0x587e0056
#define CTC_MSA_INSN		0x583e0816
#define LDB_MSA_INSN		0x58000807
#define LDH_MSA_INSN		0x58000817
#define LDW_MSA_INSN		0x58000827
#define LDD_MSA_INSN		0x58000837
#define STB_MSA_INSN		0x5800080f
#define STH_MSA_INSN		0x5800081f
#define STW_MSA_INSN		0x5800082f
#define STD_MSA_INSN		0x5800083f
#define COPY_SW_MSA_INSN	0x58b00056
#define COPY_SD_MSA_INSN	0x58b80056
#define INSERT_W_MSA_INSN	0x59300816
#define INSERT_D_MSA_INSN	0x59380816
#else
#define CFC_MSA_INSN		0x787e0059
#define CTC_MSA_INSN		0x783e0819
#define LDB_MSA_INSN		0x78000820
#define LDH_MSA_INSN		0x78000821
#define LDW_MSA_INSN		0x78000822
#define LDD_MSA_INSN		0x78000823
#define STB_MSA_INSN		0x78000824
#define STH_MSA_INSN		0x78000825
#define STW_MSA_INSN		0x78000826
#define STD_MSA_INSN		0x78000827
#define COPY_SW_MSA_INSN	0x78b00059
#define COPY_SD_MSA_INSN	0x78b80059
#define INSERT_W_MSA_INSN	0x79300819
#define INSERT_D_MSA_INSN	0x79380819
#endif

	/*
	 * Temporary until all toolchains in use include MSA support.
	 */
	.macro	_cfcmsa	rd, cs
	.set	push
	.set	noat
	SET_HARDFLOAT
	.insn
	.word	CFC_MSA_INSN | (\cs << 11)
	move	\rd, $1
	.set	pop
	.endm

	.macro	_ctcmsa	cd, rs
	.set	push
	.set	noat
	SET_HARDFLOAT
	move	$1, \rs
	.word	CTC_MSA_INSN | (\cd << 6)
	.set	pop
	.endm

	.macro	ld_b	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	.word	LDB_MSA_INSN | (\wd << 6)
	.set	pop
	.endm

	.macro	ld_h	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	.word	LDH_MSA_INSN | (\wd << 6)
	.set	pop
	.endm

	.macro	ld_w	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	.word	LDW_MSA_INSN | (\wd << 6)
	.set	pop
	.endm

	.macro	ld_d	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	.word	LDD_MSA_INSN | (\wd << 6)
	.set	pop
	.endm

	.macro	st_b	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	.word	STB_MSA_INSN | (\wd << 6)
	.set	pop
	.endm

	.macro	st_h	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	.word	STH_MSA_INSN | (\wd << 6)
	.set	pop
	.endm

	.macro	st_w	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	.word	STW_MSA_INSN | (\wd << 6)
	.set	pop
	.endm

	.macro	st_d	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	.word	STD_MSA_INSN | (\wd << 6)
	.set	pop
	.endm

	.macro	copy_s_w	ws, n
	.set	push
	.set	noat
	SET_HARDFLOAT
	.insn
	.word	COPY_SW_MSA_INSN | (\n << 16) | (\ws << 11)
	.set	pop
	.endm

	.macro	copy_s_d	ws, n
	.set	push
	.set	noat
	SET_HARDFLOAT
	.insn
	.word	COPY_SD_MSA_INSN | (\n << 16) | (\ws << 11)
	.set	pop
	.endm

	.macro	insert_w	wd, n
	.set	push
	.set	noat
	SET_HARDFLOAT
	.word	INSERT_W_MSA_INSN | (\n << 16) | (\wd << 6)
	.set	pop
	.endm

	.macro	insert_d	wd, n
	.set	push
	.set	noat
	SET_HARDFLOAT
	.word	INSERT_D_MSA_INSN | (\n << 16) | (\wd << 6)
	.set	pop
	.endm
#endif

#ifdef TOOLCHAIN_SUPPORTS_MSA
#define FPR_BASE_OFFS	THREAD_FPR0
#define FPR_BASE	$1
#else
#define FPR_BASE_OFFS	0
#define FPR_BASE	\thread
#endif

	.macro	msa_save_all	thread
	.set	push
	.set	noat
#ifdef TOOLCHAIN_SUPPORTS_MSA
	PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
#endif
	st_d	 0, THREAD_FPR0  - FPR_BASE_OFFS, FPR_BASE
	st_d	 1, THREAD_FPR1  - FPR_BASE_OFFS, FPR_BASE
	st_d	 2, THREAD_FPR2  - FPR_BASE_OFFS, FPR_BASE
	st_d	 3, THREAD_FPR3  - FPR_BASE_OFFS, FPR_BASE
	st_d	 4, THREAD_FPR4  - FPR_BASE_OFFS, FPR_BASE
	st_d	 5, THREAD_FPR5  - FPR_BASE_OFFS, FPR_BASE
	st_d	 6, THREAD_FPR6  - FPR_BASE_OFFS, FPR_BASE
	st_d	 7, THREAD_FPR7  - FPR_BASE_OFFS, FPR_BASE
	st_d	 8, THREAD_FPR8  - FPR_BASE_OFFS, FPR_BASE
	st_d	 9, THREAD_FPR9  - FPR_BASE_OFFS, FPR_BASE
	st_d	10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
	st_d	11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
	st_d	12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
	st_d	13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
	st_d	14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
	st_d	15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
	st_d	16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
	st_d	17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
	st_d	18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
	st_d	19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
	st_d	20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
	st_d	21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
	st_d	22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
	st_d	23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
	st_d	24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
	st_d	25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
	st_d	26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
	st_d	27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
	st_d	28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
	st_d	29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
	st_d	30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
	st_d	31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
	SET_HARDFLOAT
	_cfcmsa	$1, MSA_CSR
	sw	$1, THREAD_MSA_CSR(\thread)
	.set	pop
	.endm

	.macro	msa_restore_all	thread
	.set	push
	.set	noat
	SET_HARDFLOAT
	lw	$1, THREAD_MSA_CSR(\thread)
	_ctcmsa	MSA_CSR, $1
#ifdef TOOLCHAIN_SUPPORTS_MSA
	PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
#endif
	ld_d	 0, THREAD_FPR0  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 1, THREAD_FPR1  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 2, THREAD_FPR2  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 3, THREAD_FPR3  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 4, THREAD_FPR4  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 5, THREAD_FPR5  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 6, THREAD_FPR6  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 7, THREAD_FPR7  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 8, THREAD_FPR8  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 9, THREAD_FPR9  - FPR_BASE_OFFS, FPR_BASE
	ld_d	10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
	ld_d	11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
	ld_d	12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
	ld_d	13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
	ld_d	14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
	ld_d	15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
	ld_d	16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
	ld_d	17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
	ld_d	18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
	ld_d	19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
	ld_d	20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
	ld_d	21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
	ld_d	22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
	ld_d	23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
	ld_d	24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
	ld_d	25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
	ld_d	26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
	ld_d	27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
	ld_d	28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
	ld_d	29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
	ld_d	30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
	ld_d	31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
	.set pop
	.endm

#undef FPR_BASE_OFFS
#undef FPR_BASE

	.macro	msa_init_upper wd
#ifdef CONFIG_64BIT
	insert_d \wd, 1
#else
	insert_w \wd, 2
	insert_w \wd, 3
#endif
	.endm

	.macro	msa_init_all_upper
	.set	push
	.set	noat
	SET_HARDFLOAT
	not	$1, zero
	msa_init_upper	0
	msa_init_upper	1
	msa_init_upper	2
	msa_init_upper	3
	msa_init_upper	4
	msa_init_upper	5
	msa_init_upper	6
	msa_init_upper	7
	msa_init_upper	8
	msa_init_upper	9
	msa_init_upper	10
	msa_init_upper	11
	msa_init_upper	12
	msa_init_upper	13
	msa_init_upper	14
	msa_init_upper	15
	msa_init_upper	16
	msa_init_upper	17
	msa_init_upper	18
	msa_init_upper	19
	msa_init_upper	20
	msa_init_upper	21
	msa_init_upper	22
	msa_init_upper	23
	msa_init_upper	24
	msa_init_upper	25
	msa_init_upper	26
	msa_init_upper	27
	msa_init_upper	28
	msa_init_upper	29
	msa_init_upper	30
	msa_init_upper	31
	.set	pop
	.endm

#endif /* _ASM_ASMMACRO_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2003 Ralf Baechle
	7	*/
	8	#ifndef _ASM_ASMMACRO_H
	9	#define _ASM_ASMMACRO_H
42a3b4f2	10
1da177e4	11	#include <asm/hazards.h>
71ca7588	12	#include <asm/asm-offsets.h>
f7a46fa7	13	#include <asm/msa.h>
42a3b4f2	14
875d43e7	15	#ifdef CONFIG_32BIT
1da177e4 LT	16	#include <asm/asmmacro-32.h>
1da177e4 LT	17	#endif
875d43e7	18	#ifdef CONFIG_64BIT
1da177e4 LT	19	#include <asm/asmmacro-64.h>
1da177e4 LT	20	#endif
41c594ab	21
226da55f	22	#if defined(CONFIG_CPU_MIPSR2) \|\| defined(CONFIG_CPU_MIPSR6)
b6354db5 DD	23	.macro local_irq_enable reg=t0
	24	ei
	25	irq_enable_hazard
	26	.endm
	27
	28	.macro local_irq_disable reg=t0
	29	di
	30	irq_disable_hazard
	31	.endm
41c594ab	32	#else
1da177e4 LT	33	.macro local_irq_enable reg=t0
	34	mfc0 \reg, CP0_STATUS
	35	ori \reg, \reg, 1
	36	mtc0 \reg, CP0_STATUS
	37	irq_enable_hazard
	38	.endm
	39
	40	.macro local_irq_disable reg=t0
71ca7588 JQ	41	#ifdef CONFIG_PREEMPT
	42	lw \reg, TI_PRE_COUNT($28)
	43	addi \reg, \reg, 1
	44	sw \reg, TI_PRE_COUNT($28)
	45	#endif
1da177e4 LT	46	mfc0 \reg, CP0_STATUS
	47	ori \reg, \reg, 1
	48	xori \reg, \reg, 1
	49	mtc0 \reg, CP0_STATUS
	50	irq_disable_hazard
71ca7588 JQ	51	#ifdef CONFIG_PREEMPT
	52	lw \reg, TI_PRE_COUNT($28)
	53	addi \reg, \reg, -1
	54	sw \reg, TI_PRE_COUNT($28)
	55	#endif
1da177e4	56	.endm
b633648c	57	#endif /* CONFIG_CPU_MIPSR2 */
1da177e4	58
597ce172	59	.macro fpu_save_16even thread tmp=t0
842dfc11 ML	60	.set push
842dfc11 ML	61	SET_HARDFLOAT
597ce172	62	cfc1 \tmp, fcr31
466aec5f JH	63	sdc1 $f0, THREAD_FPR0(\thread)
	64	sdc1 $f2, THREAD_FPR2(\thread)
	65	sdc1 $f4, THREAD_FPR4(\thread)
	66	sdc1 $f6, THREAD_FPR6(\thread)
	67	sdc1 $f8, THREAD_FPR8(\thread)
	68	sdc1 $f10, THREAD_FPR10(\thread)
	69	sdc1 $f12, THREAD_FPR12(\thread)
	70	sdc1 $f14, THREAD_FPR14(\thread)
	71	sdc1 $f16, THREAD_FPR16(\thread)
	72	sdc1 $f18, THREAD_FPR18(\thread)
	73	sdc1 $f20, THREAD_FPR20(\thread)
	74	sdc1 $f22, THREAD_FPR22(\thread)
	75	sdc1 $f24, THREAD_FPR24(\thread)
	76	sdc1 $f26, THREAD_FPR26(\thread)
	77	sdc1 $f28, THREAD_FPR28(\thread)
	78	sdc1 $f30, THREAD_FPR30(\thread)
597ce172	79	sw \tmp, THREAD_FCR31(\thread)
842dfc11	80	.set pop
597ce172 PB	81	.endm
	82
	83	.macro fpu_save_16odd thread
	84	.set push
	85	.set mips64r2
842dfc11	86	SET_HARDFLOAT
466aec5f JH	87	sdc1 $f1, THREAD_FPR1(\thread)
	88	sdc1 $f3, THREAD_FPR3(\thread)
	89	sdc1 $f5, THREAD_FPR5(\thread)
	90	sdc1 $f7, THREAD_FPR7(\thread)
	91	sdc1 $f9, THREAD_FPR9(\thread)
	92	sdc1 $f11, THREAD_FPR11(\thread)
	93	sdc1 $f13, THREAD_FPR13(\thread)
	94	sdc1 $f15, THREAD_FPR15(\thread)
	95	sdc1 $f17, THREAD_FPR17(\thread)
	96	sdc1 $f19, THREAD_FPR19(\thread)
	97	sdc1 $f21, THREAD_FPR21(\thread)
	98	sdc1 $f23, THREAD_FPR23(\thread)
	99	sdc1 $f25, THREAD_FPR25(\thread)
	100	sdc1 $f27, THREAD_FPR27(\thread)
	101	sdc1 $f29, THREAD_FPR29(\thread)
	102	sdc1 $f31, THREAD_FPR31(\thread)
597ce172 PB	103	.set pop
	104	.endm
	105
	106	.macro fpu_save_double thread status tmp
207083b1 LY	107	#if defined(CONFIG_64BIT) \|\| defined(CONFIG_CPU_MIPS32_R2) \|\| \
207083b1 LY	108	defined(CONFIG_CPU_MIPS32_R6)
597ce172 PB	109	sll \tmp, \status, 5
	110	bgez \tmp, 10f
	111	fpu_save_16odd \thread
	112	10:
	113	#endif
	114	fpu_save_16even \thread \tmp
	115	.endm
	116
	117	.macro fpu_restore_16even thread tmp=t0
842dfc11 ML	118	.set push
842dfc11 ML	119	SET_HARDFLOAT
597ce172	120	lw \tmp, THREAD_FCR31(\thread)
466aec5f JH	121	ldc1 $f0, THREAD_FPR0(\thread)
	122	ldc1 $f2, THREAD_FPR2(\thread)
	123	ldc1 $f4, THREAD_FPR4(\thread)
	124	ldc1 $f6, THREAD_FPR6(\thread)
	125	ldc1 $f8, THREAD_FPR8(\thread)
	126	ldc1 $f10, THREAD_FPR10(\thread)
	127	ldc1 $f12, THREAD_FPR12(\thread)
	128	ldc1 $f14, THREAD_FPR14(\thread)
	129	ldc1 $f16, THREAD_FPR16(\thread)
	130	ldc1 $f18, THREAD_FPR18(\thread)
	131	ldc1 $f20, THREAD_FPR20(\thread)
	132	ldc1 $f22, THREAD_FPR22(\thread)
	133	ldc1 $f24, THREAD_FPR24(\thread)
	134	ldc1 $f26, THREAD_FPR26(\thread)
	135	ldc1 $f28, THREAD_FPR28(\thread)
	136	ldc1 $f30, THREAD_FPR30(\thread)
597ce172 PB	137	ctc1 \tmp, fcr31
	138	.endm
	139
	140	.macro fpu_restore_16odd thread
	141	.set push
	142	.set mips64r2
842dfc11	143	SET_HARDFLOAT
466aec5f JH	144	ldc1 $f1, THREAD_FPR1(\thread)
	145	ldc1 $f3, THREAD_FPR3(\thread)
	146	ldc1 $f5, THREAD_FPR5(\thread)
	147	ldc1 $f7, THREAD_FPR7(\thread)
	148	ldc1 $f9, THREAD_FPR9(\thread)
	149	ldc1 $f11, THREAD_FPR11(\thread)
	150	ldc1 $f13, THREAD_FPR13(\thread)
	151	ldc1 $f15, THREAD_FPR15(\thread)
	152	ldc1 $f17, THREAD_FPR17(\thread)
	153	ldc1 $f19, THREAD_FPR19(\thread)
	154	ldc1 $f21, THREAD_FPR21(\thread)
	155	ldc1 $f23, THREAD_FPR23(\thread)
	156	ldc1 $f25, THREAD_FPR25(\thread)
	157	ldc1 $f27, THREAD_FPR27(\thread)
	158	ldc1 $f29, THREAD_FPR29(\thread)
	159	ldc1 $f31, THREAD_FPR31(\thread)
597ce172 PB	160	.set pop
	161	.endm
	162
	163	.macro fpu_restore_double thread status tmp
207083b1 LY	164	#if defined(CONFIG_64BIT) \|\| defined(CONFIG_CPU_MIPS32_R2) \|\| \
207083b1 LY	165	defined(CONFIG_CPU_MIPS32_R6)
597ce172 PB	166	sll \tmp, \status, 5
	167	bgez \tmp, 10f # 16 register mode?
	168
	169	fpu_restore_16odd \thread
	170	10:
	171	#endif
	172	fpu_restore_16even \thread \tmp
	173	.endm
	174
207083b1	175	#if defined(CONFIG_CPU_MIPSR2) \|\| defined(CONFIG_CPU_MIPSR6)
1d688087 PB	176	.macro _EXT rd, rs, p, s
	177	ext \rd, \rs, \p, \s
	178	.endm
207083b1	179	#else /* !CONFIG_CPU_MIPSR2 \|\| !CONFIG_CPU_MIPSR6 */
1d688087 PB	180	.macro _EXT rd, rs, p, s
	181	srl \rd, \rs, \p
	182	andi \rd, \rd, (1 << \s) - 1
	183	.endm
207083b1	184	#endif /* !CONFIG_CPU_MIPSR2 \|\| !CONFIG_CPU_MIPSR6 */
1d688087	185
41c594ab RB	186	/*
	187	* Temporary until all gas have MT ASE support
	188	*/
	189	.macro DMT reg=0
49a89efb	190	.word 0x41600bc1 \| (\reg << 16)
41c594ab RB	191	.endm
	192
	193	.macro EMT reg=0
49a89efb	194	.word 0x41600be1 \| (\reg << 16)
41c594ab RB	195	.endm
	196
	197	.macro DVPE reg=0
49a89efb	198	.word 0x41600001 \| (\reg << 16)
41c594ab RB	199	.endm
	200
	201	.macro EVPE reg=0
49a89efb	202	.word 0x41600021 \| (\reg << 16)
41c594ab RB	203	.endm
	204
	205	.macro MFTR rt=0, rd=0, u=0, sel=0
49a89efb	206	.word 0x41000000 \| (\rt << 16) \| (\rd << 11) \| (\u << 5) \| (\sel)
41c594ab RB	207	.endm
	208
	209	.macro MTTR rt=0, rd=0, u=0, sel=0
49a89efb	210	.word 0x41800000 \| (\rt << 16) \| (\rd << 11) \| (\u << 5) \| (\sel)
41c594ab RB	211	.endm
41c594ab RB	212
7f65afb9	213	#ifdef TOOLCHAIN_SUPPORTS_MSA
2bd7bc25 MC	214	/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
	215	#undef fp
	216
e1bebbab PB	217	.macro _cfcmsa rd, cs
	218	.set push
	219	.set mips32r2
2bd7bc25	220	.set fp=64
e1bebbab PB	221	.set msa
	222	cfcmsa \rd, $\cs
	223	.set pop
	224	.endm
	225
	226	.macro _ctcmsa cd, rs
	227	.set push
	228	.set mips32r2
2bd7bc25	229	.set fp=64
e1bebbab PB	230	.set msa
	231	ctcmsa $\cd, \rs
	232	.set pop
	233	.endm
	234
6b35e114 PB	235	.macro ld_b wd, off, base
	236	.set push
	237	.set mips32r2
92e9953c	238	.set fp=64
6b35e114 PB	239	.set msa
	240	ld.b $w\wd, \off(\base)
	241	.set pop
	242	.endm
	243
	244	.macro ld_h wd, off, base
	245	.set push
	246	.set mips32r2
92e9953c	247	.set fp=64
6b35e114 PB	248	.set msa
	249	ld.h $w\wd, \off(\base)
	250	.set pop
	251	.endm
	252
	253	.macro ld_w wd, off, base
	254	.set push
	255	.set mips32r2
92e9953c	256	.set fp=64
6b35e114 PB	257	.set msa
	258	ld.w $w\wd, \off(\base)
	259	.set pop
	260	.endm
	261
7f65afb9 PB	262	.macro ld_d wd, off, base
	263	.set push
	264	.set mips32r2
2bd7bc25	265	.set fp=64
7f65afb9 PB	266	.set msa
	267	ld.d $w\wd, \off(\base)
	268	.set pop
	269	.endm
	270
6b35e114 PB	271	.macro st_b wd, off, base
	272	.set push
	273	.set mips32r2
92e9953c	274	.set fp=64
6b35e114 PB	275	.set msa
	276	st.b $w\wd, \off(\base)
	277	.set pop
	278	.endm
	279
	280	.macro st_h wd, off, base
	281	.set push
	282	.set mips32r2
92e9953c	283	.set fp=64
6b35e114 PB	284	.set msa
	285	st.h $w\wd, \off(\base)
	286	.set pop
	287	.endm
	288
	289	.macro st_w wd, off, base
	290	.set push
	291	.set mips32r2
92e9953c	292	.set fp=64
6b35e114 PB	293	.set msa
	294	st.w $w\wd, \off(\base)
	295	.set pop
	296	.endm
	297
7f65afb9 PB	298	.macro st_d wd, off, base
	299	.set push
	300	.set mips32r2
2bd7bc25	301	.set fp=64
7f65afb9 PB	302	.set msa
	303	st.d $w\wd, \off(\base)
	304	.set pop
	305	.endm
	306
8a3c8b48	307	.macro copy_s_w ws, n
7f65afb9 PB	308	.set push
7f65afb9 PB	309	.set mips32r2
2bd7bc25	310	.set fp=64
7f65afb9	311	.set msa
8a3c8b48	312	copy_s.w $1, $w\ws[\n]
7f65afb9 PB	313	.set pop
	314	.endm
	315
8a3c8b48	316	.macro copy_s_d ws, n
7f65afb9 PB	317	.set push
7f65afb9 PB	318	.set mips64r2
2bd7bc25	319	.set fp=64
7f65afb9	320	.set msa
8a3c8b48	321	copy_s.d $1, $w\ws[\n]
7f65afb9 PB	322	.set pop
	323	.endm
	324
f23ce388	325	.macro insert_w wd, n
7f65afb9 PB	326	.set push
7f65afb9 PB	327	.set mips32r2
2bd7bc25	328	.set fp=64
7f65afb9	329	.set msa
f23ce388	330	insert.w $w\wd[\n], $1
7f65afb9 PB	331	.set pop
	332	.endm
	333
f23ce388	334	.macro insert_d wd, n
7f65afb9 PB	335	.set push
7f65afb9 PB	336	.set mips64r2
2bd7bc25	337	.set fp=64
7f65afb9	338	.set msa
f23ce388	339	insert.d $w\wd[\n], $1
7f65afb9 PB	340	.set pop
	341	.endm
	342	#else
d96cc3d1 SH	343
	344	#ifdef CONFIG_CPU_MICROMIPS
	345	#define CFC_MSA_INSN 0x587e0056
	346	#define CTC_MSA_INSN 0x583e0816
6b35e114 PB	347	#define LDB_MSA_INSN 0x58000807
	348	#define LDH_MSA_INSN 0x58000817
	349	#define LDW_MSA_INSN 0x58000827
d96cc3d1	350	#define LDD_MSA_INSN 0x58000837
6b35e114 PB	351	#define STB_MSA_INSN 0x5800080f
	352	#define STH_MSA_INSN 0x5800081f
	353	#define STW_MSA_INSN 0x5800082f
d96cc3d1	354	#define STD_MSA_INSN 0x5800083f
8a3c8b48 PB	355	#define COPY_SW_MSA_INSN 0x58b00056
8a3c8b48 PB	356	#define COPY_SD_MSA_INSN 0x58b80056
d96cc3d1 SH	357	#define INSERT_W_MSA_INSN 0x59300816
	358	#define INSERT_D_MSA_INSN 0x59380816
	359	#else
	360	#define CFC_MSA_INSN 0x787e0059
	361	#define CTC_MSA_INSN 0x783e0819
6b35e114 PB	362	#define LDB_MSA_INSN 0x78000820
	363	#define LDH_MSA_INSN 0x78000821
	364	#define LDW_MSA_INSN 0x78000822
d96cc3d1	365	#define LDD_MSA_INSN 0x78000823
6b35e114 PB	366	#define STB_MSA_INSN 0x78000824
	367	#define STH_MSA_INSN 0x78000825
	368	#define STW_MSA_INSN 0x78000826
d96cc3d1	369	#define STD_MSA_INSN 0x78000827
8a3c8b48 PB	370	#define COPY_SW_MSA_INSN 0x78b00059
8a3c8b48 PB	371	#define COPY_SD_MSA_INSN 0x78b80059
d96cc3d1 SH	372	#define INSERT_W_MSA_INSN 0x79300819
	373	#define INSERT_D_MSA_INSN 0x79380819
	374	#endif
	375
7f65afb9 PB	376	/*
	377	* Temporary until all toolchains in use include MSA support.
	378	*/
e1bebbab	379	.macro _cfcmsa rd, cs
7f65afb9 PB	380	.set push
7f65afb9 PB	381	.set noat
842dfc11	382	SET_HARDFLOAT
d96cc3d1 SH	383	.insn
d96cc3d1 SH	384	.word CFC_MSA_INSN \| (\cs << 11)
7f65afb9 PB	385	move \rd, $1
	386	.set pop
	387	.endm
	388
e1bebbab	389	.macro _ctcmsa cd, rs
7f65afb9 PB	390	.set push
7f65afb9 PB	391	.set noat
842dfc11	392	SET_HARDFLOAT
7f65afb9	393	move $1, \rs
d96cc3d1	394	.word CTC_MSA_INSN \| (\cd << 6)
7f65afb9 PB	395	.set pop
	396	.endm
	397
6b35e114 PB	398	.macro ld_b wd, off, base
	399	.set push
	400	.set noat
	401	SET_HARDFLOAT
ea168857	402	PTR_ADDU $1, \base, \off
6b35e114 PB	403	.word LDB_MSA_INSN \| (\wd << 6)
	404	.set pop
	405	.endm
	406
	407	.macro ld_h wd, off, base
	408	.set push
	409	.set noat
	410	SET_HARDFLOAT
ea168857	411	PTR_ADDU $1, \base, \off
6b35e114 PB	412	.word LDH_MSA_INSN \| (\wd << 6)
	413	.set pop
	414	.endm
	415
	416	.macro ld_w wd, off, base
	417	.set push
	418	.set noat
	419	SET_HARDFLOAT
ea168857	420	PTR_ADDU $1, \base, \off
6b35e114 PB	421	.word LDW_MSA_INSN \| (\wd << 6)
	422	.set pop
	423	.endm
	424
7f65afb9 PB	425	.macro ld_d wd, off, base
	426	.set push
	427	.set noat
842dfc11	428	SET_HARDFLOAT
ea168857	429	PTR_ADDU $1, \base, \off
d96cc3d1	430	.word LDD_MSA_INSN \| (\wd << 6)
7f65afb9 PB	431	.set pop
	432	.endm
	433
6b35e114 PB	434	.macro st_b wd, off, base
	435	.set push
	436	.set noat
	437	SET_HARDFLOAT
ea168857	438	PTR_ADDU $1, \base, \off
6b35e114 PB	439	.word STB_MSA_INSN \| (\wd << 6)
	440	.set pop
	441	.endm
	442
	443	.macro st_h wd, off, base
	444	.set push
	445	.set noat
	446	SET_HARDFLOAT
ea168857	447	PTR_ADDU $1, \base, \off
6b35e114 PB	448	.word STH_MSA_INSN \| (\wd << 6)
	449	.set pop
	450	.endm
	451
	452	.macro st_w wd, off, base
	453	.set push
	454	.set noat
	455	SET_HARDFLOAT
ea168857	456	PTR_ADDU $1, \base, \off
6b35e114 PB	457	.word STW_MSA_INSN \| (\wd << 6)
	458	.set pop
	459	.endm
	460
7f65afb9 PB	461	.macro st_d wd, off, base
	462	.set push
	463	.set noat
842dfc11	464	SET_HARDFLOAT
ea168857	465	PTR_ADDU $1, \base, \off
d96cc3d1	466	.word STD_MSA_INSN \| (\wd << 6)
7f65afb9 PB	467	.set pop
	468	.endm
	469
8a3c8b48	470	.macro copy_s_w ws, n
7f65afb9 PB	471	.set push
7f65afb9 PB	472	.set noat
842dfc11	473	SET_HARDFLOAT
d96cc3d1	474	.insn
8a3c8b48	475	.word COPY_SW_MSA_INSN \| (\n << 16) \| (\ws << 11)
7f65afb9 PB	476	.set pop
	477	.endm
	478
8a3c8b48	479	.macro copy_s_d ws, n
7f65afb9 PB	480	.set push
7f65afb9 PB	481	.set noat
842dfc11	482	SET_HARDFLOAT
d96cc3d1	483	.insn
8a3c8b48	484	.word COPY_SD_MSA_INSN \| (\n << 16) \| (\ws << 11)
7f65afb9 PB	485	.set pop
	486	.endm
	487
f23ce388	488	.macro insert_w wd, n
7f65afb9 PB	489	.set push
7f65afb9 PB	490	.set noat
842dfc11	491	SET_HARDFLOAT
d96cc3d1	492	.word INSERT_W_MSA_INSN \| (\n << 16) \| (\wd << 6)
7f65afb9 PB	493	.set pop
	494	.endm
	495
f23ce388	496	.macro insert_d wd, n
7f65afb9 PB	497	.set push
7f65afb9 PB	498	.set noat
842dfc11	499	SET_HARDFLOAT
d96cc3d1	500	.word INSERT_D_MSA_INSN \| (\n << 16) \| (\wd << 6)
7f65afb9 PB	501	.set pop
	502	.endm
	503	#endif
	504
143e93d7 JH	505	#ifdef TOOLCHAIN_SUPPORTS_MSA
	506	#define FPR_BASE_OFFS THREAD_FPR0
	507	#define FPR_BASE $1
	508	#else
	509	#define FPR_BASE_OFFS 0
	510	#define FPR_BASE \thread
	511	#endif
	512
1db1af84	513	.macro msa_save_all thread
f7a46fa7 PB	514	.set push
f7a46fa7 PB	515	.set noat
143e93d7 JH	516	#ifdef TOOLCHAIN_SUPPORTS_MSA
	517	PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
	518	#endif
	519	st_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE
	520	st_d 1, THREAD_FPR1 - FPR_BASE_OFFS, FPR_BASE
	521	st_d 2, THREAD_FPR2 - FPR_BASE_OFFS, FPR_BASE
	522	st_d 3, THREAD_FPR3 - FPR_BASE_OFFS, FPR_BASE
	523	st_d 4, THREAD_FPR4 - FPR_BASE_OFFS, FPR_BASE
	524	st_d 5, THREAD_FPR5 - FPR_BASE_OFFS, FPR_BASE
	525	st_d 6, THREAD_FPR6 - FPR_BASE_OFFS, FPR_BASE
	526	st_d 7, THREAD_FPR7 - FPR_BASE_OFFS, FPR_BASE
	527	st_d 8, THREAD_FPR8 - FPR_BASE_OFFS, FPR_BASE
	528	st_d 9, THREAD_FPR9 - FPR_BASE_OFFS, FPR_BASE
	529	st_d 10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
	530	st_d 11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
	531	st_d 12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
	532	st_d 13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
	533	st_d 14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
	534	st_d 15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
	535	st_d 16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
	536	st_d 17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
	537	st_d 18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
	538	st_d 19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
	539	st_d 20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
	540	st_d 21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
	541	st_d 22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
	542	st_d 23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
	543	st_d 24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
	544	st_d 25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
	545	st_d 26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
	546	st_d 27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
	547	st_d 28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
	548	st_d 29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
	549	st_d 30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
	550	st_d 31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
842dfc11	551	SET_HARDFLOAT
e1bebbab	552	_cfcmsa $1, MSA_CSR
f7a46fa7 PB	553	sw $1, THREAD_MSA_CSR(\thread)
f7a46fa7 PB	554	.set pop
1db1af84 PB	555	.endm
	556
	557	.macro msa_restore_all thread
f7a46fa7 PB	558	.set push
f7a46fa7 PB	559	.set noat
842dfc11	560	SET_HARDFLOAT
f7a46fa7	561	lw $1, THREAD_MSA_CSR(\thread)
e1bebbab	562	_ctcmsa MSA_CSR, $1
143e93d7 JH	563	#ifdef TOOLCHAIN_SUPPORTS_MSA
	564	PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
	565	#endif
	566	ld_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE
	567	ld_d 1, THREAD_FPR1 - FPR_BASE_OFFS, FPR_BASE
	568	ld_d 2, THREAD_FPR2 - FPR_BASE_OFFS, FPR_BASE
	569	ld_d 3, THREAD_FPR3 - FPR_BASE_OFFS, FPR_BASE
	570	ld_d 4, THREAD_FPR4 - FPR_BASE_OFFS, FPR_BASE
	571	ld_d 5, THREAD_FPR5 - FPR_BASE_OFFS, FPR_BASE
	572	ld_d 6, THREAD_FPR6 - FPR_BASE_OFFS, FPR_BASE
	573	ld_d 7, THREAD_FPR7 - FPR_BASE_OFFS, FPR_BASE
	574	ld_d 8, THREAD_FPR8 - FPR_BASE_OFFS, FPR_BASE
	575	ld_d 9, THREAD_FPR9 - FPR_BASE_OFFS, FPR_BASE
	576	ld_d 10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
	577	ld_d 11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
	578	ld_d 12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
	579	ld_d 13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
	580	ld_d 14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
	581	ld_d 15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
	582	ld_d 16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
	583	ld_d 17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
	584	ld_d 18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
	585	ld_d 19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
	586	ld_d 20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
	587	ld_d 21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
	588	ld_d 22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
	589	ld_d 23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
	590	ld_d 24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
	591	ld_d 25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
	592	ld_d 26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
	593	ld_d 27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
	594	ld_d 28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
	595	ld_d 29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
	596	ld_d 30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
	597	ld_d 31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
	598	.set pop
	599	.endm
	600
	601	#undef FPR_BASE_OFFS
	602	#undef FPR_BASE
1db1af84	603
c9017757 PB	604	.macro msa_init_upper wd
	605	#ifdef CONFIG_64BIT
	606	insert_d \wd, 1
	607	#else
	608	insert_w \wd, 2
	609	insert_w \wd, 3
	610	#endif
c9017757 PB	611	.endm
	612
	613	.macro msa_init_all_upper
	614	.set push
	615	.set noat
842dfc11	616	SET_HARDFLOAT
c9017757 PB	617	not $1, zero
c9017757 PB	618	msa_init_upper 0
a3a49810 PB	619	msa_init_upper 1
	620	msa_init_upper 2
	621	msa_init_upper 3
	622	msa_init_upper 4
	623	msa_init_upper 5
	624	msa_init_upper 6
	625	msa_init_upper 7
	626	msa_init_upper 8
	627	msa_init_upper 9
	628	msa_init_upper 10
	629	msa_init_upper 11
	630	msa_init_upper 12
	631	msa_init_upper 13
	632	msa_init_upper 14
	633	msa_init_upper 15
	634	msa_init_upper 16
	635	msa_init_upper 17
	636	msa_init_upper 18
	637	msa_init_upper 19
	638	msa_init_upper 20
	639	msa_init_upper 21
	640	msa_init_upper 22
	641	msa_init_upper 23
	642	msa_init_upper 24
	643	msa_init_upper 25
	644	msa_init_upper 26
	645	msa_init_upper 27
	646	msa_init_upper 28
	647	msa_init_upper 29
	648	msa_init_upper 30
	649	msa_init_upper 31
c9017757 PB	650	.set pop
	651	.endm
	652
1da177e4	653	#endif /* _ASM_ASMMACRO_H */