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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2003 Ralf Baechle | |
7 | */ | |
8 | #ifndef _ASM_ASMMACRO_H | |
9 | #define _ASM_ASMMACRO_H | |
42a3b4f2 | 10 | |
1da177e4 | 11 | #include <asm/hazards.h> |
71ca7588 | 12 | #include <asm/asm-offsets.h> |
f7a46fa7 | 13 | #include <asm/msa.h> |
42a3b4f2 | 14 | |
875d43e7 | 15 | #ifdef CONFIG_32BIT |
1da177e4 LT |
16 | #include <asm/asmmacro-32.h> |
17 | #endif | |
875d43e7 | 18 | #ifdef CONFIG_64BIT |
1da177e4 LT |
19 | #include <asm/asmmacro-64.h> |
20 | #endif | |
41c594ab | 21 | |
b633648c | 22 | #ifdef CONFIG_CPU_MIPSR2 |
b6354db5 DD |
23 | .macro local_irq_enable reg=t0 |
24 | ei | |
25 | irq_enable_hazard | |
26 | .endm | |
27 | ||
28 | .macro local_irq_disable reg=t0 | |
29 | di | |
30 | irq_disable_hazard | |
31 | .endm | |
41c594ab | 32 | #else |
1da177e4 LT |
33 | .macro local_irq_enable reg=t0 |
34 | mfc0 \reg, CP0_STATUS | |
35 | ori \reg, \reg, 1 | |
36 | mtc0 \reg, CP0_STATUS | |
37 | irq_enable_hazard | |
38 | .endm | |
39 | ||
40 | .macro local_irq_disable reg=t0 | |
71ca7588 JQ |
41 | #ifdef CONFIG_PREEMPT |
42 | lw \reg, TI_PRE_COUNT($28) | |
43 | addi \reg, \reg, 1 | |
44 | sw \reg, TI_PRE_COUNT($28) | |
45 | #endif | |
1da177e4 LT |
46 | mfc0 \reg, CP0_STATUS |
47 | ori \reg, \reg, 1 | |
48 | xori \reg, \reg, 1 | |
49 | mtc0 \reg, CP0_STATUS | |
50 | irq_disable_hazard | |
71ca7588 JQ |
51 | #ifdef CONFIG_PREEMPT |
52 | lw \reg, TI_PRE_COUNT($28) | |
53 | addi \reg, \reg, -1 | |
54 | sw \reg, TI_PRE_COUNT($28) | |
55 | #endif | |
1da177e4 | 56 | .endm |
b633648c | 57 | #endif /* CONFIG_CPU_MIPSR2 */ |
1da177e4 | 58 | |
597ce172 | 59 | .macro fpu_save_16even thread tmp=t0 |
842dfc11 ML |
60 | .set push |
61 | SET_HARDFLOAT | |
597ce172 | 62 | cfc1 \tmp, fcr31 |
02987633 PB |
63 | sdc1 $f0, THREAD_FPR0_LS64(\thread) |
64 | sdc1 $f2, THREAD_FPR2_LS64(\thread) | |
65 | sdc1 $f4, THREAD_FPR4_LS64(\thread) | |
66 | sdc1 $f6, THREAD_FPR6_LS64(\thread) | |
67 | sdc1 $f8, THREAD_FPR8_LS64(\thread) | |
68 | sdc1 $f10, THREAD_FPR10_LS64(\thread) | |
69 | sdc1 $f12, THREAD_FPR12_LS64(\thread) | |
70 | sdc1 $f14, THREAD_FPR14_LS64(\thread) | |
71 | sdc1 $f16, THREAD_FPR16_LS64(\thread) | |
72 | sdc1 $f18, THREAD_FPR18_LS64(\thread) | |
73 | sdc1 $f20, THREAD_FPR20_LS64(\thread) | |
74 | sdc1 $f22, THREAD_FPR22_LS64(\thread) | |
75 | sdc1 $f24, THREAD_FPR24_LS64(\thread) | |
76 | sdc1 $f26, THREAD_FPR26_LS64(\thread) | |
77 | sdc1 $f28, THREAD_FPR28_LS64(\thread) | |
78 | sdc1 $f30, THREAD_FPR30_LS64(\thread) | |
597ce172 | 79 | sw \tmp, THREAD_FCR31(\thread) |
842dfc11 | 80 | .set pop |
597ce172 PB |
81 | .endm |
82 | ||
83 | .macro fpu_save_16odd thread | |
84 | .set push | |
85 | .set mips64r2 | |
842dfc11 | 86 | SET_HARDFLOAT |
02987633 PB |
87 | sdc1 $f1, THREAD_FPR1_LS64(\thread) |
88 | sdc1 $f3, THREAD_FPR3_LS64(\thread) | |
89 | sdc1 $f5, THREAD_FPR5_LS64(\thread) | |
90 | sdc1 $f7, THREAD_FPR7_LS64(\thread) | |
91 | sdc1 $f9, THREAD_FPR9_LS64(\thread) | |
92 | sdc1 $f11, THREAD_FPR11_LS64(\thread) | |
93 | sdc1 $f13, THREAD_FPR13_LS64(\thread) | |
94 | sdc1 $f15, THREAD_FPR15_LS64(\thread) | |
95 | sdc1 $f17, THREAD_FPR17_LS64(\thread) | |
96 | sdc1 $f19, THREAD_FPR19_LS64(\thread) | |
97 | sdc1 $f21, THREAD_FPR21_LS64(\thread) | |
98 | sdc1 $f23, THREAD_FPR23_LS64(\thread) | |
99 | sdc1 $f25, THREAD_FPR25_LS64(\thread) | |
100 | sdc1 $f27, THREAD_FPR27_LS64(\thread) | |
101 | sdc1 $f29, THREAD_FPR29_LS64(\thread) | |
102 | sdc1 $f31, THREAD_FPR31_LS64(\thread) | |
597ce172 PB |
103 | .set pop |
104 | .endm | |
105 | ||
106 | .macro fpu_save_double thread status tmp | |
f5868f05 | 107 | #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) |
597ce172 PB |
108 | sll \tmp, \status, 5 |
109 | bgez \tmp, 10f | |
110 | fpu_save_16odd \thread | |
111 | 10: | |
112 | #endif | |
113 | fpu_save_16even \thread \tmp | |
114 | .endm | |
115 | ||
116 | .macro fpu_restore_16even thread tmp=t0 | |
842dfc11 ML |
117 | .set push |
118 | SET_HARDFLOAT | |
597ce172 | 119 | lw \tmp, THREAD_FCR31(\thread) |
02987633 PB |
120 | ldc1 $f0, THREAD_FPR0_LS64(\thread) |
121 | ldc1 $f2, THREAD_FPR2_LS64(\thread) | |
122 | ldc1 $f4, THREAD_FPR4_LS64(\thread) | |
123 | ldc1 $f6, THREAD_FPR6_LS64(\thread) | |
124 | ldc1 $f8, THREAD_FPR8_LS64(\thread) | |
125 | ldc1 $f10, THREAD_FPR10_LS64(\thread) | |
126 | ldc1 $f12, THREAD_FPR12_LS64(\thread) | |
127 | ldc1 $f14, THREAD_FPR14_LS64(\thread) | |
128 | ldc1 $f16, THREAD_FPR16_LS64(\thread) | |
129 | ldc1 $f18, THREAD_FPR18_LS64(\thread) | |
130 | ldc1 $f20, THREAD_FPR20_LS64(\thread) | |
131 | ldc1 $f22, THREAD_FPR22_LS64(\thread) | |
132 | ldc1 $f24, THREAD_FPR24_LS64(\thread) | |
133 | ldc1 $f26, THREAD_FPR26_LS64(\thread) | |
134 | ldc1 $f28, THREAD_FPR28_LS64(\thread) | |
135 | ldc1 $f30, THREAD_FPR30_LS64(\thread) | |
597ce172 PB |
136 | ctc1 \tmp, fcr31 |
137 | .endm | |
138 | ||
139 | .macro fpu_restore_16odd thread | |
140 | .set push | |
141 | .set mips64r2 | |
842dfc11 | 142 | SET_HARDFLOAT |
02987633 PB |
143 | ldc1 $f1, THREAD_FPR1_LS64(\thread) |
144 | ldc1 $f3, THREAD_FPR3_LS64(\thread) | |
145 | ldc1 $f5, THREAD_FPR5_LS64(\thread) | |
146 | ldc1 $f7, THREAD_FPR7_LS64(\thread) | |
147 | ldc1 $f9, THREAD_FPR9_LS64(\thread) | |
148 | ldc1 $f11, THREAD_FPR11_LS64(\thread) | |
149 | ldc1 $f13, THREAD_FPR13_LS64(\thread) | |
150 | ldc1 $f15, THREAD_FPR15_LS64(\thread) | |
151 | ldc1 $f17, THREAD_FPR17_LS64(\thread) | |
152 | ldc1 $f19, THREAD_FPR19_LS64(\thread) | |
153 | ldc1 $f21, THREAD_FPR21_LS64(\thread) | |
154 | ldc1 $f23, THREAD_FPR23_LS64(\thread) | |
155 | ldc1 $f25, THREAD_FPR25_LS64(\thread) | |
156 | ldc1 $f27, THREAD_FPR27_LS64(\thread) | |
157 | ldc1 $f29, THREAD_FPR29_LS64(\thread) | |
158 | ldc1 $f31, THREAD_FPR31_LS64(\thread) | |
597ce172 PB |
159 | .set pop |
160 | .endm | |
161 | ||
162 | .macro fpu_restore_double thread status tmp | |
f5868f05 | 163 | #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) |
597ce172 PB |
164 | sll \tmp, \status, 5 |
165 | bgez \tmp, 10f # 16 register mode? | |
166 | ||
167 | fpu_restore_16odd \thread | |
168 | 10: | |
169 | #endif | |
170 | fpu_restore_16even \thread \tmp | |
171 | .endm | |
172 | ||
1d688087 PB |
173 | #ifdef CONFIG_CPU_MIPSR2 |
174 | .macro _EXT rd, rs, p, s | |
175 | ext \rd, \rs, \p, \s | |
176 | .endm | |
177 | #else /* !CONFIG_CPU_MIPSR2 */ | |
178 | .macro _EXT rd, rs, p, s | |
179 | srl \rd, \rs, \p | |
180 | andi \rd, \rd, (1 << \s) - 1 | |
181 | .endm | |
182 | #endif /* !CONFIG_CPU_MIPSR2 */ | |
183 | ||
41c594ab RB |
184 | /* |
185 | * Temporary until all gas have MT ASE support | |
186 | */ | |
187 | .macro DMT reg=0 | |
49a89efb | 188 | .word 0x41600bc1 | (\reg << 16) |
41c594ab RB |
189 | .endm |
190 | ||
191 | .macro EMT reg=0 | |
49a89efb | 192 | .word 0x41600be1 | (\reg << 16) |
41c594ab RB |
193 | .endm |
194 | ||
195 | .macro DVPE reg=0 | |
49a89efb | 196 | .word 0x41600001 | (\reg << 16) |
41c594ab RB |
197 | .endm |
198 | ||
199 | .macro EVPE reg=0 | |
49a89efb | 200 | .word 0x41600021 | (\reg << 16) |
41c594ab RB |
201 | .endm |
202 | ||
203 | .macro MFTR rt=0, rd=0, u=0, sel=0 | |
49a89efb | 204 | .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) |
41c594ab RB |
205 | .endm |
206 | ||
207 | .macro MTTR rt=0, rd=0, u=0, sel=0 | |
49a89efb | 208 | .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) |
41c594ab RB |
209 | .endm |
210 | ||
7f65afb9 PB |
211 | #ifdef TOOLCHAIN_SUPPORTS_MSA |
212 | .macro ld_d wd, off, base | |
213 | .set push | |
214 | .set mips32r2 | |
215 | .set msa | |
216 | ld.d $w\wd, \off(\base) | |
217 | .set pop | |
218 | .endm | |
219 | ||
220 | .macro st_d wd, off, base | |
221 | .set push | |
222 | .set mips32r2 | |
223 | .set msa | |
224 | st.d $w\wd, \off(\base) | |
225 | .set pop | |
226 | .endm | |
227 | ||
228 | .macro copy_u_w rd, ws, n | |
229 | .set push | |
230 | .set mips32r2 | |
231 | .set msa | |
232 | copy_u.w \rd, $w\ws[\n] | |
233 | .set pop | |
234 | .endm | |
235 | ||
236 | .macro copy_u_d rd, ws, n | |
237 | .set push | |
238 | .set mips64r2 | |
239 | .set msa | |
240 | copy_u.d \rd, $w\ws[\n] | |
241 | .set pop | |
242 | .endm | |
243 | ||
244 | .macro insert_w wd, n, rs | |
245 | .set push | |
246 | .set mips32r2 | |
247 | .set msa | |
248 | insert.w $w\wd[\n], \rs | |
249 | .set pop | |
250 | .endm | |
251 | ||
252 | .macro insert_d wd, n, rs | |
253 | .set push | |
254 | .set mips64r2 | |
255 | .set msa | |
256 | insert.d $w\wd[\n], \rs | |
257 | .set pop | |
258 | .endm | |
259 | #else | |
d96cc3d1 SH |
260 | |
261 | #ifdef CONFIG_CPU_MICROMIPS | |
262 | #define CFC_MSA_INSN 0x587e0056 | |
263 | #define CTC_MSA_INSN 0x583e0816 | |
264 | #define LDD_MSA_INSN 0x58000837 | |
265 | #define STD_MSA_INSN 0x5800083f | |
266 | #define COPY_UW_MSA_INSN 0x58f00056 | |
267 | #define COPY_UD_MSA_INSN 0x58f80056 | |
268 | #define INSERT_W_MSA_INSN 0x59300816 | |
269 | #define INSERT_D_MSA_INSN 0x59380816 | |
270 | #else | |
271 | #define CFC_MSA_INSN 0x787e0059 | |
272 | #define CTC_MSA_INSN 0x783e0819 | |
273 | #define LDD_MSA_INSN 0x78000823 | |
274 | #define STD_MSA_INSN 0x78000827 | |
275 | #define COPY_UW_MSA_INSN 0x78f00059 | |
276 | #define COPY_UD_MSA_INSN 0x78f80059 | |
277 | #define INSERT_W_MSA_INSN 0x79300819 | |
278 | #define INSERT_D_MSA_INSN 0x79380819 | |
279 | #endif | |
280 | ||
7f65afb9 PB |
281 | /* |
282 | * Temporary until all toolchains in use include MSA support. | |
283 | */ | |
284 | .macro cfcmsa rd, cs | |
285 | .set push | |
286 | .set noat | |
842dfc11 | 287 | SET_HARDFLOAT |
d96cc3d1 SH |
288 | .insn |
289 | .word CFC_MSA_INSN | (\cs << 11) | |
7f65afb9 PB |
290 | move \rd, $1 |
291 | .set pop | |
292 | .endm | |
293 | ||
294 | .macro ctcmsa cd, rs | |
295 | .set push | |
296 | .set noat | |
842dfc11 | 297 | SET_HARDFLOAT |
7f65afb9 | 298 | move $1, \rs |
d96cc3d1 | 299 | .word CTC_MSA_INSN | (\cd << 6) |
7f65afb9 PB |
300 | .set pop |
301 | .endm | |
302 | ||
303 | .macro ld_d wd, off, base | |
304 | .set push | |
305 | .set noat | |
842dfc11 | 306 | SET_HARDFLOAT |
7f65afb9 | 307 | add $1, \base, \off |
d96cc3d1 | 308 | .word LDD_MSA_INSN | (\wd << 6) |
7f65afb9 PB |
309 | .set pop |
310 | .endm | |
311 | ||
312 | .macro st_d wd, off, base | |
313 | .set push | |
314 | .set noat | |
842dfc11 | 315 | SET_HARDFLOAT |
7f65afb9 | 316 | add $1, \base, \off |
d96cc3d1 | 317 | .word STD_MSA_INSN | (\wd << 6) |
7f65afb9 PB |
318 | .set pop |
319 | .endm | |
320 | ||
321 | .macro copy_u_w rd, ws, n | |
322 | .set push | |
323 | .set noat | |
842dfc11 | 324 | SET_HARDFLOAT |
d96cc3d1 SH |
325 | .insn |
326 | .word COPY_UW_MSA_INSN | (\n << 16) | (\ws << 11) | |
7f65afb9 PB |
327 | /* move triggers an assembler bug... */ |
328 | or \rd, $1, zero | |
329 | .set pop | |
330 | .endm | |
331 | ||
332 | .macro copy_u_d rd, ws, n | |
333 | .set push | |
334 | .set noat | |
842dfc11 | 335 | SET_HARDFLOAT |
d96cc3d1 SH |
336 | .insn |
337 | .word COPY_UD_MSA_INSN | (\n << 16) | (\ws << 11) | |
7f65afb9 PB |
338 | /* move triggers an assembler bug... */ |
339 | or \rd, $1, zero | |
340 | .set pop | |
341 | .endm | |
342 | ||
343 | .macro insert_w wd, n, rs | |
344 | .set push | |
345 | .set noat | |
842dfc11 | 346 | SET_HARDFLOAT |
7f65afb9 PB |
347 | /* move triggers an assembler bug... */ |
348 | or $1, \rs, zero | |
d96cc3d1 | 349 | .word INSERT_W_MSA_INSN | (\n << 16) | (\wd << 6) |
7f65afb9 PB |
350 | .set pop |
351 | .endm | |
352 | ||
353 | .macro insert_d wd, n, rs | |
354 | .set push | |
355 | .set noat | |
842dfc11 | 356 | SET_HARDFLOAT |
7f65afb9 PB |
357 | /* move triggers an assembler bug... */ |
358 | or $1, \rs, zero | |
d96cc3d1 | 359 | .word INSERT_D_MSA_INSN | (\n << 16) | (\wd << 6) |
7f65afb9 PB |
360 | .set pop |
361 | .endm | |
362 | #endif | |
363 | ||
1db1af84 PB |
364 | .macro msa_save_all thread |
365 | st_d 0, THREAD_FPR0, \thread | |
366 | st_d 1, THREAD_FPR1, \thread | |
367 | st_d 2, THREAD_FPR2, \thread | |
368 | st_d 3, THREAD_FPR3, \thread | |
369 | st_d 4, THREAD_FPR4, \thread | |
370 | st_d 5, THREAD_FPR5, \thread | |
371 | st_d 6, THREAD_FPR6, \thread | |
372 | st_d 7, THREAD_FPR7, \thread | |
373 | st_d 8, THREAD_FPR8, \thread | |
374 | st_d 9, THREAD_FPR9, \thread | |
375 | st_d 10, THREAD_FPR10, \thread | |
376 | st_d 11, THREAD_FPR11, \thread | |
377 | st_d 12, THREAD_FPR12, \thread | |
378 | st_d 13, THREAD_FPR13, \thread | |
379 | st_d 14, THREAD_FPR14, \thread | |
380 | st_d 15, THREAD_FPR15, \thread | |
381 | st_d 16, THREAD_FPR16, \thread | |
382 | st_d 17, THREAD_FPR17, \thread | |
383 | st_d 18, THREAD_FPR18, \thread | |
384 | st_d 19, THREAD_FPR19, \thread | |
385 | st_d 20, THREAD_FPR20, \thread | |
386 | st_d 21, THREAD_FPR21, \thread | |
387 | st_d 22, THREAD_FPR22, \thread | |
388 | st_d 23, THREAD_FPR23, \thread | |
389 | st_d 24, THREAD_FPR24, \thread | |
390 | st_d 25, THREAD_FPR25, \thread | |
391 | st_d 26, THREAD_FPR26, \thread | |
392 | st_d 27, THREAD_FPR27, \thread | |
393 | st_d 28, THREAD_FPR28, \thread | |
394 | st_d 29, THREAD_FPR29, \thread | |
395 | st_d 30, THREAD_FPR30, \thread | |
396 | st_d 31, THREAD_FPR31, \thread | |
f7a46fa7 PB |
397 | .set push |
398 | .set noat | |
842dfc11 | 399 | SET_HARDFLOAT |
f7a46fa7 PB |
400 | cfcmsa $1, MSA_CSR |
401 | sw $1, THREAD_MSA_CSR(\thread) | |
402 | .set pop | |
1db1af84 PB |
403 | .endm |
404 | ||
405 | .macro msa_restore_all thread | |
f7a46fa7 PB |
406 | .set push |
407 | .set noat | |
842dfc11 | 408 | SET_HARDFLOAT |
f7a46fa7 PB |
409 | lw $1, THREAD_MSA_CSR(\thread) |
410 | ctcmsa MSA_CSR, $1 | |
411 | .set pop | |
1db1af84 PB |
412 | ld_d 0, THREAD_FPR0, \thread |
413 | ld_d 1, THREAD_FPR1, \thread | |
414 | ld_d 2, THREAD_FPR2, \thread | |
415 | ld_d 3, THREAD_FPR3, \thread | |
416 | ld_d 4, THREAD_FPR4, \thread | |
417 | ld_d 5, THREAD_FPR5, \thread | |
418 | ld_d 6, THREAD_FPR6, \thread | |
419 | ld_d 7, THREAD_FPR7, \thread | |
420 | ld_d 8, THREAD_FPR8, \thread | |
421 | ld_d 9, THREAD_FPR9, \thread | |
422 | ld_d 10, THREAD_FPR10, \thread | |
423 | ld_d 11, THREAD_FPR11, \thread | |
424 | ld_d 12, THREAD_FPR12, \thread | |
425 | ld_d 13, THREAD_FPR13, \thread | |
426 | ld_d 14, THREAD_FPR14, \thread | |
427 | ld_d 15, THREAD_FPR15, \thread | |
428 | ld_d 16, THREAD_FPR16, \thread | |
429 | ld_d 17, THREAD_FPR17, \thread | |
430 | ld_d 18, THREAD_FPR18, \thread | |
431 | ld_d 19, THREAD_FPR19, \thread | |
432 | ld_d 20, THREAD_FPR20, \thread | |
433 | ld_d 21, THREAD_FPR21, \thread | |
434 | ld_d 22, THREAD_FPR22, \thread | |
435 | ld_d 23, THREAD_FPR23, \thread | |
436 | ld_d 24, THREAD_FPR24, \thread | |
437 | ld_d 25, THREAD_FPR25, \thread | |
438 | ld_d 26, THREAD_FPR26, \thread | |
439 | ld_d 27, THREAD_FPR27, \thread | |
440 | ld_d 28, THREAD_FPR28, \thread | |
441 | ld_d 29, THREAD_FPR29, \thread | |
442 | ld_d 30, THREAD_FPR30, \thread | |
443 | ld_d 31, THREAD_FPR31, \thread | |
444 | .endm | |
445 | ||
c9017757 PB |
446 | .macro msa_init_upper wd |
447 | #ifdef CONFIG_64BIT | |
448 | insert_d \wd, 1 | |
449 | #else | |
450 | insert_w \wd, 2 | |
451 | insert_w \wd, 3 | |
452 | #endif | |
453 | .if 31-\wd | |
454 | msa_init_upper (\wd+1) | |
455 | .endif | |
456 | .endm | |
457 | ||
458 | .macro msa_init_all_upper | |
459 | .set push | |
460 | .set noat | |
842dfc11 | 461 | SET_HARDFLOAT |
c9017757 PB |
462 | not $1, zero |
463 | msa_init_upper 0 | |
464 | .set pop | |
465 | .endm | |
466 | ||
1da177e4 | 467 | #endif /* _ASM_ASMMACRO_H */ |