[deliverable/linux.git] / arch / mips / include / asm / barrier.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org)
 */
#ifndef __ASM_BARRIER_H
#define __ASM_BARRIER_H

#include <asm/addrspace.h>

#ifdef CONFIG_CPU_HAS_SYNC
#define __sync()				\
	__asm__ __volatile__(			\
		".set	push\n\t"		\
		".set	noreorder\n\t"		\
		".set	mips2\n\t"		\
		"sync\n\t"			\
		".set	pop"			\
		: /* no output */		\
		: /* no input */		\
		: "memory")
#else
#define __sync()	do { } while(0)
#endif

#define __fast_iob()				\
	__asm__ __volatile__(			\
		".set	push\n\t"		\
		".set	noreorder\n\t"		\
		"lw	$0,%0\n\t"		\
		"nop\n\t"			\
		".set	pop"			\
		: /* no output */		\
		: "m" (*(int *)CKSEG1)		\
		: "memory")
#ifdef CONFIG_CPU_CAVIUM_OCTEON
# define OCTEON_SYNCW_STR	".set push\n.set arch=octeon\nsyncw\nsyncw\n.set pop\n"
# define __syncw()	__asm__ __volatile__(OCTEON_SYNCW_STR : : : "memory")

# define fast_wmb()	__syncw()
# define fast_rmb()	barrier()
# define fast_mb()	__sync()
# define fast_iob()	do { } while (0)
#else /* ! CONFIG_CPU_CAVIUM_OCTEON */
# define fast_wmb()	__sync()
# define fast_rmb()	__sync()
# define fast_mb()	__sync()
# ifdef CONFIG_SGI_IP28
#  define fast_iob()				\
	__asm__ __volatile__(			\
		".set	push\n\t"		\
		".set	noreorder\n\t"		\
		"lw	$0,%0\n\t"		\
		"sync\n\t"			\
		"lw	$0,%0\n\t"		\
		".set	pop"			\
		: /* no output */		\
		: "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
		: "memory")
# else
#  define fast_iob()				\
	do {					\
		__sync();			\
		__fast_iob();			\
	} while (0)
# endif
#endif /* CONFIG_CPU_CAVIUM_OCTEON */

#ifdef CONFIG_CPU_HAS_WB

#include <asm/wbflush.h>

#define mb()		wbflush()
#define iob()		wbflush()

#else /* !CONFIG_CPU_HAS_WB */

#define mb()		fast_mb()
#define iob()		fast_iob()

#endif /* !CONFIG_CPU_HAS_WB */

#define wmb()		fast_wmb()
#define rmb()		fast_rmb()

#if defined(CONFIG_WEAK_ORDERING)
# ifdef CONFIG_CPU_CAVIUM_OCTEON
#  define __smp_mb()	__sync()
#  define __smp_rmb()	barrier()
#  define __smp_wmb()	__syncw()
# else
#  define __smp_mb()	__asm__ __volatile__("sync" : : :"memory")
#  define __smp_rmb()	__asm__ __volatile__("sync" : : :"memory")
#  define __smp_wmb()	__asm__ __volatile__("sync" : : :"memory")
# endif
#else
#define __smp_mb()	barrier()
#define __smp_rmb()	barrier()
#define __smp_wmb()	barrier()
#endif

#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
#define __WEAK_LLSC_MB		"	sync	\n"
#else
#define __WEAK_LLSC_MB		"		\n"
#endif

#define smp_llsc_mb()	__asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")

#ifdef CONFIG_CPU_CAVIUM_OCTEON
#define smp_mb__before_llsc() smp_wmb()
#define __smp_mb__before_llsc() __smp_wmb()
/* Cause previous writes to become visible on all CPUs as soon as possible */
#define nudge_writes() __asm__ __volatile__(".set push\n\t"		\
					    ".set arch=octeon\n\t"	\
					    "syncw\n\t"			\
					    ".set pop" : : : "memory")
#else
#define smp_mb__before_llsc() smp_llsc_mb()
#define __smp_mb__before_llsc() smp_llsc_mb()
#define nudge_writes() mb()
#endif

#define __smp_mb__before_atomic()	__smp_mb__before_llsc()
#define __smp_mb__after_atomic()	smp_llsc_mb()

#include <asm-generic/barrier.h>

#endif /* __ASM_BARRIER_H */
Commit	Line	Data
0004a9df RB	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org)
	7	*/
	8	#ifndef __ASM_BARRIER_H
	9	#define __ASM_BARRIER_H
	10
b81947c6 DH	11	#include <asm/addrspace.h>
b81947c6 DH	12
0004a9df RB	13	#ifdef CONFIG_CPU_HAS_SYNC
	14	#define __sync() \
	15	__asm__ __volatile__( \
	16	".set push\n\t" \
	17	".set noreorder\n\t" \
	18	".set mips2\n\t" \
	19	"sync\n\t" \
	20	".set pop" \
	21	: /* no output */ \
	22	: /* no input */ \
	23	: "memory")
	24	#else
	25	#define __sync() do { } while(0)
	26	#endif
	27
	28	#define __fast_iob() \
	29	__asm__ __volatile__( \
	30	".set push\n\t" \
	31	".set noreorder\n\t" \
	32	"lw $0,%0\n\t" \
	33	"nop\n\t" \
	34	".set pop" \
	35	: /* no output */ \
	36	: "m" ((int )CKSEG1) \
	37	: "memory")
6b07d38a DD	38	#ifdef CONFIG_CPU_CAVIUM_OCTEON
6b07d38a DD	39	# define OCTEON_SYNCW_STR ".set push\n.set arch=octeon\nsyncw\nsyncw\n.set pop\n"
70342287	40	# define __syncw() __asm__ __volatile__(OCTEON_SYNCW_STR : : : "memory")
6b07d38a DD	41
	42	# define fast_wmb() __syncw()
	43	# define fast_rmb() barrier()
	44	# define fast_mb() __sync()
	45	# define fast_iob() do { } while (0)
	46	#else /* ! CONFIG_CPU_CAVIUM_OCTEON */
	47	# define fast_wmb() __sync()
	48	# define fast_rmb() __sync()
	49	# define fast_mb() __sync()
	50	# ifdef CONFIG_SGI_IP28
	51	# define fast_iob() \
7a2852e4 TB	52	__asm__ __volatile__( \
	53	".set push\n\t" \
	54	".set noreorder\n\t" \
	55	"lw $0,%0\n\t" \
	56	"sync\n\t" \
	57	"lw $0,%0\n\t" \
	58	".set pop" \
	59	: /* no output */ \
	60	: "m" ((int )CKSEG1ADDR(0x1fa00004)) \
	61	: "memory")
6b07d38a DD	62	# else
6b07d38a DD	63	# define fast_iob() \
0004a9df RB	64	do { \
	65	__sync(); \
	66	__fast_iob(); \
	67	} while (0)
6b07d38a DD	68	# endif
6b07d38a DD	69	#endif /* CONFIG_CPU_CAVIUM_OCTEON */
0004a9df RB	70
	71	#ifdef CONFIG_CPU_HAS_WB
	72
	73	#include <asm/wbflush.h>
	74
0004a9df RB	75	#define mb() wbflush()
	76	#define iob() wbflush()
	77
	78	#else /* !CONFIG_CPU_HAS_WB */
	79
0004a9df RB	80	#define mb() fast_mb()
	81	#define iob() fast_iob()
	82
	83	#endif /* !CONFIG_CPU_HAS_WB */
	84
1077fa36 AD	85	#define wmb() fast_wmb()
1077fa36 AD	86	#define rmb() fast_rmb()
1077fa36	87
a60514ba	88	#if defined(CONFIG_WEAK_ORDERING)
6b07d38a	89	# ifdef CONFIG_CPU_CAVIUM_OCTEON
a60514ba MT	90	# define __smp_mb() __sync()
	91	# define __smp_rmb() barrier()
	92	# define __smp_wmb() __syncw()
6b07d38a	93	# else
a60514ba MT	94	# define __smp_mb() __asm__ __volatile__("sync" : : :"memory")
	95	# define __smp_rmb() __asm__ __volatile__("sync" : : :"memory")
	96	# define __smp_wmb() __asm__ __volatile__("sync" : : :"memory")
6b07d38a	97	# endif
0004a9df	98	#else
a60514ba MT	99	#define __smp_mb() barrier()
	100	#define __smp_rmb() barrier()
	101	#define __smp_wmb() barrier()
0004a9df	102	#endif
f252ffd5	103
17099b11	104	#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
70342287	105	#define __WEAK_LLSC_MB " sync \n"
17099b11 RB	106	#else
	107	#define __WEAK_LLSC_MB " \n"
	108	#endif
0004a9df	109
17099b11	110	#define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
17099b11	111
6b07d38a DD	112	#ifdef CONFIG_CPU_CAVIUM_OCTEON
6b07d38a DD	113	#define smp_mb__before_llsc() smp_wmb()
a60514ba	114	#define __smp_mb__before_llsc() __smp_wmb()
500c2e1f DD	115	/* Cause previous writes to become visible on all CPUs as soon as possible */
	116	#define nudge_writes() __asm__ __volatile__(".set push\n\t" \
	117	".set arch=octeon\n\t" \
	118	"syncw\n\t" \
	119	".set pop" : : : "memory")
6b07d38a	120	#else
f252ffd5	121	#define smp_mb__before_llsc() smp_llsc_mb()
a60514ba	122	#define __smp_mb__before_llsc() smp_llsc_mb()
500c2e1f	123	#define nudge_writes() mb()
6b07d38a	124	#endif
f252ffd5	125
a60514ba MT	126	#define __smp_mb__before_atomic() __smp_mb__before_llsc()
a60514ba MT	127	#define __smp_mb__after_atomic() smp_llsc_mb()
91bbefe6	128
fa083e28 MT	129	#include <asm-generic/barrier.h>
fa083e28 MT	130
0004a9df	131	#endif /* __ASM_BARRIER_H */