[deliverable/linux.git] / arch / mips / include / asm / cpu-features.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2003, 2004 Ralf Baechle
 * Copyright (C) 2004  Maciej W. Rozycki
 */
#ifndef __ASM_CPU_FEATURES_H
#define __ASM_CPU_FEATURES_H

#include <asm/cpu.h>
#include <asm/cpu-info.h>
#include <cpu-feature-overrides.h>

/*
 * SMP assumption: Options of CPU 0 are a superset of all processors.
 * This is true for all known MIPS systems.
 */
#ifndef cpu_has_tlb
#define cpu_has_tlb		(cpu_data[0].options & MIPS_CPU_TLB)
#endif

/*
 * For the moment we don't consider R6000 and R8000 so we can assume that
 * anything that doesn't support R4000-style exceptions and interrupts is
 * R3000-like.  Users should still treat these two macro definitions as
 * opaque.
 */
#ifndef cpu_has_3kex
#define cpu_has_3kex		(!cpu_has_4kex)
#endif
#ifndef cpu_has_4kex
#define cpu_has_4kex		(cpu_data[0].options & MIPS_CPU_4KEX)
#endif
#ifndef cpu_has_3k_cache
#define cpu_has_3k_cache	(cpu_data[0].options & MIPS_CPU_3K_CACHE)
#endif
#define cpu_has_6k_cache	0
#define cpu_has_8k_cache	0
#ifndef cpu_has_4k_cache
#define cpu_has_4k_cache	(cpu_data[0].options & MIPS_CPU_4K_CACHE)
#endif
#ifndef cpu_has_tx39_cache
#define cpu_has_tx39_cache	(cpu_data[0].options & MIPS_CPU_TX39_CACHE)
#endif
#ifndef cpu_has_octeon_cache
#define cpu_has_octeon_cache	0
#endif
#ifndef cpu_has_fpu
#define cpu_has_fpu		(current_cpu_data.options & MIPS_CPU_FPU)
#define raw_cpu_has_fpu		(raw_current_cpu_data.options & MIPS_CPU_FPU)
#else
#define raw_cpu_has_fpu		cpu_has_fpu
#endif
#ifndef cpu_has_32fpr
#define cpu_has_32fpr		(cpu_data[0].options & MIPS_CPU_32FPR)
#endif
#ifndef cpu_has_counter
#define cpu_has_counter		(cpu_data[0].options & MIPS_CPU_COUNTER)
#endif
#ifndef cpu_has_watch
#define cpu_has_watch		(cpu_data[0].options & MIPS_CPU_WATCH)
#endif
#ifndef cpu_has_divec
#define cpu_has_divec		(cpu_data[0].options & MIPS_CPU_DIVEC)
#endif
#ifndef cpu_has_vce
#define cpu_has_vce		(cpu_data[0].options & MIPS_CPU_VCE)
#endif
#ifndef cpu_has_cache_cdex_p
#define cpu_has_cache_cdex_p	(cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
#endif
#ifndef cpu_has_cache_cdex_s
#define cpu_has_cache_cdex_s	(cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
#endif
#ifndef cpu_has_prefetch
#define cpu_has_prefetch	(cpu_data[0].options & MIPS_CPU_PREFETCH)
#endif
#ifndef cpu_has_mcheck
#define cpu_has_mcheck		(cpu_data[0].options & MIPS_CPU_MCHECK)
#endif
#ifndef cpu_has_ejtag
#define cpu_has_ejtag		(cpu_data[0].options & MIPS_CPU_EJTAG)
#endif
#ifndef cpu_has_llsc
#define cpu_has_llsc		(cpu_data[0].options & MIPS_CPU_LLSC)
#endif
#ifndef kernel_uses_llsc
#define kernel_uses_llsc	cpu_has_llsc
#endif
#ifndef cpu_has_mips16
#define cpu_has_mips16		(cpu_data[0].ases & MIPS_ASE_MIPS16)
#endif
#ifndef cpu_has_mdmx
#define cpu_has_mdmx		(cpu_data[0].ases & MIPS_ASE_MDMX)
#endif
#ifndef cpu_has_mips3d
#define cpu_has_mips3d		(cpu_data[0].ases & MIPS_ASE_MIPS3D)
#endif
#ifndef cpu_has_smartmips
#define cpu_has_smartmips	(cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
#endif
#ifndef cpu_has_rixi
#define cpu_has_rixi		(cpu_data[0].options & MIPS_CPU_RIXI)
#endif
#ifndef cpu_has_mmips
# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
#  define cpu_has_mmips		(cpu_data[0].options & MIPS_CPU_MICROMIPS)
# else
#  define cpu_has_mmips		0
# endif
#endif
#ifndef cpu_has_vtag_icache
#define cpu_has_vtag_icache	(cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
#endif
#ifndef cpu_has_dc_aliases
#define cpu_has_dc_aliases	(cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
#endif
#ifndef cpu_has_ic_fills_f_dc
#define cpu_has_ic_fills_f_dc	(cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
#endif
#ifndef cpu_has_pindexed_dcache
#define cpu_has_pindexed_dcache	(cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
#endif
#ifndef cpu_has_local_ebase
#define cpu_has_local_ebase	1
#endif

/*
 * I-Cache snoops remote store.	 This only matters on SMP.  Some multiprocessors
 * such as the R10000 have I-Caches that snoop local stores; the embedded ones
 * don't.  For maintaining I-cache coherency this means we need to flush the
 * D-cache all the way back to whever the I-cache does refills from, so the
 * I-cache has a chance to see the new data at all.  Then we have to flush the
 * I-cache also.
 * Note we may have been rescheduled and may no longer be running on the CPU
 * that did the store so we can't optimize this into only doing the flush on
 * the local CPU.
 */
#ifndef cpu_icache_snoops_remote_store
#ifdef CONFIG_SMP
#define cpu_icache_snoops_remote_store	(cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
#else
#define cpu_icache_snoops_remote_store	1
#endif
#endif

#ifndef cpu_has_mips_2
# define cpu_has_mips_2		(cpu_data[0].isa_level & MIPS_CPU_ISA_II)
#endif
#ifndef cpu_has_mips_3
# define cpu_has_mips_3		(cpu_data[0].isa_level & MIPS_CPU_ISA_III)
#endif
#ifndef cpu_has_mips_4
# define cpu_has_mips_4		(cpu_data[0].isa_level & MIPS_CPU_ISA_IV)
#endif
#ifndef cpu_has_mips_5
# define cpu_has_mips_5		(cpu_data[0].isa_level & MIPS_CPU_ISA_V)
#endif
#ifndef cpu_has_mips32r1
# define cpu_has_mips32r1	(cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
#endif
#ifndef cpu_has_mips32r2
# define cpu_has_mips32r2	(cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
#endif
#ifndef cpu_has_mips64r1
# define cpu_has_mips64r1	(cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
#endif
#ifndef cpu_has_mips64r2
# define cpu_has_mips64r2	(cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
#endif

/*
 * Shortcuts ...
 */
#define cpu_has_mips32	(cpu_has_mips32r1 | cpu_has_mips32r2)
#define cpu_has_mips64	(cpu_has_mips64r1 | cpu_has_mips64r2)
#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
#define cpu_has_mips_r	(cpu_has_mips32r1 | cpu_has_mips32r2 | \
			 cpu_has_mips64r1 | cpu_has_mips64r2)

#ifndef cpu_has_mips_r2_exec_hazard
#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2
#endif

/*
 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
 * pre-MIPS32/MIPS64 processors have CLO, CLZ.	The IDT RC64574 is 64-bit and
 * has CLO and CLZ but not DCLO nor DCLZ.  For 64-bit kernels
 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
 */
#ifndef cpu_has_clo_clz
#define cpu_has_clo_clz	cpu_has_mips_r
#endif

#ifndef cpu_has_dsp
#define cpu_has_dsp		(cpu_data[0].ases & MIPS_ASE_DSP)
#endif

#ifndef cpu_has_dsp2
#define cpu_has_dsp2		(cpu_data[0].ases & MIPS_ASE_DSP2P)
#endif

#ifndef cpu_has_mipsmt
#define cpu_has_mipsmt		(cpu_data[0].ases & MIPS_ASE_MIPSMT)
#endif

#ifndef cpu_has_userlocal
#define cpu_has_userlocal	(cpu_data[0].options & MIPS_CPU_ULRI)
#endif

#ifdef CONFIG_32BIT
# ifndef cpu_has_nofpuex
# define cpu_has_nofpuex	(cpu_data[0].options & MIPS_CPU_NOFPUEX)
# endif
# ifndef cpu_has_64bits
# define cpu_has_64bits		(cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
# endif
# ifndef cpu_has_64bit_zero_reg
# define cpu_has_64bit_zero_reg	(cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
# endif
# ifndef cpu_has_64bit_gp_regs
# define cpu_has_64bit_gp_regs		0
# endif
# ifndef cpu_has_64bit_addresses
# define cpu_has_64bit_addresses	0
# endif
# ifndef cpu_vmbits
# define cpu_vmbits 31
# endif
#endif

#ifdef CONFIG_64BIT
# ifndef cpu_has_nofpuex
# define cpu_has_nofpuex		0
# endif
# ifndef cpu_has_64bits
# define cpu_has_64bits			1
# endif
# ifndef cpu_has_64bit_zero_reg
# define cpu_has_64bit_zero_reg		1
# endif
# ifndef cpu_has_64bit_gp_regs
# define cpu_has_64bit_gp_regs		1
# endif
# ifndef cpu_has_64bit_addresses
# define cpu_has_64bit_addresses	1
# endif
# ifndef cpu_vmbits
# define cpu_vmbits cpu_data[0].vmbits
# define __NEED_VMBITS_PROBE
# endif
#endif

#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
# define cpu_has_vint		(cpu_data[0].options & MIPS_CPU_VINT)
#elif !defined(cpu_has_vint)
# define cpu_has_vint			0
#endif

#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
# define cpu_has_veic		(cpu_data[0].options & MIPS_CPU_VEIC)
#elif !defined(cpu_has_veic)
# define cpu_has_veic			0
#endif

#ifndef cpu_has_inclusive_pcaches
#define cpu_has_inclusive_pcaches	(cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
#endif

#ifndef cpu_dcache_line_size
#define cpu_dcache_line_size()	cpu_data[0].dcache.linesz
#endif
#ifndef cpu_icache_line_size
#define cpu_icache_line_size()	cpu_data[0].icache.linesz
#endif
#ifndef cpu_scache_line_size
#define cpu_scache_line_size()	cpu_data[0].scache.linesz
#endif

#ifndef cpu_hwrena_impl_bits
#define cpu_hwrena_impl_bits		0
#endif

#ifndef cpu_has_perf_cntr_intr_bit
#define cpu_has_perf_cntr_intr_bit	(cpu_data[0].options & MIPS_CPU_PCI)
#endif

#ifndef cpu_has_vz
#define cpu_has_vz		(cpu_data[0].ases & MIPS_ASE_VZ)
#endif

#endif /* __ASM_CPU_FEATURES_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2003, 2004 Ralf Baechle
4194318c	7	* Copyright (C) 2004 Maciej W. Rozycki
1da177e4 LT	8	*/
	9	#ifndef __ASM_CPU_FEATURES_H
	10	#define __ASM_CPU_FEATURES_H
	11
1da177e4 LT	12	#include <asm/cpu.h>
	13	#include <asm/cpu-info.h>
	14	#include <cpu-feature-overrides.h>
	15
	16	/*
	17	* SMP assumption: Options of CPU 0 are a superset of all processors.
	18	* This is true for all known MIPS systems.
	19	*/
	20	#ifndef cpu_has_tlb
	21	#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
	22	#endif
1990e542 RB	23
	24	/*
	25	* For the moment we don't consider R6000 and R8000 so we can assume that
	26	* anything that doesn't support R4000-style exceptions and interrupts is
	27	* R3000-like. Users should still treat these two macro definitions as
	28	* opaque.
	29	*/
	30	#ifndef cpu_has_3kex
	31	#define cpu_has_3kex (!cpu_has_4kex)
	32	#endif
1da177e4 LT	33	#ifndef cpu_has_4kex
	34	#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
	35	#endif
02cf2119 RB	36	#ifndef cpu_has_3k_cache
	37	#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
	38	#endif
	39	#define cpu_has_6k_cache 0
	40	#define cpu_has_8k_cache 0
	41	#ifndef cpu_has_4k_cache
	42	#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
	43	#endif
	44	#ifndef cpu_has_tx39_cache
	45	#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
	46	#endif
47d979ec DD	47	#ifndef cpu_has_octeon_cache
	48	#define cpu_has_octeon_cache 0
	49	#endif
1da177e4	50	#ifndef cpu_has_fpu
f088fc84	51	#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
53dc8028 AN	52	#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
	53	#else
	54	#define raw_cpu_has_fpu cpu_has_fpu
1da177e4 LT	55	#endif
	56	#ifndef cpu_has_32fpr
	57	#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
	58	#endif
	59	#ifndef cpu_has_counter
	60	#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
	61	#endif
	62	#ifndef cpu_has_watch
	63	#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
	64	#endif
1da177e4 LT	65	#ifndef cpu_has_divec
	66	#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
	67	#endif
	68	#ifndef cpu_has_vce
	69	#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
	70	#endif
	71	#ifndef cpu_has_cache_cdex_p
	72	#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
	73	#endif
	74	#ifndef cpu_has_cache_cdex_s
	75	#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
	76	#endif
	77	#ifndef cpu_has_prefetch
	78	#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
	79	#endif
	80	#ifndef cpu_has_mcheck
	81	#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
	82	#endif
	83	#ifndef cpu_has_ejtag
	84	#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
	85	#endif
	86	#ifndef cpu_has_llsc
	87	#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
	88	#endif
b791d119 DD	89	#ifndef kernel_uses_llsc
	90	#define kernel_uses_llsc cpu_has_llsc
	91	#endif
4194318c RB	92	#ifndef cpu_has_mips16
	93	#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
	94	#endif
	95	#ifndef cpu_has_mdmx
fc192e50	96	#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
4194318c RB	97	#endif
4194318c RB	98	#ifndef cpu_has_mips3d
fc192e50	99	#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
4194318c RB	100	#endif
4194318c RB	101	#ifndef cpu_has_smartmips
fc192e50	102	#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
4194318c	103	#endif
b2ab4f08 SH	104	#ifndef cpu_has_rixi
	105	#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
	106	#endif
f8fa4811	107	#ifndef cpu_has_mmips
3ddc14ad DD	108	# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
	109	# define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
	110	# else
	111	# define cpu_has_mmips 0
	112	# endif
f8fa4811	113	#endif
1da177e4 LT	114	#ifndef cpu_has_vtag_icache
	115	#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
	116	#endif
	117	#ifndef cpu_has_dc_aliases
	118	#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
	119	#endif
	120	#ifndef cpu_has_ic_fills_f_dc
	121	#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
	122	#endif
de62893b	123	#ifndef cpu_has_pindexed_dcache
fc192e50	124	#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
de62893b	125	#endif
8759934e HC	126	#ifndef cpu_has_local_ebase
	127	#define cpu_has_local_ebase 1
	128	#endif
1da177e4 LT	129
1da177e4 LT	130	/*
70342287	131	* I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
1da177e4 LT	132	* such as the R10000 have I-Caches that snoop local stores; the embedded ones
	133	* don't. For maintaining I-cache coherency this means we need to flush the
	134	* D-cache all the way back to whever the I-cache does refills from, so the
	135	* I-cache has a chance to see the new data at all. Then we have to flush the
	136	* I-cache also.
	137	* Note we may have been rescheduled and may no longer be running on the CPU
	138	* that did the store so we can't optimize this into only doing the flush on
	139	* the local CPU.
	140	*/
	141	#ifndef cpu_icache_snoops_remote_store
	142	#ifdef CONFIG_SMP
	143	#define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
	144	#else
	145	#define cpu_icache_snoops_remote_store 1
	146	#endif
	147	#endif
	148
a96102be SH	149	#ifndef cpu_has_mips_2
	150	# define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II)
	151	#endif
	152	#ifndef cpu_has_mips_3
	153	# define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III)
	154	#endif
	155	#ifndef cpu_has_mips_4
	156	# define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV)
	157	#endif
	158	#ifndef cpu_has_mips_5
	159	# define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
	160	#endif
fc192e50	161	#ifndef cpu_has_mips32r1
0401572a	162	# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
fc192e50 TW	163	#endif
fc192e50 TW	164	#ifndef cpu_has_mips32r2
0401572a	165	# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
fc192e50 TW	166	#endif
fc192e50 TW	167	#ifndef cpu_has_mips64r1
0401572a	168	# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
fc192e50 TW	169	#endif
fc192e50 TW	170	#ifndef cpu_has_mips64r2
0401572a	171	# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
fc192e50	172	#endif
0401572a RB	173
	174	/*
	175	* Shortcuts ...
	176	*/
	177	#define cpu_has_mips32 (cpu_has_mips32r1 \| cpu_has_mips32r2)
	178	#define cpu_has_mips64 (cpu_has_mips64r1 \| cpu_has_mips64r2)
70342287 RB	179	#define cpu_has_mips_r1 (cpu_has_mips32r1 \| cpu_has_mips64r1)
70342287 RB	180	#define cpu_has_mips_r2 (cpu_has_mips32r2 \| cpu_has_mips64r2)
c46b302b RB	181	#define cpu_has_mips_r (cpu_has_mips32r1 \| cpu_has_mips32r2 \| \
c46b302b RB	182	cpu_has_mips64r1 \| cpu_has_mips64r2)
0401572a	183
41f0e4d0 DD	184	#ifndef cpu_has_mips_r2_exec_hazard
	185	#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2
	186	#endif
	187
47740eb8 RB	188	/*
47740eb8 RB	189	* MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
becee6b8	190	* pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and
417a5eb0	191	* has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
47740eb8 RB	192	* cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
47740eb8 RB	193	*/
fc192e50 TW	194	#ifndef cpu_has_clo_clz
	195	#define cpu_has_clo_clz cpu_has_mips_r
	196	#endif
47740eb8	197
e50c0a8f RB	198	#ifndef cpu_has_dsp
	199	#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
	200	#endif
	201
ee80f7c7 SH	202	#ifndef cpu_has_dsp2
	203	#define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P)
	204	#endif
	205
8f40611d	206	#ifndef cpu_has_mipsmt
2e128ded	207	#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
8f40611d RB	208	#endif
8f40611d RB	209
a3692020 RB	210	#ifndef cpu_has_userlocal
	211	#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
	212	#endif
	213
875d43e7	214	#ifdef CONFIG_32BIT
1da177e4 LT	215	# ifndef cpu_has_nofpuex
	216	# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
	217	# endif
	218	# ifndef cpu_has_64bits
	219	# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
	220	# endif
	221	# ifndef cpu_has_64bit_zero_reg
fc192e50	222	# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
1da177e4 LT	223	# endif
	224	# ifndef cpu_has_64bit_gp_regs
	225	# define cpu_has_64bit_gp_regs 0
	226	# endif
	227	# ifndef cpu_has_64bit_addresses
	228	# define cpu_has_64bit_addresses 0
	229	# endif
91dfc423 GR	230	# ifndef cpu_vmbits
	231	# define cpu_vmbits 31
	232	# endif
1da177e4 LT	233	#endif
1da177e4 LT	234
875d43e7	235	#ifdef CONFIG_64BIT
1da177e4 LT	236	# ifndef cpu_has_nofpuex
	237	# define cpu_has_nofpuex 0
	238	# endif
	239	# ifndef cpu_has_64bits
	240	# define cpu_has_64bits 1
	241	# endif
	242	# ifndef cpu_has_64bit_zero_reg
	243	# define cpu_has_64bit_zero_reg 1
	244	# endif
	245	# ifndef cpu_has_64bit_gp_regs
	246	# define cpu_has_64bit_gp_regs 1
	247	# endif
	248	# ifndef cpu_has_64bit_addresses
	249	# define cpu_has_64bit_addresses 1
	250	# endif
91dfc423 GR	251	# ifndef cpu_vmbits
	252	# define cpu_vmbits cpu_data[0].vmbits
	253	# define __NEED_VMBITS_PROBE
	254	# endif
1da177e4 LT	255	#endif
1da177e4 LT	256
f41ae0b2 RB	257	#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
	258	# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
	259	#elif !defined(cpu_has_vint)
8f40611d	260	# define cpu_has_vint 0
f41ae0b2 RB	261	#endif
	262
	263	#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
	264	# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
	265	#elif !defined(cpu_has_veic)
8f40611d RB	266	# define cpu_has_veic 0
	267	#endif
	268
fc5d2d27 RB	269	#ifndef cpu_has_inclusive_pcaches
fc5d2d27 RB	270	#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
1da177e4 LT	271	#endif
	272
	273	#ifndef cpu_dcache_line_size
54fd6441	274	#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
1da177e4 LT	275	#endif
1da177e4 LT	276	#ifndef cpu_icache_line_size
54fd6441	277	#define cpu_icache_line_size() cpu_data[0].icache.linesz
1da177e4 LT	278	#endif
1da177e4 LT	279	#ifndef cpu_scache_line_size
54fd6441	280	#define cpu_scache_line_size() cpu_data[0].scache.linesz
1da177e4 LT	281	#endif
1da177e4 LT	282
fbeda19f DD	283	#ifndef cpu_hwrena_impl_bits
	284	#define cpu_hwrena_impl_bits 0
	285	#endif
	286
da4b62cd AC	287	#ifndef cpu_has_perf_cntr_intr_bit
	288	#define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI)
	289	#endif
	290
1e7decdb DD	291	#ifndef cpu_has_vz
	292	#define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ)
	293	#endif
	294
1da177e4	295	#endif /* __ASM_CPU_FEATURES_H */