[deliverable/linux.git] / arch / mips / include / asm / cpu-features.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2003, 2004 Ralf Baechle
 * Copyright (C) 2004  Maciej W. Rozycki
 */
#ifndef __ASM_CPU_FEATURES_H
#define __ASM_CPU_FEATURES_H

#include <asm/cpu.h>
#include <asm/cpu-info.h>
#include <cpu-feature-overrides.h>

#ifndef current_cpu_type
#define current_cpu_type()      current_cpu_data.cputype
#endif

/*
 * SMP assumption: Options of CPU 0 are a superset of all processors.
 * This is true for all known MIPS systems.
 */
#ifndef cpu_has_tlb
#define cpu_has_tlb		(cpu_data[0].options & MIPS_CPU_TLB)
#endif
#ifndef cpu_has_4kex
#define cpu_has_4kex		(cpu_data[0].options & MIPS_CPU_4KEX)
#endif
#ifndef cpu_has_3k_cache
#define cpu_has_3k_cache	(cpu_data[0].options & MIPS_CPU_3K_CACHE)
#endif
#define cpu_has_6k_cache	0
#define cpu_has_8k_cache	0
#ifndef cpu_has_4k_cache
#define cpu_has_4k_cache	(cpu_data[0].options & MIPS_CPU_4K_CACHE)
#endif
#ifndef cpu_has_tx39_cache
#define cpu_has_tx39_cache	(cpu_data[0].options & MIPS_CPU_TX39_CACHE)
#endif
#ifndef cpu_has_octeon_cache
#define cpu_has_octeon_cache	0
#endif
#ifndef cpu_has_fpu
#define cpu_has_fpu		(current_cpu_data.options & MIPS_CPU_FPU)
#define raw_cpu_has_fpu		(raw_current_cpu_data.options & MIPS_CPU_FPU)
#else
#define raw_cpu_has_fpu		cpu_has_fpu
#endif
#ifndef cpu_has_32fpr
#define cpu_has_32fpr		(cpu_data[0].options & MIPS_CPU_32FPR)
#endif
#ifndef cpu_has_counter
#define cpu_has_counter		(cpu_data[0].options & MIPS_CPU_COUNTER)
#endif
#ifndef cpu_has_watch
#define cpu_has_watch		(cpu_data[0].options & MIPS_CPU_WATCH)
#endif
#ifndef cpu_has_divec
#define cpu_has_divec		(cpu_data[0].options & MIPS_CPU_DIVEC)
#endif
#ifndef cpu_has_vce
#define cpu_has_vce		(cpu_data[0].options & MIPS_CPU_VCE)
#endif
#ifndef cpu_has_cache_cdex_p
#define cpu_has_cache_cdex_p	(cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
#endif
#ifndef cpu_has_cache_cdex_s
#define cpu_has_cache_cdex_s	(cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
#endif
#ifndef cpu_has_prefetch
#define cpu_has_prefetch	(cpu_data[0].options & MIPS_CPU_PREFETCH)
#endif
#ifndef cpu_has_mcheck
#define cpu_has_mcheck		(cpu_data[0].options & MIPS_CPU_MCHECK)
#endif
#ifndef cpu_has_ejtag
#define cpu_has_ejtag		(cpu_data[0].options & MIPS_CPU_EJTAG)
#endif
#ifndef cpu_has_llsc
#define cpu_has_llsc		(cpu_data[0].options & MIPS_CPU_LLSC)
#endif
#ifndef cpu_has_mips16
#define cpu_has_mips16		(cpu_data[0].ases & MIPS_ASE_MIPS16)
#endif
#ifndef cpu_has_mdmx
#define cpu_has_mdmx           (cpu_data[0].ases & MIPS_ASE_MDMX)
#endif
#ifndef cpu_has_mips3d
#define cpu_has_mips3d         (cpu_data[0].ases & MIPS_ASE_MIPS3D)
#endif
#ifndef cpu_has_smartmips
#define cpu_has_smartmips      (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
#endif
#ifndef cpu_has_vtag_icache
#define cpu_has_vtag_icache	(cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
#endif
#ifndef cpu_has_dc_aliases
#define cpu_has_dc_aliases	(cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
#endif
#ifndef cpu_has_ic_fills_f_dc
#define cpu_has_ic_fills_f_dc	(cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
#endif
#ifndef cpu_has_pindexed_dcache
#define cpu_has_pindexed_dcache	(cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
#endif

/*
 * I-Cache snoops remote store.  This only matters on SMP.  Some multiprocessors
 * such as the R10000 have I-Caches that snoop local stores; the embedded ones
 * don't.  For maintaining I-cache coherency this means we need to flush the
 * D-cache all the way back to whever the I-cache does refills from, so the
 * I-cache has a chance to see the new data at all.  Then we have to flush the
 * I-cache also.
 * Note we may have been rescheduled and may no longer be running on the CPU
 * that did the store so we can't optimize this into only doing the flush on
 * the local CPU.
 */
#ifndef cpu_icache_snoops_remote_store
#ifdef CONFIG_SMP
#define cpu_icache_snoops_remote_store	(cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
#else
#define cpu_icache_snoops_remote_store	1
#endif
#endif

# ifndef cpu_has_mips32r1
# define cpu_has_mips32r1	(cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
# endif
# ifndef cpu_has_mips32r2
# define cpu_has_mips32r2	(cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
# endif
# ifndef cpu_has_mips64r1
# define cpu_has_mips64r1	(cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
# endif
# ifndef cpu_has_mips64r2
# define cpu_has_mips64r2	(cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
# endif

/*
 * Shortcuts ...
 */
#define cpu_has_mips32	(cpu_has_mips32r1 | cpu_has_mips32r2)
#define cpu_has_mips64	(cpu_has_mips64r1 | cpu_has_mips64r2)
#define cpu_has_mips_r1	(cpu_has_mips32r1 | cpu_has_mips64r1)
#define cpu_has_mips_r2	(cpu_has_mips32r2 | cpu_has_mips64r2)
#define cpu_has_mips_r	(cpu_has_mips32r1 | cpu_has_mips32r2 | \
			 cpu_has_mips64r1 | cpu_has_mips64r2)

/*
 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
 * pre-MIPS32/MIPS53 processors have CLO, CLZ.  For 64-bit kernels
 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
 */
# ifndef cpu_has_clo_clz
# define cpu_has_clo_clz	cpu_has_mips_r
# endif

#ifndef cpu_has_dsp
#define cpu_has_dsp		(cpu_data[0].ases & MIPS_ASE_DSP)
#endif

#ifndef cpu_has_mipsmt
#define cpu_has_mipsmt		(cpu_data[0].ases & MIPS_ASE_MIPSMT)
#endif

#ifndef cpu_has_userlocal
#define cpu_has_userlocal	(cpu_data[0].options & MIPS_CPU_ULRI)
#endif

#ifdef CONFIG_32BIT
# ifndef cpu_has_nofpuex
# define cpu_has_nofpuex	(cpu_data[0].options & MIPS_CPU_NOFPUEX)
# endif
# ifndef cpu_has_64bits
# define cpu_has_64bits		(cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
# endif
# ifndef cpu_has_64bit_zero_reg
# define cpu_has_64bit_zero_reg	(cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
# endif
# ifndef cpu_has_64bit_gp_regs
# define cpu_has_64bit_gp_regs		0
# endif
# ifndef cpu_has_64bit_addresses
# define cpu_has_64bit_addresses	0
# endif
#endif

#ifdef CONFIG_64BIT
# ifndef cpu_has_nofpuex
# define cpu_has_nofpuex		0
# endif
# ifndef cpu_has_64bits
# define cpu_has_64bits			1
# endif
# ifndef cpu_has_64bit_zero_reg
# define cpu_has_64bit_zero_reg		1
# endif
# ifndef cpu_has_64bit_gp_regs
# define cpu_has_64bit_gp_regs		1
# endif
# ifndef cpu_has_64bit_addresses
# define cpu_has_64bit_addresses	1
# endif
#endif

#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
# define cpu_has_vint		(cpu_data[0].options & MIPS_CPU_VINT)
#elif !defined(cpu_has_vint)
# define cpu_has_vint			0
#endif

#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
# define cpu_has_veic		(cpu_data[0].options & MIPS_CPU_VEIC)
#elif !defined(cpu_has_veic)
# define cpu_has_veic			0
#endif

#ifndef cpu_has_inclusive_pcaches
#define cpu_has_inclusive_pcaches	(cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
#endif

#ifndef cpu_dcache_line_size
#define cpu_dcache_line_size()	cpu_data[0].dcache.linesz
#endif
#ifndef cpu_icache_line_size
#define cpu_icache_line_size()	cpu_data[0].icache.linesz
#endif
#ifndef cpu_scache_line_size
#define cpu_scache_line_size()	cpu_data[0].scache.linesz
#endif

#endif /* __ASM_CPU_FEATURES_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2003, 2004 Ralf Baechle
4194318c	7	* Copyright (C) 2004 Maciej W. Rozycki
1da177e4 LT	8	*/
	9	#ifndef __ASM_CPU_FEATURES_H
	10	#define __ASM_CPU_FEATURES_H
	11
1da177e4 LT	12	#include <asm/cpu.h>
	13	#include <asm/cpu-info.h>
	14	#include <cpu-feature-overrides.h>
	15
10cc3529 RB	16	#ifndef current_cpu_type
	17	#define current_cpu_type() current_cpu_data.cputype
	18	#endif
	19
1da177e4 LT	20	/*
	21	* SMP assumption: Options of CPU 0 are a superset of all processors.
	22	* This is true for all known MIPS systems.
	23	*/
	24	#ifndef cpu_has_tlb
	25	#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
	26	#endif
	27	#ifndef cpu_has_4kex
	28	#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
	29	#endif
02cf2119 RB	30	#ifndef cpu_has_3k_cache
	31	#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
	32	#endif
	33	#define cpu_has_6k_cache 0
	34	#define cpu_has_8k_cache 0
	35	#ifndef cpu_has_4k_cache
	36	#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
	37	#endif
	38	#ifndef cpu_has_tx39_cache
	39	#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
	40	#endif
47d979ec DD	41	#ifndef cpu_has_octeon_cache
	42	#define cpu_has_octeon_cache 0
	43	#endif
1da177e4	44	#ifndef cpu_has_fpu
f088fc84	45	#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
53dc8028 AN	46	#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
	47	#else
	48	#define raw_cpu_has_fpu cpu_has_fpu
1da177e4 LT	49	#endif
	50	#ifndef cpu_has_32fpr
	51	#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
	52	#endif
	53	#ifndef cpu_has_counter
	54	#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
	55	#endif
	56	#ifndef cpu_has_watch
	57	#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
	58	#endif
1da177e4 LT	59	#ifndef cpu_has_divec
	60	#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
	61	#endif
	62	#ifndef cpu_has_vce
	63	#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
	64	#endif
	65	#ifndef cpu_has_cache_cdex_p
	66	#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
	67	#endif
	68	#ifndef cpu_has_cache_cdex_s
	69	#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
	70	#endif
	71	#ifndef cpu_has_prefetch
	72	#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
	73	#endif
	74	#ifndef cpu_has_mcheck
	75	#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
	76	#endif
	77	#ifndef cpu_has_ejtag
	78	#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
	79	#endif
	80	#ifndef cpu_has_llsc
	81	#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
	82	#endif
4194318c RB	83	#ifndef cpu_has_mips16
	84	#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
	85	#endif
	86	#ifndef cpu_has_mdmx
	87	#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
	88	#endif
	89	#ifndef cpu_has_mips3d
	90	#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
	91	#endif
	92	#ifndef cpu_has_smartmips
	93	#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
	94	#endif
1da177e4 LT	95	#ifndef cpu_has_vtag_icache
	96	#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
	97	#endif
	98	#ifndef cpu_has_dc_aliases
	99	#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
	100	#endif
	101	#ifndef cpu_has_ic_fills_f_dc
	102	#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
	103	#endif
de62893b AN	104	#ifndef cpu_has_pindexed_dcache
	105	#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
	106	#endif
1da177e4 LT	107
	108	/*
	109	* I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
	110	* such as the R10000 have I-Caches that snoop local stores; the embedded ones
	111	* don't. For maintaining I-cache coherency this means we need to flush the
	112	* D-cache all the way back to whever the I-cache does refills from, so the
	113	* I-cache has a chance to see the new data at all. Then we have to flush the
	114	* I-cache also.
	115	* Note we may have been rescheduled and may no longer be running on the CPU
	116	* that did the store so we can't optimize this into only doing the flush on
	117	* the local CPU.
	118	*/
	119	#ifndef cpu_icache_snoops_remote_store
	120	#ifdef CONFIG_SMP
	121	#define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
	122	#else
	123	#define cpu_icache_snoops_remote_store 1
	124	#endif
	125	#endif
	126
0401572a RB	127	# ifndef cpu_has_mips32r1
	128	# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
	129	# endif
	130	# ifndef cpu_has_mips32r2
	131	# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
	132	# endif
	133	# ifndef cpu_has_mips64r1
	134	# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
	135	# endif
	136	# ifndef cpu_has_mips64r2
	137	# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
	138	# endif
	139
	140	/*
	141	* Shortcuts ...
	142	*/
	143	#define cpu_has_mips32 (cpu_has_mips32r1 \| cpu_has_mips32r2)
	144	#define cpu_has_mips64 (cpu_has_mips64r1 \| cpu_has_mips64r2)
	145	#define cpu_has_mips_r1 (cpu_has_mips32r1 \| cpu_has_mips64r1)
	146	#define cpu_has_mips_r2 (cpu_has_mips32r2 \| cpu_has_mips64r2)
c46b302b RB	147	#define cpu_has_mips_r (cpu_has_mips32r1 \| cpu_has_mips32r2 \| \
c46b302b RB	148	cpu_has_mips64r1 \| cpu_has_mips64r2)
0401572a	149
47740eb8 RB	150	/*
	151	* MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
	152	* pre-MIPS32/MIPS53 processors have CLO, CLZ. For 64-bit kernels
	153	* cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
	154	*/
	155	# ifndef cpu_has_clo_clz
	156	# define cpu_has_clo_clz cpu_has_mips_r
	157	# endif
	158
e50c0a8f RB	159	#ifndef cpu_has_dsp
	160	#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
	161	#endif
	162
8f40611d	163	#ifndef cpu_has_mipsmt
2e128ded	164	#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
8f40611d RB	165	#endif
8f40611d RB	166
a3692020 RB	167	#ifndef cpu_has_userlocal
	168	#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
	169	#endif
	170
875d43e7	171	#ifdef CONFIG_32BIT
1da177e4 LT	172	# ifndef cpu_has_nofpuex
	173	# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
	174	# endif
	175	# ifndef cpu_has_64bits
	176	# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
	177	# endif
	178	# ifndef cpu_has_64bit_zero_reg
	179	# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
	180	# endif
	181	# ifndef cpu_has_64bit_gp_regs
	182	# define cpu_has_64bit_gp_regs 0
	183	# endif
	184	# ifndef cpu_has_64bit_addresses
	185	# define cpu_has_64bit_addresses 0
	186	# endif
	187	#endif
	188
875d43e7	189	#ifdef CONFIG_64BIT
1da177e4 LT	190	# ifndef cpu_has_nofpuex
	191	# define cpu_has_nofpuex 0
	192	# endif
	193	# ifndef cpu_has_64bits
	194	# define cpu_has_64bits 1
	195	# endif
	196	# ifndef cpu_has_64bit_zero_reg
	197	# define cpu_has_64bit_zero_reg 1
	198	# endif
	199	# ifndef cpu_has_64bit_gp_regs
	200	# define cpu_has_64bit_gp_regs 1
	201	# endif
	202	# ifndef cpu_has_64bit_addresses
	203	# define cpu_has_64bit_addresses 1
	204	# endif
	205	#endif
	206
f41ae0b2 RB	207	#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
	208	# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
	209	#elif !defined(cpu_has_vint)
8f40611d	210	# define cpu_has_vint 0
f41ae0b2 RB	211	#endif
	212
	213	#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
	214	# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
	215	#elif !defined(cpu_has_veic)
8f40611d RB	216	# define cpu_has_veic 0
	217	#endif
	218
fc5d2d27 RB	219	#ifndef cpu_has_inclusive_pcaches
fc5d2d27 RB	220	#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
1da177e4 LT	221	#endif
	222
	223	#ifndef cpu_dcache_line_size
54fd6441	224	#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
1da177e4 LT	225	#endif
1da177e4 LT	226	#ifndef cpu_icache_line_size
54fd6441	227	#define cpu_icache_line_size() cpu_data[0].icache.linesz
1da177e4 LT	228	#endif
1da177e4 LT	229	#ifndef cpu_scache_line_size
54fd6441	230	#define cpu_scache_line_size() cpu_data[0].scache.linesz
1da177e4 LT	231	#endif
	232
	233	#endif /* __ASM_CPU_FEATURES_H */