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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1994 Waldorf GMBH | |
7 | * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle | |
8 | * Copyright (C) 1996 Paul M. Antoine | |
9 | * Copyright (C) 1999, 2000 Silicon Graphics, Inc. | |
4194318c | 10 | * Copyright (C) 2004 Maciej W. Rozycki |
1da177e4 LT |
11 | */ |
12 | #ifndef __ASM_CPU_INFO_H | |
13 | #define __ASM_CPU_INFO_H | |
14 | ||
6aa3524c DD |
15 | #include <linux/types.h> |
16 | ||
1da177e4 LT |
17 | #include <asm/cache.h> |
18 | ||
1da177e4 LT |
19 | /* |
20 | * Descriptor for a cache | |
21 | */ | |
22 | struct cache_desc { | |
1da177e4 | 23 | unsigned int waysize; /* Bytes per way */ |
6f2c3fa0 RB |
24 | unsigned short sets; /* Number of lines per set */ |
25 | unsigned char ways; /* Number of ways */ | |
26 | unsigned char linesz; /* Size of line in bytes */ | |
27 | unsigned char waybit; /* Bits to select in a cache set */ | |
28 | unsigned char flags; /* Flags describing cache properties */ | |
1da177e4 LT |
29 | }; |
30 | ||
6ad816e7 JH |
31 | struct guest_info { |
32 | unsigned long ases; | |
33 | unsigned long ases_dyn; | |
34 | unsigned long long options; | |
35 | unsigned long long options_dyn; | |
36 | u8 conf; | |
37 | u8 kscratch_mask; | |
38 | }; | |
39 | ||
1da177e4 LT |
40 | /* |
41 | * Flag definitions | |
42 | */ | |
43 | #define MIPS_CACHE_NOT_PRESENT 0x00000001 | |
44 | #define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */ | |
45 | #define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */ | |
46 | #define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */ | |
47 | #define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */ | |
de62893b | 48 | #define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */ |
1da177e4 LT |
49 | |
50 | struct cpuinfo_mips { | |
e5eb925a | 51 | unsigned long asid_cache; |
2db003a5 PB |
52 | #ifdef CONFIG_MIPS_ASID_BITS_VARIABLE |
53 | unsigned long asid_mask; | |
54 | #endif | |
1da177e4 LT |
55 | |
56 | /* | |
57 | * Capability and feature descriptor structure for MIPS CPU | |
58 | */ | |
4194318c | 59 | unsigned long ases; |
03a58777 | 60 | unsigned long long options; |
e5eb925a | 61 | unsigned int udelay_val; |
1da177e4 LT |
62 | unsigned int processor_id; |
63 | unsigned int fpu_id; | |
9b26616c MR |
64 | unsigned int fpu_csr31; |
65 | unsigned int fpu_msk31; | |
a5e9a69e | 66 | unsigned int msa_id; |
1da177e4 LT |
67 | unsigned int cputype; |
68 | int isa_level; | |
69 | int tlbsize; | |
75b5b5e0 LY |
70 | int tlbsizevtlb; |
71 | int tlbsizeftlbsets; | |
72 | int tlbsizeftlbways; | |
70342287 RB |
73 | struct cache_desc icache; /* Primary I-cache */ |
74 | struct cache_desc dcache; /* Primary D or combined I/D cache */ | |
b2edcfc8 | 75 | struct cache_desc vcache; /* Victim cache, between pcache and scache */ |
70342287 RB |
76 | struct cache_desc scache; /* Secondary cache */ |
77 | struct cache_desc tcache; /* Tertiary/split secondary cache */ | |
78 | int srsets; /* Shadow register sets */ | |
bda4584c | 79 | int package;/* physical package number */ |
0ab7aefc | 80 | int core; /* physical core number */ |
91dfc423 | 81 | #ifdef CONFIG_64BIT |
70342287 | 82 | int vmbits; /* Virtual memory size in bits */ |
91dfc423 | 83 | #endif |
5a3e7c02 | 84 | #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6) |
41c594ab | 85 | /* |
b633648c RB |
86 | * There is not necessarily a 1:1 mapping of VPE num to CPU number |
87 | * in particular on multi-core systems. | |
41c594ab | 88 | */ |
70342287 | 89 | int vpe_id; /* Virtual Processor number */ |
0ab7aefc | 90 | #endif |
70342287 | 91 | void *data; /* Additional data */ |
6aa3524c DD |
92 | unsigned int watch_reg_count; /* Number that exist */ |
93 | unsigned int watch_reg_use_cnt; /* Usable by ptrace */ | |
94 | #define NUM_WATCH_REGS 4 | |
95 | u16 watch_reg_masks[NUM_WATCH_REGS]; | |
e77c32fe | 96 | unsigned int kscratch_mask; /* Usable KScratch mask. */ |
4f12b91d MC |
97 | /* |
98 | * Cache Coherency attribute for write-combine memory writes. | |
99 | * (shifted by _CACHE_SHIFT) | |
100 | */ | |
101 | unsigned int writecombine; | |
ed4cbc81 MC |
102 | /* |
103 | * Simple counter to prevent enabling HTW in nested | |
104 | * htw_start/htw_stop calls | |
105 | */ | |
106 | unsigned int htw_seq; | |
6ad816e7 JH |
107 | |
108 | /* VZ & Guest features */ | |
109 | struct guest_info guest; | |
110 | unsigned int gtoffset_mask; | |
111 | unsigned int guestid_mask; | |
1da177e4 LT |
112 | } __attribute__((aligned(SMP_CACHE_BYTES))); |
113 | ||
114 | extern struct cpuinfo_mips cpu_data[]; | |
115 | #define current_cpu_data cpu_data[smp_processor_id()] | |
53dc8028 | 116 | #define raw_current_cpu_data cpu_data[raw_smp_processor_id()] |
c5f66596 | 117 | #define boot_cpu_data cpu_data[0] |
1da177e4 LT |
118 | |
119 | extern void cpu_probe(void); | |
120 | extern void cpu_report(void); | |
121 | ||
9966db25 | 122 | extern const char *__cpu_name[]; |
e95008a1 | 123 | #define cpu_name_string() __cpu_name[raw_smp_processor_id()] |
9966db25 | 124 | |
d6d3c9af RB |
125 | struct seq_file; |
126 | struct notifier_block; | |
127 | ||
128 | extern int register_proc_cpuinfo_notifier(struct notifier_block *nb); | |
129 | extern int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v); | |
130 | ||
131 | #define proc_cpuinfo_notifier(fn, pri) \ | |
132 | ({ \ | |
133 | static struct notifier_block fn##_nb = { \ | |
134 | .notifier_call = fn, \ | |
135 | .priority = pri \ | |
136 | }; \ | |
137 | \ | |
138 | register_proc_cpuinfo_notifier(&fn##_nb); \ | |
139 | }) | |
140 | ||
141 | struct proc_cpuinfo_notifier_args { | |
142 | struct seq_file *m; | |
143 | unsigned long n; | |
144 | }; | |
145 | ||
5a3e7c02 | 146 | #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6) |
b86c2247 PB |
147 | # define cpu_vpe_id(cpuinfo) ((cpuinfo)->vpe_id) |
148 | #else | |
34bd3e6b | 149 | # define cpu_vpe_id(cpuinfo) ({ (void)cpuinfo; 0; }) |
b86c2247 PB |
150 | #endif |
151 | ||
4edf00a4 PB |
152 | static inline unsigned long cpu_asid_inc(void) |
153 | { | |
154 | return 1 << CONFIG_MIPS_ASID_SHIFT; | |
155 | } | |
156 | ||
157 | static inline unsigned long cpu_asid_mask(struct cpuinfo_mips *cpuinfo) | |
158 | { | |
2db003a5 PB |
159 | #ifdef CONFIG_MIPS_ASID_BITS_VARIABLE |
160 | return cpuinfo->asid_mask; | |
161 | #endif | |
4edf00a4 PB |
162 | return ((1 << CONFIG_MIPS_ASID_BITS) - 1) << CONFIG_MIPS_ASID_SHIFT; |
163 | } | |
164 | ||
2db003a5 PB |
165 | static inline void set_cpu_asid_mask(struct cpuinfo_mips *cpuinfo, |
166 | unsigned long asid_mask) | |
167 | { | |
168 | #ifdef CONFIG_MIPS_ASID_BITS_VARIABLE | |
169 | cpuinfo->asid_mask = asid_mask; | |
170 | #endif | |
171 | } | |
172 | ||
1da177e4 | 173 | #endif /* __ASM_CPU_INFO_H */ |