projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * cpu.h: Values of the PRId register used to match up | |
| 3 | * various MIPS cpu types. | |
| 4 | * | |
| 79add627 | 5 | * Copyright (C) 1996 David S. Miller (davem@davemloft.net) |
| 4194318c | 6 | * Copyright (C) 2004 Maciej W. Rozycki |
| 1da177e4 LT |
7 | */ |
| 8 | #ifndef _ASM_CPU_H | |
| 9 | #define _ASM_CPU_H | |
| 10 | ||
| 11 | /* Assigned Company values for bits 23:16 of the PRId Register | |
| 12 | (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from | |
| 13 | MTI, the PRId register is defined in this (backwards compatible) | |
| 14 | way: | |
| 15 | ||
| 16 | +----------------+----------------+----------------+----------------+ | |
| 17 | | Company Options| Company ID | Processor ID | Revision | | |
| 18 | +----------------+----------------+----------------+----------------+ | |
| 19 | 31 24 23 16 15 8 7 | |
| 20 | ||
| 21 | I don't have docs for all the previous processors, but my impression is | |
| 22 | that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64 | |
| 23 | spec. | |
| 24 | */ | |
| 25 | ||
| 55a6feb6 RB |
26 | #define PRID_COMP_LEGACY 0x000000 |
| 27 | #define PRID_COMP_MIPS 0x010000 | |
| 28 | #define PRID_COMP_BROADCOM 0x020000 | |
| 29 | #define PRID_COMP_ALCHEMY 0x030000 | |
| 30 | #define PRID_COMP_SIBYTE 0x040000 | |
| 31 | #define PRID_COMP_SANDCRAFT 0x050000 | |
| a92b0588 | 32 | #define PRID_COMP_NXP 0x060000 |
| 55a6feb6 RB |
33 | #define PRID_COMP_TOSHIBA 0x070000 |
| 34 | #define PRID_COMP_LSI 0x080000 | |
| 35 | #define PRID_COMP_LEXRA 0x0b0000 | |
| a7117c6b | 36 | #define PRID_COMP_NETLOGIC 0x0c0000 |
| 0dd4781b | 37 | #define PRID_COMP_CAVIUM 0x0d0000 |
| 83ccf69d | 38 | #define PRID_COMP_INGENIC 0xd00000 |
| 1da177e4 LT |
39 | |
| 40 | /* | |
| 41 | * Assigned values for the product ID register. In order to detect a | |
| 42 | * certain CPU type exactly eventually additional registers may need to | |
| 43 | * be examined. These are valid when 23:16 == PRID_COMP_LEGACY | |
| 44 | */ | |
| 45 | #define PRID_IMP_R2000 0x0100 | |
| 46 | #define PRID_IMP_AU1_REV1 0x0100 | |
| 47 | #define PRID_IMP_AU1_REV2 0x0200 | |
| 48 | #define PRID_IMP_R3000 0x0200 /* Same as R2000A */ | |
| 49 | #define PRID_IMP_R6000 0x0300 /* Same as R3000A */ | |
| 50 | #define PRID_IMP_R4000 0x0400 | |
| 51 | #define PRID_IMP_R6000A 0x0600 | |
| 52 | #define PRID_IMP_R10000 0x0900 | |
| 53 | #define PRID_IMP_R4300 0x0b00 | |
| 54 | #define PRID_IMP_VR41XX 0x0c00 | |
| 55 | #define PRID_IMP_R12000 0x0e00 | |
| 44d921b2 | 56 | #define PRID_IMP_R14000 0x0f00 |
| 1da177e4 | 57 | #define PRID_IMP_R8000 0x1000 |
| bdf21b18 | 58 | #define PRID_IMP_PR4450 0x1200 |
| 1da177e4 LT |
59 | #define PRID_IMP_R4600 0x2000 |
| 60 | #define PRID_IMP_R4700 0x2100 | |
| 61 | #define PRID_IMP_TX39 0x2200 | |
| 62 | #define PRID_IMP_R4640 0x2200 | |
| 63 | #define PRID_IMP_R4650 0x2200 /* Same as R4640 */ | |
| 64 | #define PRID_IMP_R5000 0x2300 | |
| 65 | #define PRID_IMP_TX49 0x2d00 | |
| 66 | #define PRID_IMP_SONIC 0x2400 | |
| 67 | #define PRID_IMP_MAGIC 0x2500 | |
| 68 | #define PRID_IMP_RM7000 0x2700 | |
| 69 | #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */ | |
| 70 | #define PRID_IMP_RM9000 0x3400 | |
| 2954c02a | 71 | #define PRID_IMP_LOONGSON1 0x4200 |
| 1da177e4 LT |
72 | #define PRID_IMP_R5432 0x5400 |
| 73 | #define PRID_IMP_R5500 0x5500 | |
| 2954c02a | 74 | #define PRID_IMP_LOONGSON2 0x6300 |
| 98e316d4 MR |
75 | |
| 76 | #define PRID_IMP_UNKNOWN 0xff00 | |
| 77 | ||
| 78 | /* | |
| 79 | * These are the PRID's for when 23:16 == PRID_COMP_MIPS | |
| 80 | */ | |
| 81 | ||
| 1da177e4 LT |
82 | #define PRID_IMP_4KC 0x8000 |
| 83 | #define PRID_IMP_5KC 0x8100 | |
| 84 | #define PRID_IMP_20KC 0x8200 | |
| 85 | #define PRID_IMP_4KEC 0x8400 | |
| 86 | #define PRID_IMP_4KSC 0x8600 | |
| 87 | #define PRID_IMP_25KF 0x8800 | |
| 88 | #define PRID_IMP_5KE 0x8900 | |
| 89 | #define PRID_IMP_4KECR2 0x9000 | |
| 90 | #define PRID_IMP_4KEMPR2 0x9100 | |
| 91 | #define PRID_IMP_4KSD 0x9200 | |
| 92 | #define PRID_IMP_24K 0x9300 | |
| bbc7f22f | 93 | #define PRID_IMP_34K 0x9500 |
| e50c0a8f | 94 | #define PRID_IMP_24KE 0x9600 |
| c620953c | 95 | #define PRID_IMP_74K 0x9700 |
| 39b8d525 | 96 | #define PRID_IMP_1004K 0x9900 |
| 006a851b | 97 | #define PRID_IMP_1074K 0x9a00 |
| 113c62d9 | 98 | #define PRID_IMP_M14KC 0x9c00 |
| 1da177e4 | 99 | |
| 1da177e4 LT |
100 | /* |
| 101 | * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE | |
| 102 | */ | |
| 103 | ||
| 104 | #define PRID_IMP_SB1 0x0100 | |
| 93ce2f52 | 105 | #define PRID_IMP_SB1A 0x1100 |
| 1da177e4 LT |
106 | |
| 107 | /* | |
| 108 | * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT | |
| 109 | */ | |
| 110 | ||
| 111 | #define PRID_IMP_SR71000 0x0400 | |
| 112 | ||
| 1c0c13eb AJ |
113 | /* |
| 114 | * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM | |
| 115 | */ | |
| 116 | ||
| 190fca3e KC |
117 | #define PRID_IMP_BMIPS32_REV4 0x4000 |
| 118 | #define PRID_IMP_BMIPS32_REV8 0x8000 | |
| 602977b0 KC |
119 | #define PRID_IMP_BMIPS3300 0x9000 |
| 120 | #define PRID_IMP_BMIPS3300_ALT 0x9100 | |
| 121 | #define PRID_IMP_BMIPS3300_BUG 0x0000 | |
| 122 | #define PRID_IMP_BMIPS43XX 0xa000 | |
| 123 | #define PRID_IMP_BMIPS5000 0x5a00 | |
| 124 | ||
| 125 | #define PRID_REV_BMIPS4380_LO 0x0040 | |
| 126 | #define PRID_REV_BMIPS4380_HI 0x006f | |
| 1c0c13eb | 127 | |
| 0dd4781b DD |
128 | /* |
| 129 | * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM | |
| 130 | */ | |
| 131 | ||
| 132 | #define PRID_IMP_CAVIUM_CN38XX 0x0000 | |
| 133 | #define PRID_IMP_CAVIUM_CN31XX 0x0100 | |
| 134 | #define PRID_IMP_CAVIUM_CN30XX 0x0200 | |
| 135 | #define PRID_IMP_CAVIUM_CN58XX 0x0300 | |
| 136 | #define PRID_IMP_CAVIUM_CN56XX 0x0400 | |
| 137 | #define PRID_IMP_CAVIUM_CN50XX 0x0600 | |
| 138 | #define PRID_IMP_CAVIUM_CN52XX 0x0700 | |
| 1584d7f2 | 139 | #define PRID_IMP_CAVIUM_CN63XX 0x9000 |
| 074ef0d2 DD |
140 | #define PRID_IMP_CAVIUM_CN68XX 0x9100 |
| 141 | #define PRID_IMP_CAVIUM_CN66XX 0x9200 | |
| 142 | #define PRID_IMP_CAVIUM_CN61XX 0x9300 | |
| 0dd4781b | 143 | |
| 83ccf69d LPC |
144 | /* |
| 145 | * These are the PRID's for when 23:16 == PRID_COMP_INGENIC | |
| 146 | */ | |
| 147 | ||
| 148 | #define PRID_IMP_JZRISC 0x0200 | |
| 149 | ||
| a7117c6b J |
150 | /* |
| 151 | * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC | |
| 152 | */ | |
| 153 | #define PRID_IMP_NETLOGIC_XLR732 0x0000 | |
| 154 | #define PRID_IMP_NETLOGIC_XLR716 0x0200 | |
| 155 | #define PRID_IMP_NETLOGIC_XLR532 0x0900 | |
| 156 | #define PRID_IMP_NETLOGIC_XLR308 0x0600 | |
| 157 | #define PRID_IMP_NETLOGIC_XLR532C 0x0800 | |
| 158 | #define PRID_IMP_NETLOGIC_XLR516C 0x0a00 | |
| 159 | #define PRID_IMP_NETLOGIC_XLR508C 0x0b00 | |
| 160 | #define PRID_IMP_NETLOGIC_XLR308C 0x0f00 | |
| 161 | #define PRID_IMP_NETLOGIC_XLS608 0x8000 | |
| 162 | #define PRID_IMP_NETLOGIC_XLS408 0x8800 | |
| 163 | #define PRID_IMP_NETLOGIC_XLS404 0x8c00 | |
| 164 | #define PRID_IMP_NETLOGIC_XLS208 0x8e00 | |
| 165 | #define PRID_IMP_NETLOGIC_XLS204 0x8f00 | |
| 166 | #define PRID_IMP_NETLOGIC_XLS108 0xce00 | |
| 167 | #define PRID_IMP_NETLOGIC_XLS104 0xcf00 | |
| 168 | #define PRID_IMP_NETLOGIC_XLS616B 0x4000 | |
| 169 | #define PRID_IMP_NETLOGIC_XLS608B 0x4a00 | |
| 170 | #define PRID_IMP_NETLOGIC_XLS416B 0x4400 | |
| 171 | #define PRID_IMP_NETLOGIC_XLS412B 0x4c00 | |
| 172 | #define PRID_IMP_NETLOGIC_XLS408B 0x4e00 | |
| 173 | #define PRID_IMP_NETLOGIC_XLS404B 0x4f00 | |
| 809f36c6 | 174 | #define PRID_IMP_NETLOGIC_AU13XX 0x8000 |
| a7117c6b | 175 | |
| 2aa54b20 J |
176 | #define PRID_IMP_NETLOGIC_XLP8XX 0x1000 |
| 177 | #define PRID_IMP_NETLOGIC_XLP3XX 0x1100 | |
| a7117c6b | 178 | |
| 1da177e4 LT |
179 | /* |
| 180 | * Definitions for 7:0 on legacy processors | |
| 181 | */ | |
| 182 | ||
| 9267a30d | 183 | #define PRID_REV_MASK 0x00ff |
| 1da177e4 LT |
184 | |
| 185 | #define PRID_REV_TX4927 0x0022 | |
| 186 | #define PRID_REV_TX4937 0x0030 | |
| 187 | #define PRID_REV_R4400 0x0040 | |
| 188 | #define PRID_REV_R3000A 0x0030 | |
| 189 | #define PRID_REV_R3000 0x0020 | |
| 190 | #define PRID_REV_R2000A 0x0010 | |
| 191 | #define PRID_REV_TX3912 0x0010 | |
| 192 | #define PRID_REV_TX3922 0x0030 | |
| 193 | #define PRID_REV_TX3927 0x0040 | |
| 194 | #define PRID_REV_VR4111 0x0050 | |
| 195 | #define PRID_REV_VR4181 0x0050 /* Same as VR4111 */ | |
| 196 | #define PRID_REV_VR4121 0x0060 | |
| 197 | #define PRID_REV_VR4122 0x0070 | |
| 198 | #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ | |
| 199 | #define PRID_REV_VR4130 0x0080 | |
| 9267a30d | 200 | #define PRID_REV_34K_V1_0_2 0x0022 |
| 2fa36399 | 201 | #define PRID_REV_LOONGSON1B 0x0020 |
| f8ede0f7 WZ |
202 | #define PRID_REV_LOONGSON2E 0x0002 |
| 203 | #define PRID_REV_LOONGSON2F 0x0003 | |
| 1da177e4 | 204 | |
| fde97822 RB |
205 | /* |
| 206 | * Older processors used to encode processor version and revision in two | |
| 207 | * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores | |
| 208 | * have switched to use the 8-bits as 3:3:2 bitfield with the last field as | |
| 209 | * the patch number. *ARGH* | |
| 210 | */ | |
| 211 | #define PRID_REV_ENCODE_44(ver, rev) \ | |
| 212 | ((ver) << 4 | (rev)) | |
| 213 | #define PRID_REV_ENCODE_332(ver, rev, patch) \ | |
| 214 | ((ver) << 5 | (rev) << 2 | (patch)) | |
| 215 | ||
| 1da177e4 LT |
216 | /* |
| 217 | * FPU implementation/revision register (CP1 control register 0). | |
| 218 | * | |
| 219 | * +---------------------------------+----------------+----------------+ | |
| 220 | * | 0 | Implementation | Revision | | |
| 221 | * +---------------------------------+----------------+----------------+ | |
| 222 | * 31 16 15 8 7 0 | |
| 223 | */ | |
| 224 | ||
| 225 | #define FPIR_IMP_NONE 0x0000 | |
| 226 | ||
| 36cfbaad RB |
227 | enum cpu_type_enum { |
| 228 | CPU_UNKNOWN, | |
| 229 | ||
| 230 | /* | |
| 231 | * R2000 class processors | |
| 232 | */ | |
| 233 | CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052, | |
| 234 | CPU_R3081, CPU_R3081E, | |
| 235 | ||
| 236 | /* | |
| 237 | * R6000 class processors | |
| 238 | */ | |
| 239 | CPU_R6000, CPU_R6000A, | |
| 240 | ||
| 241 | /* | |
| 242 | * R4000 class processors | |
| 243 | */ | |
| 244 | CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310, | |
| 245 | CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650, | |
| fb2b1dba RB |
246 | CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000, |
| 247 | CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, CPU_VR4122, | |
| 248 | CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000, | |
| 36cfbaad RB |
249 | CPU_SR71000, CPU_RM9000, CPU_TX49XX, |
| 250 | ||
| 251 | /* | |
| 252 | * R8000 class processors | |
| 253 | */ | |
| 254 | CPU_R8000, | |
| 255 | ||
| 256 | /* | |
| 257 | * TX3900 class processors | |
| 258 | */ | |
| 259 | CPU_TX3912, CPU_TX3922, CPU_TX3927, | |
| 260 | ||
| 261 | /* | |
| 262 | * MIPS32 class processors | |
| 263 | */ | |
| 39b8d525 | 264 | CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, |
| 602977b0 | 265 | CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, |
| 2fa36399 | 266 | CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC, |
| 36cfbaad RB |
267 | |
| 268 | /* | |
| 269 | * MIPS64 class processors | |
| 270 | */ | |
| 78d4803f | 271 | CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, |
| 1584d7f2 | 272 | CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, |
| a3d4fb2d | 273 | CPU_XLR, CPU_XLP, |
| 36cfbaad RB |
274 | |
| 275 | CPU_LAST | |
| 276 | }; | |
| 277 | ||
| 1da177e4 LT |
278 | |
| 279 | /* | |
| 280 | * ISA Level encodings | |
| 281 | * | |
| 282 | */ | |
| 283 | #define MIPS_CPU_ISA_I 0x00000001 | |
| 284 | #define MIPS_CPU_ISA_II 0x00000002 | |
| 9cf8ff96 MR |
285 | #define MIPS_CPU_ISA_III 0x00000004 |
| 286 | #define MIPS_CPU_ISA_IV 0x00000008 | |
| 287 | #define MIPS_CPU_ISA_V 0x00000010 | |
| e7958bb9 | 288 | #define MIPS_CPU_ISA_M32R1 0x00000020 |
| b4672d37 | 289 | #define MIPS_CPU_ISA_M32R2 0x00000040 |
| 0401572a RB |
290 | #define MIPS_CPU_ISA_M64R1 0x00000080 |
| 291 | #define MIPS_CPU_ISA_M64R2 0x00000100 | |
| 292 | ||
| 293 | #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \ | |
| 113c62d9 | 294 | MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2) |
| 0401572a RB |
295 | #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ |
| 296 | MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2) | |
| 1da177e4 LT |
297 | |
| 298 | /* | |
| 299 | * CPU Option encodings | |
| 300 | */ | |
| 301 | #define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */ | |
| 02cf2119 RB |
302 | #define MIPS_CPU_4KEX 0x00000002 /* "R4K" exception model */ |
| 303 | #define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */ | |
| 304 | #define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */ | |
| 305 | #define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */ | |
| 641e97f3 RB |
306 | #define MIPS_CPU_FPU 0x00000020 /* CPU has FPU */ |
| 307 | #define MIPS_CPU_32FPR 0x00000040 /* 32 dbl. prec. FP registers */ | |
| 308 | #define MIPS_CPU_COUNTER 0x00000080 /* Cycle count/compare */ | |
| 309 | #define MIPS_CPU_WATCH 0x00000100 /* watchpoint registers */ | |
| 310 | #define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */ | |
| 311 | #define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */ | |
| 312 | #define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */ | |
| 313 | #define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */ | |
| 314 | #define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */ | |
| 315 | #define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */ | |
| 316 | #define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */ | |
| 317 | #define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */ | |
| 318 | #define MIPS_CPU_INCLUSIVE_CACHES 0x00020000 /* P-cache subset enforced */ | |
| 319 | #define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */ | |
| 320 | #define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */ | |
| 321 | #define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ | |
| 322 | #define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ | |
| da4b62cd AC |
323 | #define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */ |
| 324 | #define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */ | |
| 1da177e4 | 325 | |
| 4194318c RB |
326 | /* |
| 327 | * CPU ASE encodings | |
| 328 | */ | |
| 329 | #define MIPS_ASE_MIPS16 0x00000001 /* code compression */ | |
| 330 | #define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */ | |
| 331 | #define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */ | |
| 332 | #define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */ | |
| e50c0a8f | 333 | #define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ |
| 8f40611d | 334 | #define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ |
| ee80f7c7 | 335 | #define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */ |
| 8f40611d | 336 | |
| 4194318c | 337 | |
| 1da177e4 | 338 | #endif /* _ASM_CPU_H */ |