[deliverable/linux.git] / arch / mips / include / asm / cpu.h

/*
 * cpu.h: Values of the PRId register used to match up
 *	  various MIPS cpu types.
 *
 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
 * Copyright (C) 2004  Maciej W. Rozycki
 */
#ifndef _ASM_CPU_H
#define _ASM_CPU_H

/* Assigned Company values for bits 23:16 of the PRId Register
   (CP0 register 15, select 0).	 As of the MIPS32 and MIPS64 specs from
   MTI, the PRId register is defined in this (backwards compatible)
   way:

  +----------------+----------------+----------------+----------------+
  | Company Options| Company ID	    | Processor ID   | Revision	      |
  +----------------+----------------+----------------+----------------+
   31		 24 23		  16 15		    8 7

   I don't have docs for all the previous processors, but my impression is
   that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
   spec.
*/

#define PRID_COMP_LEGACY	0x000000
#define PRID_COMP_MIPS		0x010000
#define PRID_COMP_BROADCOM	0x020000
#define PRID_COMP_ALCHEMY	0x030000
#define PRID_COMP_SIBYTE	0x040000
#define PRID_COMP_SANDCRAFT	0x050000
#define PRID_COMP_NXP		0x060000
#define PRID_COMP_TOSHIBA	0x070000
#define PRID_COMP_LSI		0x080000
#define PRID_COMP_LEXRA		0x0b0000
#define PRID_COMP_NETLOGIC	0x0c0000
#define PRID_COMP_CAVIUM	0x0d0000
#define PRID_COMP_INGENIC	0xd00000

/*
 * Assigned values for the product ID register.	 In order to detect a
 * certain CPU type exactly eventually additional registers may need to
 * be examined.	 These are valid when 23:16 == PRID_COMP_LEGACY
 */
#define PRID_IMP_R2000		0x0100
#define PRID_IMP_AU1_REV1	0x0100
#define PRID_IMP_AU1_REV2	0x0200
#define PRID_IMP_R3000		0x0200		/* Same as R2000A  */
#define PRID_IMP_R6000		0x0300		/* Same as R3000A  */
#define PRID_IMP_R4000		0x0400
#define PRID_IMP_R6000A		0x0600
#define PRID_IMP_R10000		0x0900
#define PRID_IMP_R4300		0x0b00
#define PRID_IMP_VR41XX		0x0c00
#define PRID_IMP_R12000		0x0e00
#define PRID_IMP_R14000		0x0f00
#define PRID_IMP_R8000		0x1000
#define PRID_IMP_PR4450		0x1200
#define PRID_IMP_R4600		0x2000
#define PRID_IMP_R4700		0x2100
#define PRID_IMP_TX39		0x2200
#define PRID_IMP_R4640		0x2200
#define PRID_IMP_R4650		0x2200		/* Same as R4640 */
#define PRID_IMP_R5000		0x2300
#define PRID_IMP_TX49		0x2d00
#define PRID_IMP_SONIC		0x2400
#define PRID_IMP_MAGIC		0x2500
#define PRID_IMP_RM7000		0x2700
#define PRID_IMP_NEVADA		0x2800		/* RM5260 ??? */
#define PRID_IMP_RM9000		0x3400
#define PRID_IMP_LOONGSON1	0x4200
#define PRID_IMP_R5432		0x5400
#define PRID_IMP_R5500		0x5500
#define PRID_IMP_LOONGSON2	0x6300

#define PRID_IMP_UNKNOWN	0xff00

/*
 * These are the PRID's for when 23:16 == PRID_COMP_MIPS
 */

#define PRID_IMP_4KC		0x8000
#define PRID_IMP_5KC		0x8100
#define PRID_IMP_20KC		0x8200
#define PRID_IMP_4KEC		0x8400
#define PRID_IMP_4KSC		0x8600
#define PRID_IMP_25KF		0x8800
#define PRID_IMP_5KE		0x8900
#define PRID_IMP_4KECR2		0x9000
#define PRID_IMP_4KEMPR2	0x9100
#define PRID_IMP_4KSD		0x9200
#define PRID_IMP_24K		0x9300
#define PRID_IMP_34K		0x9500
#define PRID_IMP_24KE		0x9600
#define PRID_IMP_74K		0x9700
#define PRID_IMP_1004K		0x9900
#define PRID_IMP_1074K		0x9a00
#define PRID_IMP_M14KC		0x9c00
#define PRID_IMP_M14KEC		0x9e00

/*
 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
 */

#define PRID_IMP_SB1		0x0100
#define PRID_IMP_SB1A		0x1100

/*
 * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
 */

#define PRID_IMP_SR71000	0x0400

/*
 * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
 */

#define PRID_IMP_BMIPS32_REV4	0x4000
#define PRID_IMP_BMIPS32_REV8	0x8000
#define PRID_IMP_BMIPS3300	0x9000
#define PRID_IMP_BMIPS3300_ALT	0x9100
#define PRID_IMP_BMIPS3300_BUG	0x0000
#define PRID_IMP_BMIPS43XX	0xa000
#define PRID_IMP_BMIPS5000	0x5a00

#define PRID_REV_BMIPS4380_LO	0x0040
#define PRID_REV_BMIPS4380_HI	0x006f

/*
 * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
 */

#define PRID_IMP_CAVIUM_CN38XX 0x0000
#define PRID_IMP_CAVIUM_CN31XX 0x0100
#define PRID_IMP_CAVIUM_CN30XX 0x0200
#define PRID_IMP_CAVIUM_CN58XX 0x0300
#define PRID_IMP_CAVIUM_CN56XX 0x0400
#define PRID_IMP_CAVIUM_CN50XX 0x0600
#define PRID_IMP_CAVIUM_CN52XX 0x0700
#define PRID_IMP_CAVIUM_CN63XX 0x9000
#define PRID_IMP_CAVIUM_CN68XX 0x9100
#define PRID_IMP_CAVIUM_CN66XX 0x9200
#define PRID_IMP_CAVIUM_CN61XX 0x9300

/*
 * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
 */

#define PRID_IMP_JZRISC	       0x0200

/*
 * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
 */
#define PRID_IMP_NETLOGIC_XLR732	0x0000
#define PRID_IMP_NETLOGIC_XLR716	0x0200
#define PRID_IMP_NETLOGIC_XLR532	0x0900
#define PRID_IMP_NETLOGIC_XLR308	0x0600
#define PRID_IMP_NETLOGIC_XLR532C	0x0800
#define PRID_IMP_NETLOGIC_XLR516C	0x0a00
#define PRID_IMP_NETLOGIC_XLR508C	0x0b00
#define PRID_IMP_NETLOGIC_XLR308C	0x0f00
#define PRID_IMP_NETLOGIC_XLS608	0x8000
#define PRID_IMP_NETLOGIC_XLS408	0x8800
#define PRID_IMP_NETLOGIC_XLS404	0x8c00
#define PRID_IMP_NETLOGIC_XLS208	0x8e00
#define PRID_IMP_NETLOGIC_XLS204	0x8f00
#define PRID_IMP_NETLOGIC_XLS108	0xce00
#define PRID_IMP_NETLOGIC_XLS104	0xcf00
#define PRID_IMP_NETLOGIC_XLS616B	0x4000
#define PRID_IMP_NETLOGIC_XLS608B	0x4a00
#define PRID_IMP_NETLOGIC_XLS416B	0x4400
#define PRID_IMP_NETLOGIC_XLS412B	0x4c00
#define PRID_IMP_NETLOGIC_XLS408B	0x4e00
#define PRID_IMP_NETLOGIC_XLS404B	0x4f00
#define PRID_IMP_NETLOGIC_AU13XX	0x8000

#define PRID_IMP_NETLOGIC_XLP8XX	0x1000
#define PRID_IMP_NETLOGIC_XLP3XX	0x1100

/*
 * Definitions for 7:0 on legacy processors
 */

#define PRID_REV_MASK		0x00ff

#define PRID_REV_TX4927		0x0022
#define PRID_REV_TX4937		0x0030
#define PRID_REV_R4400		0x0040
#define PRID_REV_R3000A		0x0030
#define PRID_REV_R3000		0x0020
#define PRID_REV_R2000A		0x0010
#define PRID_REV_TX3912		0x0010
#define PRID_REV_TX3922		0x0030
#define PRID_REV_TX3927		0x0040
#define PRID_REV_VR4111		0x0050
#define PRID_REV_VR4181		0x0050	/* Same as VR4111 */
#define PRID_REV_VR4121		0x0060
#define PRID_REV_VR4122		0x0070
#define PRID_REV_VR4181A	0x0070	/* Same as VR4122 */
#define PRID_REV_VR4130		0x0080
#define PRID_REV_34K_V1_0_2	0x0022
#define PRID_REV_LOONGSON1B	0x0020
#define PRID_REV_LOONGSON2E	0x0002
#define PRID_REV_LOONGSON2F	0x0003

/*
 * Older processors used to encode processor version and revision in two
 * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
 * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
 * the patch number.  *ARGH*
 */
#define PRID_REV_ENCODE_44(ver, rev)					\
	((ver) << 4 | (rev))
#define PRID_REV_ENCODE_332(ver, rev, patch)				\
	((ver) << 5 | (rev) << 2 | (patch))

/*
 * FPU implementation/revision register (CP1 control register 0).
 *
 * +---------------------------------+----------------+----------------+
 * | 0				     | Implementation | Revision       |
 * +---------------------------------+----------------+----------------+
 *  31				   16 15	     8 7	      0
 */

#define FPIR_IMP_NONE		0x0000

enum cpu_type_enum {
	CPU_UNKNOWN,

	/*
	 * R2000 class processors
	 */
	CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052,
	CPU_R3081, CPU_R3081E,

	/*
	 * R6000 class processors
	 */
	CPU_R6000, CPU_R6000A,

	/*
	 * R4000 class processors
	 */
	CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
	CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
	CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000,
	CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, CPU_VR4122,
	CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
	CPU_SR71000, CPU_RM9000, CPU_TX49XX,

	/*
	 * R8000 class processors
	 */
	CPU_R8000,

	/*
	 * TX3900 class processors
	 */
	CPU_TX3912, CPU_TX3922, CPU_TX3927,

	/*
	 * MIPS32 class processors
	 */
	CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
	CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
	CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
	CPU_M14KEC,

	/*
	 * MIPS64 class processors
	 */
	CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
	CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
	CPU_XLR, CPU_XLP,

	CPU_LAST
};


/*
 * ISA Level encodings
 *
 */
#define MIPS_CPU_ISA_II		0x00000001
#define MIPS_CPU_ISA_III	0x00000002
#define MIPS_CPU_ISA_IV		0x00000004
#define MIPS_CPU_ISA_V		0x00000008
#define MIPS_CPU_ISA_M32R1	0x00000010
#define MIPS_CPU_ISA_M32R2	0x00000020
#define MIPS_CPU_ISA_M64R1	0x00000040
#define MIPS_CPU_ISA_M64R2	0x00000080

#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \
	MIPS_CPU_ISA_M32R2)
#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
	MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)

/*
 * CPU Option encodings
 */
#define MIPS_CPU_TLB		0x00000001 /* CPU has TLB */
#define MIPS_CPU_4KEX		0x00000002 /* "R4K" exception model */
#define MIPS_CPU_3K_CACHE	0x00000004 /* R3000-style caches */
#define MIPS_CPU_4K_CACHE	0x00000008 /* R4000-style caches */
#define MIPS_CPU_TX39_CACHE	0x00000010 /* TX3900-style caches */
#define MIPS_CPU_FPU		0x00000020 /* CPU has FPU */
#define MIPS_CPU_32FPR		0x00000040 /* 32 dbl. prec. FP registers */
#define MIPS_CPU_COUNTER	0x00000080 /* Cycle count/compare */
#define MIPS_CPU_WATCH		0x00000100 /* watchpoint registers */
#define MIPS_CPU_DIVEC		0x00000200 /* dedicated interrupt vector */
#define MIPS_CPU_VCE		0x00000400 /* virt. coherence conflict possible */
#define MIPS_CPU_CACHE_CDEX_P	0x00000800 /* Create_Dirty_Exclusive CACHE op */
#define MIPS_CPU_CACHE_CDEX_S	0x00001000 /* ... same for seconary cache ... */
#define MIPS_CPU_MCHECK		0x00002000 /* Machine check exception */
#define MIPS_CPU_EJTAG		0x00004000 /* EJTAG exception */
#define MIPS_CPU_NOFPUEX	0x00008000 /* no FPU exception */
#define MIPS_CPU_LLSC		0x00010000 /* CPU has ll/sc instructions */
#define MIPS_CPU_INCLUSIVE_CACHES	0x00020000 /* P-cache subset enforced */
#define MIPS_CPU_PREFETCH	0x00040000 /* CPU has usable prefetch */
#define MIPS_CPU_VINT		0x00080000 /* CPU supports MIPSR2 vectored interrupts */
#define MIPS_CPU_VEIC		0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
#define MIPS_CPU_ULRI		0x00200000 /* CPU has ULRI feature */
#define MIPS_CPU_PCI		0x00400000 /* CPU has Perf Ctr Int indicator */
#define MIPS_CPU_RIXI		0x00800000 /* CPU has TLB Read/eXec Inhibit */
#define MIPS_CPU_MICROMIPS	0x01000000 /* CPU has microMIPS capability */

/*
 * CPU ASE encodings
 */
#define MIPS_ASE_MIPS16		0x00000001 /* code compression */
#define MIPS_ASE_MDMX		0x00000002 /* MIPS digital media extension */
#define MIPS_ASE_MIPS3D		0x00000004 /* MIPS-3D */
#define MIPS_ASE_SMARTMIPS	0x00000008 /* SmartMIPS */
#define MIPS_ASE_DSP		0x00000010 /* Signal Processing ASE */
#define MIPS_ASE_MIPSMT		0x00000020 /* CPU supports MIPS MT */
#define MIPS_ASE_DSP2P		0x00000040 /* Signal Processing ASE Rev 2 */
#define MIPS_ASE_VZ		0x00000080 /* Virtualization ASE */

#endif /* _ASM_CPU_H */
Commit	Line	Data
1da177e4 LT	1	/*
1da177e4 LT	2	* cpu.h: Values of the PRId register used to match up
70342287	3	* various MIPS cpu types.
1da177e4	4	*
79add627	5	* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
4194318c	6	* Copyright (C) 2004 Maciej W. Rozycki
1da177e4 LT	7	*/
	8	#ifndef _ASM_CPU_H
	9	#define _ASM_CPU_H
	10
	11	/* Assigned Company values for bits 23:16 of the PRId Register
70342287	12	(CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from
1da177e4 LT	13	MTI, the PRId register is defined in this (backwards compatible)
	14	way:
	15
	16	+----------------+----------------+----------------+----------------+
70342287	17	\| Company Options\| Company ID \| Processor ID \| Revision \|
1da177e4	18	+----------------+----------------+----------------+----------------+
70342287	19	31 24 23 16 15 8 7
1da177e4 LT	20
	21	I don't have docs for all the previous processors, but my impression is
	22	that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
	23	spec.
	24	*/
	25
55a6feb6 RB	26	#define PRID_COMP_LEGACY 0x000000
	27	#define PRID_COMP_MIPS 0x010000
	28	#define PRID_COMP_BROADCOM 0x020000
	29	#define PRID_COMP_ALCHEMY 0x030000
	30	#define PRID_COMP_SIBYTE 0x040000
	31	#define PRID_COMP_SANDCRAFT 0x050000
70342287	32	#define PRID_COMP_NXP 0x060000
55a6feb6 RB	33	#define PRID_COMP_TOSHIBA 0x070000
	34	#define PRID_COMP_LSI 0x080000
	35	#define PRID_COMP_LEXRA 0x0b0000
a7117c6b	36	#define PRID_COMP_NETLOGIC 0x0c0000
0dd4781b	37	#define PRID_COMP_CAVIUM 0x0d0000
83ccf69d	38	#define PRID_COMP_INGENIC 0xd00000
1da177e4 LT	39
1da177e4 LT	40	/*
70342287	41	* Assigned values for the product ID register. In order to detect a
1da177e4	42	* certain CPU type exactly eventually additional registers may need to
70342287	43	* be examined. These are valid when 23:16 == PRID_COMP_LEGACY
1da177e4 LT	44	*/
	45	#define PRID_IMP_R2000 0x0100
	46	#define PRID_IMP_AU1_REV1 0x0100
	47	#define PRID_IMP_AU1_REV2 0x0200
	48	#define PRID_IMP_R3000 0x0200 /* Same as R2000A */
	49	#define PRID_IMP_R6000 0x0300 /* Same as R3000A */
	50	#define PRID_IMP_R4000 0x0400
	51	#define PRID_IMP_R6000A 0x0600
	52	#define PRID_IMP_R10000 0x0900
	53	#define PRID_IMP_R4300 0x0b00
	54	#define PRID_IMP_VR41XX 0x0c00
	55	#define PRID_IMP_R12000 0x0e00
44d921b2	56	#define PRID_IMP_R14000 0x0f00
1da177e4	57	#define PRID_IMP_R8000 0x1000
bdf21b18	58	#define PRID_IMP_PR4450 0x1200
1da177e4 LT	59	#define PRID_IMP_R4600 0x2000
	60	#define PRID_IMP_R4700 0x2100
	61	#define PRID_IMP_TX39 0x2200
	62	#define PRID_IMP_R4640 0x2200
	63	#define PRID_IMP_R4650 0x2200 /* Same as R4640 */
	64	#define PRID_IMP_R5000 0x2300
	65	#define PRID_IMP_TX49 0x2d00
	66	#define PRID_IMP_SONIC 0x2400
	67	#define PRID_IMP_MAGIC 0x2500
	68	#define PRID_IMP_RM7000 0x2700
	69	#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
	70	#define PRID_IMP_RM9000 0x3400
2954c02a	71	#define PRID_IMP_LOONGSON1 0x4200
1da177e4 LT	72	#define PRID_IMP_R5432 0x5400
1da177e4 LT	73	#define PRID_IMP_R5500 0x5500
2954c02a	74	#define PRID_IMP_LOONGSON2 0x6300
98e316d4 MR	75
	76	#define PRID_IMP_UNKNOWN 0xff00
	77
	78	/*
	79	* These are the PRID's for when 23:16 == PRID_COMP_MIPS
	80	*/
	81
1da177e4 LT	82	#define PRID_IMP_4KC 0x8000
	83	#define PRID_IMP_5KC 0x8100
	84	#define PRID_IMP_20KC 0x8200
	85	#define PRID_IMP_4KEC 0x8400
	86	#define PRID_IMP_4KSC 0x8600
	87	#define PRID_IMP_25KF 0x8800
	88	#define PRID_IMP_5KE 0x8900
	89	#define PRID_IMP_4KECR2 0x9000
	90	#define PRID_IMP_4KEMPR2 0x9100
	91	#define PRID_IMP_4KSD 0x9200
	92	#define PRID_IMP_24K 0x9300
bbc7f22f	93	#define PRID_IMP_34K 0x9500
e50c0a8f	94	#define PRID_IMP_24KE 0x9600
c620953c	95	#define PRID_IMP_74K 0x9700
39b8d525	96	#define PRID_IMP_1004K 0x9900
006a851b	97	#define PRID_IMP_1074K 0x9a00
113c62d9	98	#define PRID_IMP_M14KC 0x9c00
f8fa4811	99	#define PRID_IMP_M14KEC 0x9e00
1da177e4	100
1da177e4 LT	101	/*
	102	* These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
	103	*/
	104
70342287 RB	105	#define PRID_IMP_SB1 0x0100
70342287 RB	106	#define PRID_IMP_SB1A 0x1100
1da177e4 LT	107
	108	/*
	109	* These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
	110	*/
	111
70342287	112	#define PRID_IMP_SR71000 0x0400
1da177e4	113
1c0c13eb AJ	114	/*
	115	* These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
	116	*/
	117
190fca3e KC	118	#define PRID_IMP_BMIPS32_REV4 0x4000
190fca3e KC	119	#define PRID_IMP_BMIPS32_REV8 0x8000
602977b0 KC	120	#define PRID_IMP_BMIPS3300 0x9000
	121	#define PRID_IMP_BMIPS3300_ALT 0x9100
	122	#define PRID_IMP_BMIPS3300_BUG 0x0000
	123	#define PRID_IMP_BMIPS43XX 0xa000
	124	#define PRID_IMP_BMIPS5000 0x5a00
	125
	126	#define PRID_REV_BMIPS4380_LO 0x0040
	127	#define PRID_REV_BMIPS4380_HI 0x006f
1c0c13eb	128
0dd4781b DD	129	/*
	130	* These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
	131	*/
	132
	133	#define PRID_IMP_CAVIUM_CN38XX 0x0000
	134	#define PRID_IMP_CAVIUM_CN31XX 0x0100
	135	#define PRID_IMP_CAVIUM_CN30XX 0x0200
	136	#define PRID_IMP_CAVIUM_CN58XX 0x0300
	137	#define PRID_IMP_CAVIUM_CN56XX 0x0400
	138	#define PRID_IMP_CAVIUM_CN50XX 0x0600
	139	#define PRID_IMP_CAVIUM_CN52XX 0x0700
1584d7f2	140	#define PRID_IMP_CAVIUM_CN63XX 0x9000
074ef0d2 DD	141	#define PRID_IMP_CAVIUM_CN68XX 0x9100
	142	#define PRID_IMP_CAVIUM_CN66XX 0x9200
	143	#define PRID_IMP_CAVIUM_CN61XX 0x9300
0dd4781b	144
83ccf69d LPC	145	/*
	146	* These are the PRID's for when 23:16 == PRID_COMP_INGENIC
	147	*/
	148
70342287	149	#define PRID_IMP_JZRISC 0x0200
83ccf69d	150
a7117c6b J	151	/*
	152	* These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
	153	*/
	154	#define PRID_IMP_NETLOGIC_XLR732 0x0000
	155	#define PRID_IMP_NETLOGIC_XLR716 0x0200
	156	#define PRID_IMP_NETLOGIC_XLR532 0x0900
	157	#define PRID_IMP_NETLOGIC_XLR308 0x0600
	158	#define PRID_IMP_NETLOGIC_XLR532C 0x0800
	159	#define PRID_IMP_NETLOGIC_XLR516C 0x0a00
	160	#define PRID_IMP_NETLOGIC_XLR508C 0x0b00
	161	#define PRID_IMP_NETLOGIC_XLR308C 0x0f00
	162	#define PRID_IMP_NETLOGIC_XLS608 0x8000
	163	#define PRID_IMP_NETLOGIC_XLS408 0x8800
	164	#define PRID_IMP_NETLOGIC_XLS404 0x8c00
	165	#define PRID_IMP_NETLOGIC_XLS208 0x8e00
	166	#define PRID_IMP_NETLOGIC_XLS204 0x8f00
	167	#define PRID_IMP_NETLOGIC_XLS108 0xce00
	168	#define PRID_IMP_NETLOGIC_XLS104 0xcf00
	169	#define PRID_IMP_NETLOGIC_XLS616B 0x4000
	170	#define PRID_IMP_NETLOGIC_XLS608B 0x4a00
	171	#define PRID_IMP_NETLOGIC_XLS416B 0x4400
	172	#define PRID_IMP_NETLOGIC_XLS412B 0x4c00
	173	#define PRID_IMP_NETLOGIC_XLS408B 0x4e00
	174	#define PRID_IMP_NETLOGIC_XLS404B 0x4f00
809f36c6	175	#define PRID_IMP_NETLOGIC_AU13XX 0x8000
a7117c6b	176
2aa54b20 J	177	#define PRID_IMP_NETLOGIC_XLP8XX 0x1000
2aa54b20 J	178	#define PRID_IMP_NETLOGIC_XLP3XX 0x1100
a7117c6b	179
1da177e4 LT	180	/*
	181	* Definitions for 7:0 on legacy processors
	182	*/
	183
9267a30d	184	#define PRID_REV_MASK 0x00ff
1da177e4 LT	185
	186	#define PRID_REV_TX4927 0x0022
	187	#define PRID_REV_TX4937 0x0030
	188	#define PRID_REV_R4400 0x0040
	189	#define PRID_REV_R3000A 0x0030
	190	#define PRID_REV_R3000 0x0020
	191	#define PRID_REV_R2000A 0x0010
70342287 RB	192	#define PRID_REV_TX3912 0x0010
	193	#define PRID_REV_TX3922 0x0030
	194	#define PRID_REV_TX3927 0x0040
1da177e4 LT	195	#define PRID_REV_VR4111 0x0050
	196	#define PRID_REV_VR4181 0x0050 /* Same as VR4111 */
	197	#define PRID_REV_VR4121 0x0060
	198	#define PRID_REV_VR4122 0x0070
	199	#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
	200	#define PRID_REV_VR4130 0x0080
9267a30d	201	#define PRID_REV_34K_V1_0_2 0x0022
2fa36399	202	#define PRID_REV_LOONGSON1B 0x0020
f8ede0f7 WZ	203	#define PRID_REV_LOONGSON2E 0x0002
f8ede0f7 WZ	204	#define PRID_REV_LOONGSON2F 0x0003
1da177e4	205
fde97822 RB	206	/*
	207	* Older processors used to encode processor version and revision in two
	208	* 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
	209	* have switched to use the 8-bits as 3:3:2 bitfield with the last field as
	210	* the patch number. ARGH
	211	*/
	212	#define PRID_REV_ENCODE_44(ver, rev) \
	213	((ver) << 4 \| (rev))
	214	#define PRID_REV_ENCODE_332(ver, rev, patch) \
	215	((ver) << 5 \| (rev) << 2 \| (patch))
	216
1da177e4 LT	217	/*
	218	* FPU implementation/revision register (CP1 control register 0).
	219	*
	220	* +---------------------------------+----------------+----------------+
70342287	221	* \| 0 \| Implementation \| Revision \|
1da177e4	222	* +---------------------------------+----------------+----------------+
70342287	223	* 31 16 15 8 7 0
1da177e4 LT	224	*/
	225
	226	#define FPIR_IMP_NONE 0x0000
	227
36cfbaad RB	228	enum cpu_type_enum {
	229	CPU_UNKNOWN,
	230
	231	/*
	232	* R2000 class processors
	233	*/
	234	CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052,
	235	CPU_R3081, CPU_R3081E,
	236
	237	/*
	238	* R6000 class processors
	239	*/
	240	CPU_R6000, CPU_R6000A,
	241
	242	/*
	243	* R4000 class processors
	244	*/
	245	CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
	246	CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
fb2b1dba RB	247	CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000,
	248	CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, CPU_VR4122,
	249	CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
36cfbaad RB	250	CPU_SR71000, CPU_RM9000, CPU_TX49XX,
	251
	252	/*
	253	* R8000 class processors
	254	*/
	255	CPU_R8000,
	256
	257	/*
	258	* TX3900 class processors
	259	*/
	260	CPU_TX3912, CPU_TX3922, CPU_TX3927,
	261
	262	/*
	263	* MIPS32 class processors
	264	*/
39b8d525	265	CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
602977b0	266	CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
2fa36399	267	CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
f8fa4811	268	CPU_M14KEC,
36cfbaad RB	269
	270	/*
	271	* MIPS64 class processors
	272	*/
78d4803f	273	CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
1584d7f2	274	CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
a3d4fb2d	275	CPU_XLR, CPU_XLP,
36cfbaad RB	276
	277	CPU_LAST
	278	};
	279
1da177e4 LT	280
	281	/*
	282	* ISA Level encodings
	283	*
	284	*/
1990e542 RB	285	#define MIPS_CPU_ISA_II 0x00000001
	286	#define MIPS_CPU_ISA_III 0x00000002
	287	#define MIPS_CPU_ISA_IV 0x00000004
	288	#define MIPS_CPU_ISA_V 0x00000008
	289	#define MIPS_CPU_ISA_M32R1 0x00000010
	290	#define MIPS_CPU_ISA_M32R2 0x00000020
	291	#define MIPS_CPU_ISA_M64R1 0x00000040
	292	#define MIPS_CPU_ISA_M64R2 0x00000080
	293
	294	#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II \| MIPS_CPU_ISA_M32R1 \| \
	295	MIPS_CPU_ISA_M32R2)
0401572a RB	296	#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III \| MIPS_CPU_ISA_IV \| \
0401572a RB	297	MIPS_CPU_ISA_V \| MIPS_CPU_ISA_M64R1 \| MIPS_CPU_ISA_M64R2)
1da177e4 LT	298
	299	/*
	300	* CPU Option encodings
	301	*/
	302	#define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */
02cf2119 RB	303	#define MIPS_CPU_4KEX 0x00000002 /* "R4K" exception model */
	304	#define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */
	305	#define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */
	306	#define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */
641e97f3 RB	307	#define MIPS_CPU_FPU 0x00000020 /* CPU has FPU */
	308	#define MIPS_CPU_32FPR 0x00000040 /* 32 dbl. prec. FP registers */
	309	#define MIPS_CPU_COUNTER 0x00000080 /* Cycle count/compare */
	310	#define MIPS_CPU_WATCH 0x00000100 /* watchpoint registers */
	311	#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */
	312	#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */
	313	#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */
	314	#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */
	315	#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */
	316	#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */
	317	#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */
	318	#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */
	319	#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000 /* P-cache subset enforced */
	320	#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */
	321	#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */
	322	#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
	323	#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */
da4b62cd AC	324	#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */
da4b62cd AC	325	#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */
f8fa4811	326	#define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */
1da177e4	327
4194318c RB	328	/*
	329	* CPU ASE encodings
	330	*/
	331	#define MIPS_ASE_MIPS16 0x00000001 /* code compression */
	332	#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */
	333	#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */
	334	#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */
e50c0a8f	335	#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
8f40611d	336	#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */
ee80f7c7	337	#define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */
1e7decdb	338	#define MIPS_ASE_VZ 0x00000080 /* Virtualization ASE */
4194318c	339
1da177e4	340	#endif /* _ASM_CPU_H */