[deliverable/linux.git] / arch / mips / include / asm / cpu.h

/*
 * cpu.h: Values of the PRId register used to match up
 *	  various MIPS cpu types.
 *
 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
 * Copyright (C) 2004, 2013  Maciej W. Rozycki
 */
#ifndef _ASM_CPU_H
#define _ASM_CPU_H

/*
   As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0
   register 15, select 0) is defined in this (backwards compatible) way:

  +----------------+----------------+----------------+----------------+
  | Company Options| Company ID	    | Processor ID   | Revision	      |
  +----------------+----------------+----------------+----------------+
   31		 24 23		  16 15		    8 7

   I don't have docs for all the previous processors, but my impression is
   that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
   spec.
*/

#define PRID_OPT_MASK		0xff000000

/*
 * Assigned Company values for bits 23:16 of the PRId register.
 */

#define PRID_COMP_MASK		0xff0000

#define PRID_COMP_LEGACY	0x000000
#define PRID_COMP_MIPS		0x010000
#define PRID_COMP_BROADCOM	0x020000
#define PRID_COMP_ALCHEMY	0x030000
#define PRID_COMP_SIBYTE	0x040000
#define PRID_COMP_SANDCRAFT	0x050000
#define PRID_COMP_NXP		0x060000
#define PRID_COMP_TOSHIBA	0x070000
#define PRID_COMP_LSI		0x080000
#define PRID_COMP_LEXRA		0x0b0000
#define PRID_COMP_NETLOGIC	0x0c0000
#define PRID_COMP_CAVIUM	0x0d0000
#define PRID_COMP_INGENIC_D0	0xd00000	/* JZ4740, JZ4750 */
#define PRID_COMP_INGENIC_D1	0xd10000	/* JZ4770, JZ4775 */
#define PRID_COMP_INGENIC_E1	0xe10000	/* JZ4780 */

/*
 * Assigned Processor ID (implementation) values for bits 15:8 of the PRId
 * register.  In order to detect a certain CPU type exactly eventually
 * additional registers may need to be examined.
 */

#define PRID_IMP_MASK		0xff00

/*
 * These are valid when 23:16 == PRID_COMP_LEGACY
 */

#define PRID_IMP_R2000		0x0100
#define PRID_IMP_AU1_REV1	0x0100
#define PRID_IMP_AU1_REV2	0x0200
#define PRID_IMP_R3000		0x0200		/* Same as R2000A  */
#define PRID_IMP_R6000		0x0300		/* Same as R3000A  */
#define PRID_IMP_R4000		0x0400
#define PRID_IMP_R6000A		0x0600
#define PRID_IMP_R10000		0x0900
#define PRID_IMP_R4300		0x0b00
#define PRID_IMP_VR41XX		0x0c00
#define PRID_IMP_R12000		0x0e00
#define PRID_IMP_R14000		0x0f00		/* R14K && R16K */
#define PRID_IMP_R8000		0x1000
#define PRID_IMP_PR4450		0x1200
#define PRID_IMP_R4600		0x2000
#define PRID_IMP_R4700		0x2100
#define PRID_IMP_TX39		0x2200
#define PRID_IMP_R4640		0x2200
#define PRID_IMP_R4650		0x2200		/* Same as R4640 */
#define PRID_IMP_R5000		0x2300
#define PRID_IMP_TX49		0x2d00
#define PRID_IMP_SONIC		0x2400
#define PRID_IMP_MAGIC		0x2500
#define PRID_IMP_RM7000		0x2700
#define PRID_IMP_NEVADA		0x2800		/* RM5260 ??? */
#define PRID_IMP_RM9000		0x3400
#define PRID_IMP_LOONGSON_32	0x4200  /* Loongson-1 */
#define PRID_IMP_R5432		0x5400
#define PRID_IMP_R5500		0x5500
#define PRID_IMP_LOONGSON_64	0x6300  /* Loongson-2/3 */

#define PRID_IMP_UNKNOWN	0xff00

/*
 * These are the PRID's for when 23:16 == PRID_COMP_MIPS
 */

#define PRID_IMP_QEMU_GENERIC	0x0000
#define PRID_IMP_4KC		0x8000
#define PRID_IMP_5KC		0x8100
#define PRID_IMP_20KC		0x8200
#define PRID_IMP_4KEC		0x8400
#define PRID_IMP_4KSC		0x8600
#define PRID_IMP_25KF		0x8800
#define PRID_IMP_5KE		0x8900
#define PRID_IMP_4KECR2		0x9000
#define PRID_IMP_4KEMPR2	0x9100
#define PRID_IMP_4KSD		0x9200
#define PRID_IMP_24K		0x9300
#define PRID_IMP_34K		0x9500
#define PRID_IMP_24KE		0x9600
#define PRID_IMP_74K		0x9700
#define PRID_IMP_1004K		0x9900
#define PRID_IMP_1074K		0x9a00
#define PRID_IMP_M14KC		0x9c00
#define PRID_IMP_M14KEC		0x9e00
#define PRID_IMP_INTERAPTIV_UP	0xa000
#define PRID_IMP_INTERAPTIV_MP	0xa100
#define PRID_IMP_PROAPTIV_UP	0xa200
#define PRID_IMP_PROAPTIV_MP	0xa300
#define PRID_IMP_M5150		0xa700
#define PRID_IMP_P5600		0xa800
#define PRID_IMP_I6400		0xa900

/*
 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
 */

#define PRID_IMP_SB1		0x0100
#define PRID_IMP_SB1A		0x1100

/*
 * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
 */

#define PRID_IMP_SR71000	0x0400

/*
 * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
 */

#define PRID_IMP_BMIPS32_REV4	0x4000
#define PRID_IMP_BMIPS32_REV8	0x8000
#define PRID_IMP_BMIPS3300	0x9000
#define PRID_IMP_BMIPS3300_ALT	0x9100
#define PRID_IMP_BMIPS3300_BUG	0x0000
#define PRID_IMP_BMIPS43XX	0xa000
#define PRID_IMP_BMIPS5000	0x5a00
#define PRID_IMP_BMIPS5200	0x5b00

#define PRID_REV_BMIPS4380_LO	0x0040
#define PRID_REV_BMIPS4380_HI	0x006f

/*
 * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
 */

#define PRID_IMP_CAVIUM_CN38XX 0x0000
#define PRID_IMP_CAVIUM_CN31XX 0x0100
#define PRID_IMP_CAVIUM_CN30XX 0x0200
#define PRID_IMP_CAVIUM_CN58XX 0x0300
#define PRID_IMP_CAVIUM_CN56XX 0x0400
#define PRID_IMP_CAVIUM_CN50XX 0x0600
#define PRID_IMP_CAVIUM_CN52XX 0x0700
#define PRID_IMP_CAVIUM_CN63XX 0x9000
#define PRID_IMP_CAVIUM_CN68XX 0x9100
#define PRID_IMP_CAVIUM_CN66XX 0x9200
#define PRID_IMP_CAVIUM_CN61XX 0x9300
#define PRID_IMP_CAVIUM_CNF71XX 0x9400
#define PRID_IMP_CAVIUM_CN78XX 0x9500
#define PRID_IMP_CAVIUM_CN70XX 0x9600
#define PRID_IMP_CAVIUM_CN73XX 0x9700
#define PRID_IMP_CAVIUM_CNF75XX 0x9800

/*
 * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
 */

#define PRID_IMP_JZRISC	       0x0200

/*
 * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
 */
#define PRID_IMP_NETLOGIC_XLR732	0x0000
#define PRID_IMP_NETLOGIC_XLR716	0x0200
#define PRID_IMP_NETLOGIC_XLR532	0x0900
#define PRID_IMP_NETLOGIC_XLR308	0x0600
#define PRID_IMP_NETLOGIC_XLR532C	0x0800
#define PRID_IMP_NETLOGIC_XLR516C	0x0a00
#define PRID_IMP_NETLOGIC_XLR508C	0x0b00
#define PRID_IMP_NETLOGIC_XLR308C	0x0f00
#define PRID_IMP_NETLOGIC_XLS608	0x8000
#define PRID_IMP_NETLOGIC_XLS408	0x8800
#define PRID_IMP_NETLOGIC_XLS404	0x8c00
#define PRID_IMP_NETLOGIC_XLS208	0x8e00
#define PRID_IMP_NETLOGIC_XLS204	0x8f00
#define PRID_IMP_NETLOGIC_XLS108	0xce00
#define PRID_IMP_NETLOGIC_XLS104	0xcf00
#define PRID_IMP_NETLOGIC_XLS616B	0x4000
#define PRID_IMP_NETLOGIC_XLS608B	0x4a00
#define PRID_IMP_NETLOGIC_XLS416B	0x4400
#define PRID_IMP_NETLOGIC_XLS412B	0x4c00
#define PRID_IMP_NETLOGIC_XLS408B	0x4e00
#define PRID_IMP_NETLOGIC_XLS404B	0x4f00
#define PRID_IMP_NETLOGIC_AU13XX	0x8000

#define PRID_IMP_NETLOGIC_XLP8XX	0x1000
#define PRID_IMP_NETLOGIC_XLP3XX	0x1100
#define PRID_IMP_NETLOGIC_XLP2XX	0x1200
#define PRID_IMP_NETLOGIC_XLP9XX	0x1500
#define PRID_IMP_NETLOGIC_XLP5XX	0x1300

/*
 * Particular Revision values for bits 7:0 of the PRId register.
 */

#define PRID_REV_MASK		0x00ff

/*
 * Definitions for 7:0 on legacy processors
 */

#define PRID_REV_TX4927		0x0022
#define PRID_REV_TX4937		0x0030
#define PRID_REV_R4400		0x0040
#define PRID_REV_R3000A		0x0030
#define PRID_REV_R3000		0x0020
#define PRID_REV_R2000A		0x0010
#define PRID_REV_TX3912		0x0010
#define PRID_REV_TX3922		0x0030
#define PRID_REV_TX3927		0x0040
#define PRID_REV_VR4111		0x0050
#define PRID_REV_VR4181		0x0050	/* Same as VR4111 */
#define PRID_REV_VR4121		0x0060
#define PRID_REV_VR4122		0x0070
#define PRID_REV_VR4181A	0x0070	/* Same as VR4122 */
#define PRID_REV_VR4130		0x0080
#define PRID_REV_34K_V1_0_2	0x0022
#define PRID_REV_LOONGSON1B	0x0020
#define PRID_REV_LOONGSON2E	0x0002
#define PRID_REV_LOONGSON2F	0x0003
#define PRID_REV_LOONGSON3A	0x0005
#define PRID_REV_LOONGSON3B_R1	0x0006
#define PRID_REV_LOONGSON3B_R2	0x0007

/*
 * Older processors used to encode processor version and revision in two
 * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
 * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
 * the patch number.  *ARGH*
 */
#define PRID_REV_ENCODE_44(ver, rev)					\
	((ver) << 4 | (rev))
#define PRID_REV_ENCODE_332(ver, rev, patch)				\
	((ver) << 5 | (rev) << 2 | (patch))

/*
 * FPU implementation/revision register (CP1 control register 0).
 *
 * +---------------------------------+----------------+----------------+
 * | 0				     | Implementation | Revision       |
 * +---------------------------------+----------------+----------------+
 *  31				   16 15	     8 7	      0
 */

#define FPIR_IMP_MASK		0xff00

#define FPIR_IMP_NONE		0x0000

#if !defined(__ASSEMBLY__)

enum cpu_type_enum {
	CPU_UNKNOWN,

	/*
	 * R2000 class processors
	 */
	CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052,
	CPU_R3081, CPU_R3081E,

	/*
	 * R6000 class processors
	 */
	CPU_R6000, CPU_R6000A,

	/*
	 * R4000 class processors
	 */
	CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
	CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
	CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000,
	CPU_R12000, CPU_R14000, CPU_R16000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
	CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
	CPU_SR71000, CPU_TX49XX,

	/*
	 * R8000 class processors
	 */
	CPU_R8000,

	/*
	 * TX3900 class processors
	 */
	CPU_TX3912, CPU_TX3922, CPU_TX3927,

	/*
	 * MIPS32 class processors
	 */
	CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
	CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
	CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
	CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K, CPU_M5150,
	CPU_I6400,

	/*
	 * MIPS64 class processors
	 */
	CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
	CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
	CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP,

	CPU_QEMU_GENERIC,

	CPU_LAST
};

#endif /* !__ASSEMBLY */

/*
 * ISA Level encodings
 *
 */
#define MIPS_CPU_ISA_II		0x00000001
#define MIPS_CPU_ISA_III	0x00000002
#define MIPS_CPU_ISA_IV		0x00000004
#define MIPS_CPU_ISA_V		0x00000008
#define MIPS_CPU_ISA_M32R1	0x00000010
#define MIPS_CPU_ISA_M32R2	0x00000020
#define MIPS_CPU_ISA_M64R1	0x00000040
#define MIPS_CPU_ISA_M64R2	0x00000080
#define MIPS_CPU_ISA_M32R6	0x00000100
#define MIPS_CPU_ISA_M64R6	0x00000200

#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \
	MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M32R6)
#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
	MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2 | \
	MIPS_CPU_ISA_M64R6)

/*
 * CPU Option encodings
 */
#define MIPS_CPU_TLB		0x00000001ull /* CPU has TLB */
#define MIPS_CPU_4KEX		0x00000002ull /* "R4K" exception model */
#define MIPS_CPU_3K_CACHE	0x00000004ull /* R3000-style caches */
#define MIPS_CPU_4K_CACHE	0x00000008ull /* R4000-style caches */
#define MIPS_CPU_TX39_CACHE	0x00000010ull /* TX3900-style caches */
#define MIPS_CPU_FPU		0x00000020ull /* CPU has FPU */
#define MIPS_CPU_32FPR		0x00000040ull /* 32 dbl. prec. FP registers */
#define MIPS_CPU_COUNTER	0x00000080ull /* Cycle count/compare */
#define MIPS_CPU_WATCH		0x00000100ull /* watchpoint registers */
#define MIPS_CPU_DIVEC		0x00000200ull /* dedicated interrupt vector */
#define MIPS_CPU_VCE		0x00000400ull /* virt. coherence conflict possible */
#define MIPS_CPU_CACHE_CDEX_P	0x00000800ull /* Create_Dirty_Exclusive CACHE op */
#define MIPS_CPU_CACHE_CDEX_S	0x00001000ull /* ... same for seconary cache ... */
#define MIPS_CPU_MCHECK		0x00002000ull /* Machine check exception */
#define MIPS_CPU_EJTAG		0x00004000ull /* EJTAG exception */
#define MIPS_CPU_NOFPUEX	0x00008000ull /* no FPU exception */
#define MIPS_CPU_LLSC		0x00010000ull /* CPU has ll/sc instructions */
#define MIPS_CPU_INCLUSIVE_CACHES	0x00020000ull /* P-cache subset enforced */
#define MIPS_CPU_PREFETCH	0x00040000ull /* CPU has usable prefetch */
#define MIPS_CPU_VINT		0x00080000ull /* CPU supports MIPSR2 vectored interrupts */
#define MIPS_CPU_VEIC		0x00100000ull /* CPU supports MIPSR2 external interrupt controller mode */
#define MIPS_CPU_ULRI		0x00200000ull /* CPU has ULRI feature */
#define MIPS_CPU_PCI		0x00400000ull /* CPU has Perf Ctr Int indicator */
#define MIPS_CPU_RIXI		0x00800000ull /* CPU has TLB Read/eXec Inhibit */
#define MIPS_CPU_MICROMIPS	0x01000000ull /* CPU has microMIPS capability */
#define MIPS_CPU_TLBINV		0x02000000ull /* CPU supports TLBINV/F */
#define MIPS_CPU_SEGMENTS	0x04000000ull /* CPU supports Segmentation Control registers */
#define MIPS_CPU_EVA		0x80000000ull /* CPU supports Enhanced Virtual Addressing */
#define MIPS_CPU_HTW		0x100000000ull /* CPU support Hardware Page Table Walker */
#define MIPS_CPU_RIXIEX		0x200000000ull /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
#define MIPS_CPU_MAAR		0x400000000ull /* MAAR(I) registers are present */
#define MIPS_CPU_FRE		0x800000000ull /* FRE & UFE bits implemented */
#define MIPS_CPU_RW_LLB		0x1000000000ull /* LLADDR/LLB writes are allowed */
#define MIPS_CPU_XPA		0x2000000000ull /* CPU supports Extended Physical Addressing */
#define MIPS_CPU_CDMM		0x4000000000ull	/* CPU has Common Device Memory Map */
#define MIPS_CPU_BP_GHIST	0x8000000000ull /* R12K+ Branch Prediction Global History */
#define MIPS_CPU_SP		0x10000000000ull /* Small (1KB) page support */
#define MIPS_CPU_FTLB		0x20000000000ull /* CPU has Fixed-page-size TLB */
#define MIPS_CPU_NAN_LEGACY	0x40000000000ull /* Legacy NaN implemented */
#define MIPS_CPU_NAN_2008	0x80000000000ull /* 2008 NaN implemented */
#define MIPS_CPU_VP		0x100000000000ull /* MIPSr6 Virtual Processors (multi-threading) */

/*
 * CPU ASE encodings
 */
#define MIPS_ASE_MIPS16		0x00000001 /* code compression */
#define MIPS_ASE_MDMX		0x00000002 /* MIPS digital media extension */
#define MIPS_ASE_MIPS3D		0x00000004 /* MIPS-3D */
#define MIPS_ASE_SMARTMIPS	0x00000008 /* SmartMIPS */
#define MIPS_ASE_DSP		0x00000010 /* Signal Processing ASE */
#define MIPS_ASE_MIPSMT		0x00000020 /* CPU supports MIPS MT */
#define MIPS_ASE_DSP2P		0x00000040 /* Signal Processing ASE Rev 2 */
#define MIPS_ASE_VZ		0x00000080 /* Virtualization ASE */
#define MIPS_ASE_MSA		0x00000100 /* MIPS SIMD Architecture */

#endif /* _ASM_CPU_H */
Commit	Line	Data
1da177e4 LT	1	/*
1da177e4 LT	2	* cpu.h: Values of the PRId register used to match up
70342287	3	* various MIPS cpu types.
1da177e4	4	*
79add627	5	* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
8ff374b9	6	* Copyright (C) 2004, 2013 Maciej W. Rozycki
1da177e4 LT	7	*/
	8	#ifndef _ASM_CPU_H
	9	#define _ASM_CPU_H
	10
8ff374b9 MR	11	/*
	12	As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0
	13	register 15, select 0) is defined in this (backwards compatible) way:
1da177e4 LT	14
1da177e4 LT	15	+----------------+----------------+----------------+----------------+
70342287	16	\| Company Options\| Company ID \| Processor ID \| Revision \|
1da177e4	17	+----------------+----------------+----------------+----------------+
70342287	18	31 24 23 16 15 8 7
1da177e4 LT	19
	20	I don't have docs for all the previous processors, but my impression is
	21	that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
	22	spec.
	23	*/
	24
8ff374b9 MR	25	#define PRID_OPT_MASK 0xff000000
	26
	27	/*
	28	* Assigned Company values for bits 23:16 of the PRId register.
	29	*/
	30
	31	#define PRID_COMP_MASK 0xff0000
	32
55a6feb6 RB	33	#define PRID_COMP_LEGACY 0x000000
	34	#define PRID_COMP_MIPS 0x010000
	35	#define PRID_COMP_BROADCOM 0x020000
	36	#define PRID_COMP_ALCHEMY 0x030000
	37	#define PRID_COMP_SIBYTE 0x040000
	38	#define PRID_COMP_SANDCRAFT 0x050000
70342287	39	#define PRID_COMP_NXP 0x060000
55a6feb6 RB	40	#define PRID_COMP_TOSHIBA 0x070000
	41	#define PRID_COMP_LSI 0x080000
	42	#define PRID_COMP_LEXRA 0x0b0000
a7117c6b	43	#define PRID_COMP_NETLOGIC 0x0c0000
0dd4781b	44	#define PRID_COMP_CAVIUM 0x0d0000
252617a4 PB	45	#define PRID_COMP_INGENIC_D0 0xd00000 /* JZ4740, JZ4750 */
	46	#define PRID_COMP_INGENIC_D1 0xd10000 /* JZ4770, JZ4775 */
	47	#define PRID_COMP_INGENIC_E1 0xe10000 /* JZ4780 */
1da177e4 LT	48
1da177e4 LT	49	/*
8ff374b9 MR	50	* Assigned Processor ID (implementation) values for bits 15:8 of the PRId
	51	* register. In order to detect a certain CPU type exactly eventually
	52	* additional registers may need to be examined.
1da177e4	53	*/
8ff374b9 MR	54
	55	#define PRID_IMP_MASK 0xff00
	56
	57	/*
	58	* These are valid when 23:16 == PRID_COMP_LEGACY
	59	*/
	60
1da177e4 LT	61	#define PRID_IMP_R2000 0x0100
	62	#define PRID_IMP_AU1_REV1 0x0100
	63	#define PRID_IMP_AU1_REV2 0x0200
	64	#define PRID_IMP_R3000 0x0200 /* Same as R2000A */
	65	#define PRID_IMP_R6000 0x0300 /* Same as R3000A */
	66	#define PRID_IMP_R4000 0x0400
	67	#define PRID_IMP_R6000A 0x0600
	68	#define PRID_IMP_R10000 0x0900
	69	#define PRID_IMP_R4300 0x0b00
	70	#define PRID_IMP_VR41XX 0x0c00
	71	#define PRID_IMP_R12000 0x0e00
30577391	72	#define PRID_IMP_R14000 0x0f00 /* R14K && R16K */
1da177e4	73	#define PRID_IMP_R8000 0x1000
bdf21b18	74	#define PRID_IMP_PR4450 0x1200
1da177e4 LT	75	#define PRID_IMP_R4600 0x2000
	76	#define PRID_IMP_R4700 0x2100
	77	#define PRID_IMP_TX39 0x2200
	78	#define PRID_IMP_R4640 0x2200
	79	#define PRID_IMP_R4650 0x2200 /* Same as R4640 */
	80	#define PRID_IMP_R5000 0x2300
	81	#define PRID_IMP_TX49 0x2d00
	82	#define PRID_IMP_SONIC 0x2400
	83	#define PRID_IMP_MAGIC 0x2500
	84	#define PRID_IMP_RM7000 0x2700
	85	#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
	86	#define PRID_IMP_RM9000 0x3400
26859198	87	#define PRID_IMP_LOONGSON_32 0x4200 /* Loongson-1 */
1da177e4 LT	88	#define PRID_IMP_R5432 0x5400
1da177e4 LT	89	#define PRID_IMP_R5500 0x5500
26859198	90	#define PRID_IMP_LOONGSON_64 0x6300 /* Loongson-2/3 */
98e316d4 MR	91
	92	#define PRID_IMP_UNKNOWN 0xff00
	93
	94	/*
	95	* These are the PRID's for when 23:16 == PRID_COMP_MIPS
	96	*/
	97
aca5721e	98	#define PRID_IMP_QEMU_GENERIC 0x0000
1da177e4 LT	99	#define PRID_IMP_4KC 0x8000
	100	#define PRID_IMP_5KC 0x8100
	101	#define PRID_IMP_20KC 0x8200
	102	#define PRID_IMP_4KEC 0x8400
	103	#define PRID_IMP_4KSC 0x8600
	104	#define PRID_IMP_25KF 0x8800
	105	#define PRID_IMP_5KE 0x8900
	106	#define PRID_IMP_4KECR2 0x9000
	107	#define PRID_IMP_4KEMPR2 0x9100
	108	#define PRID_IMP_4KSD 0x9200
	109	#define PRID_IMP_24K 0x9300
bbc7f22f	110	#define PRID_IMP_34K 0x9500
e50c0a8f	111	#define PRID_IMP_24KE 0x9600
c620953c	112	#define PRID_IMP_74K 0x9700
39b8d525	113	#define PRID_IMP_1004K 0x9900
006a851b	114	#define PRID_IMP_1074K 0x9a00
113c62d9	115	#define PRID_IMP_M14KC 0x9c00
f8fa4811	116	#define PRID_IMP_M14KEC 0x9e00
0ce7d58e LY	117	#define PRID_IMP_INTERAPTIV_UP 0xa000
0ce7d58e LY	118	#define PRID_IMP_INTERAPTIV_MP 0xa100
76f59e32 LY	119	#define PRID_IMP_PROAPTIV_UP 0xa200
76f59e32 LY	120	#define PRID_IMP_PROAPTIV_MP 0xa300
4975b86a	121	#define PRID_IMP_M5150 0xa700
f43e4dfd	122	#define PRID_IMP_P5600 0xa800
90b8baa2	123	#define PRID_IMP_I6400 0xa900
1da177e4	124
1da177e4 LT	125	/*
	126	* These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
	127	*/
	128
70342287 RB	129	#define PRID_IMP_SB1 0x0100
70342287 RB	130	#define PRID_IMP_SB1A 0x1100
1da177e4 LT	131
	132	/*
	133	* These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
	134	*/
	135
70342287	136	#define PRID_IMP_SR71000 0x0400
1da177e4	137
1c0c13eb AJ	138	/*
	139	* These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
	140	*/
	141
190fca3e KC	142	#define PRID_IMP_BMIPS32_REV4 0x4000
190fca3e KC	143	#define PRID_IMP_BMIPS32_REV8 0x8000
602977b0 KC	144	#define PRID_IMP_BMIPS3300 0x9000
	145	#define PRID_IMP_BMIPS3300_ALT 0x9100
	146	#define PRID_IMP_BMIPS3300_BUG 0x0000
	147	#define PRID_IMP_BMIPS43XX 0xa000
	148	#define PRID_IMP_BMIPS5000 0x5a00
68e6a783	149	#define PRID_IMP_BMIPS5200 0x5b00
602977b0 KC	150
	151	#define PRID_REV_BMIPS4380_LO 0x0040
	152	#define PRID_REV_BMIPS4380_HI 0x006f
1c0c13eb	153
0dd4781b DD	154	/*
	155	* These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
	156	*/
	157
	158	#define PRID_IMP_CAVIUM_CN38XX 0x0000
	159	#define PRID_IMP_CAVIUM_CN31XX 0x0100
	160	#define PRID_IMP_CAVIUM_CN30XX 0x0200
	161	#define PRID_IMP_CAVIUM_CN58XX 0x0300
	162	#define PRID_IMP_CAVIUM_CN56XX 0x0400
	163	#define PRID_IMP_CAVIUM_CN50XX 0x0600
	164	#define PRID_IMP_CAVIUM_CN52XX 0x0700
1584d7f2	165	#define PRID_IMP_CAVIUM_CN63XX 0x9000
074ef0d2 DD	166	#define PRID_IMP_CAVIUM_CN68XX 0x9100
	167	#define PRID_IMP_CAVIUM_CN66XX 0x9200
	168	#define PRID_IMP_CAVIUM_CN61XX 0x9300
71a8b7d8 DD	169	#define PRID_IMP_CAVIUM_CNF71XX 0x9400
	170	#define PRID_IMP_CAVIUM_CN78XX 0x9500
	171	#define PRID_IMP_CAVIUM_CN70XX 0x9600
b8c8f665 DD	172	#define PRID_IMP_CAVIUM_CN73XX 0x9700
b8c8f665 DD	173	#define PRID_IMP_CAVIUM_CNF75XX 0x9800
0dd4781b	174
83ccf69d	175	/*
252617a4	176	* These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
83ccf69d LPC	177	*/
83ccf69d LPC	178
70342287	179	#define PRID_IMP_JZRISC 0x0200
83ccf69d	180
a7117c6b J	181	/*
	182	* These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
	183	*/
	184	#define PRID_IMP_NETLOGIC_XLR732 0x0000
	185	#define PRID_IMP_NETLOGIC_XLR716 0x0200
	186	#define PRID_IMP_NETLOGIC_XLR532 0x0900
	187	#define PRID_IMP_NETLOGIC_XLR308 0x0600
	188	#define PRID_IMP_NETLOGIC_XLR532C 0x0800
	189	#define PRID_IMP_NETLOGIC_XLR516C 0x0a00
	190	#define PRID_IMP_NETLOGIC_XLR508C 0x0b00
	191	#define PRID_IMP_NETLOGIC_XLR308C 0x0f00
	192	#define PRID_IMP_NETLOGIC_XLS608 0x8000
	193	#define PRID_IMP_NETLOGIC_XLS408 0x8800
	194	#define PRID_IMP_NETLOGIC_XLS404 0x8c00
	195	#define PRID_IMP_NETLOGIC_XLS208 0x8e00
	196	#define PRID_IMP_NETLOGIC_XLS204 0x8f00
	197	#define PRID_IMP_NETLOGIC_XLS108 0xce00
	198	#define PRID_IMP_NETLOGIC_XLS104 0xcf00
	199	#define PRID_IMP_NETLOGIC_XLS616B 0x4000
	200	#define PRID_IMP_NETLOGIC_XLS608B 0x4a00
	201	#define PRID_IMP_NETLOGIC_XLS416B 0x4400
	202	#define PRID_IMP_NETLOGIC_XLS412B 0x4c00
	203	#define PRID_IMP_NETLOGIC_XLS408B 0x4e00
	204	#define PRID_IMP_NETLOGIC_XLS404B 0x4f00
809f36c6	205	#define PRID_IMP_NETLOGIC_AU13XX 0x8000
a7117c6b	206
2aa54b20 J	207	#define PRID_IMP_NETLOGIC_XLP8XX 0x1000
2aa54b20 J	208	#define PRID_IMP_NETLOGIC_XLP3XX 0x1100
4ca86a2f	209	#define PRID_IMP_NETLOGIC_XLP2XX 0x1200
8907c55e	210	#define PRID_IMP_NETLOGIC_XLP9XX 0x1500
1c983986	211	#define PRID_IMP_NETLOGIC_XLP5XX 0x1300
a7117c6b	212
1da177e4	213	/*
8ff374b9	214	* Particular Revision values for bits 7:0 of the PRId register.
1da177e4 LT	215	*/
1da177e4 LT	216
9267a30d	217	#define PRID_REV_MASK 0x00ff
1da177e4	218
8ff374b9 MR	219	/*
	220	* Definitions for 7:0 on legacy processors
	221	*/
	222
1da177e4 LT	223	#define PRID_REV_TX4927 0x0022
	224	#define PRID_REV_TX4937 0x0030
	225	#define PRID_REV_R4400 0x0040
	226	#define PRID_REV_R3000A 0x0030
	227	#define PRID_REV_R3000 0x0020
	228	#define PRID_REV_R2000A 0x0010
70342287 RB	229	#define PRID_REV_TX3912 0x0010
	230	#define PRID_REV_TX3922 0x0030
	231	#define PRID_REV_TX3927 0x0040
1da177e4 LT	232	#define PRID_REV_VR4111 0x0050
	233	#define PRID_REV_VR4181 0x0050 /* Same as VR4111 */
	234	#define PRID_REV_VR4121 0x0060
	235	#define PRID_REV_VR4122 0x0070
	236	#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
	237	#define PRID_REV_VR4130 0x0080
9267a30d	238	#define PRID_REV_34K_V1_0_2 0x0022
2fa36399	239	#define PRID_REV_LOONGSON1B 0x0020
f8ede0f7 WZ	240	#define PRID_REV_LOONGSON2E 0x0002
f8ede0f7 WZ	241	#define PRID_REV_LOONGSON2F 0x0003
152ebb44	242	#define PRID_REV_LOONGSON3A 0x0005
e7841be5 HC	243	#define PRID_REV_LOONGSON3B_R1 0x0006
e7841be5 HC	244	#define PRID_REV_LOONGSON3B_R2 0x0007
1da177e4	245
fde97822 RB	246	/*
	247	* Older processors used to encode processor version and revision in two
	248	* 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
	249	* have switched to use the 8-bits as 3:3:2 bitfield with the last field as
	250	* the patch number. ARGH
	251	*/
	252	#define PRID_REV_ENCODE_44(ver, rev) \
	253	((ver) << 4 \| (rev))
	254	#define PRID_REV_ENCODE_332(ver, rev, patch) \
	255	((ver) << 5 \| (rev) << 2 \| (patch))
	256
1da177e4 LT	257	/*
	258	* FPU implementation/revision register (CP1 control register 0).
	259	*
	260	* +---------------------------------+----------------+----------------+
70342287	261	* \| 0 \| Implementation \| Revision \|
1da177e4	262	* +---------------------------------+----------------+----------------+
70342287	263	* 31 16 15 8 7 0
1da177e4 LT	264	*/
1da177e4 LT	265
8ff374b9 MR	266	#define FPIR_IMP_MASK 0xff00
8ff374b9 MR	267
1da177e4 LT	268	#define FPIR_IMP_NONE 0x0000
1da177e4 LT	269
68248d0c JG	270	#if !defined(__ASSEMBLY__)
68248d0c JG	271
36cfbaad RB	272	enum cpu_type_enum {
	273	CPU_UNKNOWN,
	274
	275	/*
	276	* R2000 class processors
	277	*/
	278	CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052,
	279	CPU_R3081, CPU_R3081E,
	280
	281	/*
	282	* R6000 class processors
	283	*/
	284	CPU_R6000, CPU_R6000A,
	285
	286	/*
	287	* R4000 class processors
	288	*/
	289	CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
	290	CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
fb2b1dba	291	CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000,
30577391 JK	292	CPU_R12000, CPU_R14000, CPU_R16000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
30577391 JK	293	CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
321b1863	294	CPU_SR71000, CPU_TX49XX,
36cfbaad RB	295
	296	/*
	297	* R8000 class processors
	298	*/
	299	CPU_R8000,
	300
	301	/*
	302	* TX3900 class processors
	303	*/
	304	CPU_TX3912, CPU_TX3922, CPU_TX3927,
	305
	306	/*
	307	* MIPS32 class processors
	308	*/
39b8d525	309	CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
602977b0	310	CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
2fa36399	311	CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
f36c4720	312	CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K, CPU_M5150,
90b8baa2	313	CPU_I6400,
36cfbaad RB	314
	315	/*
	316	* MIPS64 class processors
	317	*/
78d4803f	318	CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
152ebb44 HC	319	CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
152ebb44 HC	320	CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP,
36cfbaad	321
aca5721e LY	322	CPU_QEMU_GENERIC,
aca5721e LY	323
36cfbaad RB	324	CPU_LAST
	325	};
	326
68248d0c	327	#endif /* !__ASSEMBLY */
1da177e4 LT	328
	329	/*
	330	* ISA Level encodings
	331	*
	332	*/
1990e542 RB	333	#define MIPS_CPU_ISA_II 0x00000001
	334	#define MIPS_CPU_ISA_III 0x00000002
	335	#define MIPS_CPU_ISA_IV 0x00000004
	336	#define MIPS_CPU_ISA_V 0x00000008
	337	#define MIPS_CPU_ISA_M32R1 0x00000010
	338	#define MIPS_CPU_ISA_M32R2 0x00000020
	339	#define MIPS_CPU_ISA_M64R1 0x00000040
	340	#define MIPS_CPU_ISA_M64R2 0x00000080
34c56fc1 LY	341	#define MIPS_CPU_ISA_M32R6 0x00000100
34c56fc1 LY	342	#define MIPS_CPU_ISA_M64R6 0x00000200
1990e542 RB	343
1990e542 RB	344	#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II \| MIPS_CPU_ISA_M32R1 \| \
34c56fc1	345	MIPS_CPU_ISA_M32R2 \| MIPS_CPU_ISA_M32R6)
0401572a	346	#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III \| MIPS_CPU_ISA_IV \| \
34c56fc1 LY	347	MIPS_CPU_ISA_V \| MIPS_CPU_ISA_M64R1 \| MIPS_CPU_ISA_M64R2 \| \
34c56fc1 LY	348	MIPS_CPU_ISA_M64R6)
1da177e4 LT	349
	350	/*
	351	* CPU Option encodings
	352	*/
03a58777 MC	353	#define MIPS_CPU_TLB 0x00000001ull /* CPU has TLB */
	354	#define MIPS_CPU_4KEX 0x00000002ull /* "R4K" exception model */
	355	#define MIPS_CPU_3K_CACHE 0x00000004ull /* R3000-style caches */
	356	#define MIPS_CPU_4K_CACHE 0x00000008ull /* R4000-style caches */
	357	#define MIPS_CPU_TX39_CACHE 0x00000010ull /* TX3900-style caches */
	358	#define MIPS_CPU_FPU 0x00000020ull /* CPU has FPU */
	359	#define MIPS_CPU_32FPR 0x00000040ull /* 32 dbl. prec. FP registers */
	360	#define MIPS_CPU_COUNTER 0x00000080ull /* Cycle count/compare */
	361	#define MIPS_CPU_WATCH 0x00000100ull /* watchpoint registers */
	362	#define MIPS_CPU_DIVEC 0x00000200ull /* dedicated interrupt vector */
	363	#define MIPS_CPU_VCE 0x00000400ull /* virt. coherence conflict possible */
	364	#define MIPS_CPU_CACHE_CDEX_P 0x00000800ull /* Create_Dirty_Exclusive CACHE op */
	365	#define MIPS_CPU_CACHE_CDEX_S 0x00001000ull /* ... same for seconary cache ... */
	366	#define MIPS_CPU_MCHECK 0x00002000ull /* Machine check exception */
	367	#define MIPS_CPU_EJTAG 0x00004000ull /* EJTAG exception */
	368	#define MIPS_CPU_NOFPUEX 0x00008000ull /* no FPU exception */
	369	#define MIPS_CPU_LLSC 0x00010000ull /* CPU has ll/sc instructions */
	370	#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000ull /* P-cache subset enforced */
	371	#define MIPS_CPU_PREFETCH 0x00040000ull /* CPU has usable prefetch */
	372	#define MIPS_CPU_VINT 0x00080000ull /* CPU supports MIPSR2 vectored interrupts */
	373	#define MIPS_CPU_VEIC 0x00100000ull /* CPU supports MIPSR2 external interrupt controller mode */
	374	#define MIPS_CPU_ULRI 0x00200000ull /* CPU has ULRI feature */
	375	#define MIPS_CPU_PCI 0x00400000ull /* CPU has Perf Ctr Int indicator */
	376	#define MIPS_CPU_RIXI 0x00800000ull /* CPU has TLB Read/eXec Inhibit */
	377	#define MIPS_CPU_MICROMIPS 0x01000000ull /* CPU has microMIPS capability */
	378	#define MIPS_CPU_TLBINV 0x02000000ull /* CPU supports TLBINV/F */
	379	#define MIPS_CPU_SEGMENTS 0x04000000ull /* CPU supports Segmentation Control registers */
	380	#define MIPS_CPU_EVA 0x80000000ull /* CPU supports Enhanced Virtual Addressing */
e647e6b5	381	#define MIPS_CPU_HTW 0x100000000ull /* CPU support Hardware Page Table Walker */
6ee729aa	382	#define MIPS_CPU_RIXIEX 0x200000000ull /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
1f6c52ff	383	#define MIPS_CPU_MAAR 0x400000000ull /* MAAR(I) registers are present */
adac5d53	384	#define MIPS_CPU_FRE 0x800000000ull /* FRE & UFE bits implemented */
5aed9da1	385	#define MIPS_CPU_RW_LLB 0x1000000000ull /* LLADDR/LLB writes are allowed */
c5b36783	386	#define MIPS_CPU_XPA 0x2000000000ull /* CPU supports Extended Physical Addressing */
3e20a26b	387	#define MIPS_CPU_CDMM 0x4000000000ull /* CPU has Common Device Memory Map */
8d5ded16	388	#define MIPS_CPU_BP_GHIST 0x8000000000ull /* R12K+ Branch Prediction Global History */
aaa7be48	389	#define MIPS_CPU_SP 0x10000000000ull /* Small (1KB) page support */
2f6f3136	390	#define MIPS_CPU_FTLB 0x20000000000ull /* CPU has Fixed-page-size TLB */
9519ef37 MR	391	#define MIPS_CPU_NAN_LEGACY 0x40000000000ull /* Legacy NaN implemented */
9519ef37 MR	392	#define MIPS_CPU_NAN_2008 0x80000000000ull /* 2008 NaN implemented */
f270d881	393	#define MIPS_CPU_VP 0x100000000000ull /* MIPSr6 Virtual Processors (multi-threading) */
1da177e4	394
4194318c RB	395	/*
	396	* CPU ASE encodings
	397	*/
	398	#define MIPS_ASE_MIPS16 0x00000001 /* code compression */
	399	#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */
	400	#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */
	401	#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */
e50c0a8f	402	#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
8f40611d	403	#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */
ee80f7c7	404	#define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */
1e7decdb	405	#define MIPS_ASE_VZ 0x00000080 /* Virtualization ASE */
a5e9a69e	406	#define MIPS_ASE_MSA 0x00000100 /* MIPS SIMD Architecture */
4194318c	407
1da177e4	408	#endif /* _ASM_CPU_H */