projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * Miscellaneous definitions used to initialise the interrupt vector table | |
| 3 | * with the machine-specific interrupt routines. | |
| 4 | * | |
| 5 | * This file is subject to the terms and conditions of the GNU General Public | |
| 6 | * License. See the file "COPYING" in the main directory of this archive | |
| 7 | * for more details. | |
| 8 | * | |
| 9 | * Copyright (C) 1997 by Paul M. Antoine. | |
| 10 | * reworked 1998 by Harald Koerfgen. | |
| 11 | * Copyright (C) 2001, 2002, 2003 Maciej W. Rozycki | |
| 12 | */ | |
| 13 | ||
| 14 | #ifndef __ASM_DEC_INTERRUPTS_H | |
| 15 | #define __ASM_DEC_INTERRUPTS_H | |
| 16 | ||
| 97dcb82d | 17 | #include <irq.h> |
| 1da177e4 LT |
18 | #include <asm/mipsregs.h> |
| 19 | ||
| 20 | ||
| 21 | /* | |
| 22 | * The list of possible system devices which provide an | |
| 23 | * interrupt. Not all devices exist on a given system. | |
| 24 | */ | |
| 25 | #define DEC_IRQ_CASCADE 0 /* cascade from CSR or I/O ASIC */ | |
| 26 | ||
| 27 | /* Ordinary interrupts */ | |
| 28 | #define DEC_IRQ_AB_RECV 1 /* ACCESS.bus receive */ | |
| 29 | #define DEC_IRQ_AB_XMIT 2 /* ACCESS.bus transmit */ | |
| 30 | #define DEC_IRQ_DZ11 3 /* DZ11 (DC7085) serial */ | |
| 31 | #define DEC_IRQ_ASC 4 /* ASC (NCR53C94) SCSI */ | |
| 32 | #define DEC_IRQ_FLOPPY 5 /* 82077 FDC */ | |
| 33 | #define DEC_IRQ_FPU 6 /* R3k FPU */ | |
| 34 | #define DEC_IRQ_HALT 7 /* HALT button or from ACCESS.Bus */ | |
| 35 | #define DEC_IRQ_ISDN 8 /* Am79C30A ISDN */ | |
| 36 | #define DEC_IRQ_LANCE 9 /* LANCE (Am7990) Ethernet */ | |
| 37 | #define DEC_IRQ_BUS 10 /* memory, I/O bus read/write errors */ | |
| 38 | #define DEC_IRQ_PSU 11 /* power supply unit warning */ | |
| 39 | #define DEC_IRQ_RTC 12 /* DS1287 RTC */ | |
| 40 | #define DEC_IRQ_SCC0 13 /* SCC (Z85C30) serial #0 */ | |
| 41 | #define DEC_IRQ_SCC1 14 /* SCC (Z85C30) serial #1 */ | |
| 42 | #define DEC_IRQ_SII 15 /* SII (DC7061) SCSI */ | |
| 43 | #define DEC_IRQ_TC0 16 /* TURBOchannel slot #0 */ | |
| 44 | #define DEC_IRQ_TC1 17 /* TURBOchannel slot #1 */ | |
| 45 | #define DEC_IRQ_TC2 18 /* TURBOchannel slot #2 */ | |
| 46 | #define DEC_IRQ_TIMER 19 /* ARC periodic timer */ | |
| 47 | #define DEC_IRQ_VIDEO 20 /* framebuffer */ | |
| 48 | ||
| 49 | /* I/O ASIC DMA interrupts */ | |
| 50 | #define DEC_IRQ_ASC_MERR 21 /* ASC memory read error */ | |
| 51 | #define DEC_IRQ_ASC_ERR 22 /* ASC page overrun */ | |
| 52 | #define DEC_IRQ_ASC_DMA 23 /* ASC buffer pointer loaded */ | |
| 53 | #define DEC_IRQ_FLOPPY_ERR 24 /* FDC error */ | |
| 54 | #define DEC_IRQ_ISDN_ERR 25 /* ISDN memory read/overrun error */ | |
| 55 | #define DEC_IRQ_ISDN_RXDMA 26 /* ISDN recv buffer pointer loaded */ | |
| 56 | #define DEC_IRQ_ISDN_TXDMA 27 /* ISDN xmit buffer pointer loaded */ | |
| 57 | #define DEC_IRQ_LANCE_MERR 28 /* LANCE memory read error */ | |
| 58 | #define DEC_IRQ_SCC0A_RXERR 29 /* SCC0A (printer) receive overrun */ | |
| 59 | #define DEC_IRQ_SCC0A_RXDMA 30 /* SCC0A receive half page */ | |
| 60 | #define DEC_IRQ_SCC0A_TXERR 31 /* SCC0A xmit memory read/overrun */ | |
| 61 | #define DEC_IRQ_SCC0A_TXDMA 32 /* SCC0A transmit page end */ | |
| 62 | #define DEC_IRQ_AB_RXERR 33 /* ACCESS.bus receive overrun */ | |
| 63 | #define DEC_IRQ_AB_RXDMA 34 /* ACCESS.bus receive half page */ | |
| 64 | #define DEC_IRQ_AB_TXERR 35 /* ACCESS.bus xmit memory read/ovrn */ | |
| 65 | #define DEC_IRQ_AB_TXDMA 36 /* ACCESS.bus transmit page end */ | |
| 66 | #define DEC_IRQ_SCC1A_RXERR 37 /* SCC1A (modem) receive overrun */ | |
| 67 | #define DEC_IRQ_SCC1A_RXDMA 38 /* SCC1A receive half page */ | |
| 68 | #define DEC_IRQ_SCC1A_TXERR 39 /* SCC1A xmit memory read/overrun */ | |
| 69 | #define DEC_IRQ_SCC1A_TXDMA 40 /* SCC1A transmit page end */ | |
| 70 | ||
| 71 | /* TC5 & TC6 are virtual slots for KN02's onboard devices */ | |
| 72 | #define DEC_IRQ_TC5 DEC_IRQ_ASC /* virtual PMAZ-AA */ | |
| 73 | #define DEC_IRQ_TC6 DEC_IRQ_LANCE /* virtual PMAD-AA */ | |
| 74 | ||
| 75 | #define DEC_NR_INTS 41 | |
| 76 | ||
| 77 | ||
| 78 | /* Largest of cpu mask_nr tables. */ | |
| 79 | #define DEC_MAX_CPU_INTS 6 | |
| 80 | /* Largest of asic mask_nr tables. */ | |
| 81 | #define DEC_MAX_ASIC_INTS 9 | |
| 82 | ||
| 83 | ||
| 84 | /* | |
| 85 | * CPU interrupt bits common to all systems. | |
| 86 | */ | |
| 87 | #define DEC_CPU_INR_FPU 7 /* R3k FPU */ | |
| 88 | #define DEC_CPU_INR_SW1 1 /* software #1 */ | |
| 89 | #define DEC_CPU_INR_SW0 0 /* software #0 */ | |
| 90 | ||
| 97dcb82d | 91 | #define DEC_CPU_IRQ_BASE MIPS_CPU_IRQ_BASE /* first IRQ assigned to CPU */ |
| 1da177e4 LT |
92 | |
| 93 | #define DEC_CPU_IRQ_NR(n) ((n) + DEC_CPU_IRQ_BASE) | |
| 94 | #define DEC_CPU_IRQ_MASK(n) (1 << ((n) + CAUSEB_IP)) | |
| 95 | #define DEC_CPU_IRQ_ALL (0xff << CAUSEB_IP) | |
| 96 | ||
| 97 | ||
| 98 | #ifndef __ASSEMBLY__ | |
| 99 | ||
| 100 | /* | |
| 101 | * Interrupt table structures to hide differences between systems. | |
| 102 | */ | |
| 103 | typedef union { int i; void *p; } int_ptr; | |
| 104 | extern int dec_interrupt[DEC_NR_INTS]; | |
| 105 | extern int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2]; | |
| 106 | extern int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2]; | |
| 107 | extern int cpu_fpu_mask; | |
| 108 | ||
| 109 | ||
| 110 | /* | |
| 111 | * Common interrupt routine prototypes for all DECStations | |
| 112 | */ | |
| 113 | extern void kn02_io_int(void); | |
| 114 | extern void kn02xa_io_int(void); | |
| 115 | extern void kn03_io_int(void); | |
| 116 | extern void asic_dma_int(void); | |
| 117 | extern void asic_all_int(void); | |
| 118 | extern void kn02_all_int(void); | |
| 119 | extern void cpu_all_int(void); | |
| 120 | ||
| 121 | extern void dec_intr_unimplemented(void); | |
| 122 | extern void asic_intr_unimplemented(void); | |
| 123 | ||
| 124 | #endif /* __ASSEMBLY__ */ | |
| 125 | ||
| 126 | #endif |