projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * Hardware info common to DECstation 5000/1xx systems (otherwise | |
| 3 | * known as 3min or kn02ba) and Personal DECstations 5000/xx ones | |
| 4 | * (otherwise known as maxine or kn02ca). | |
| 5 | * | |
| 6 | * This file is subject to the terms and conditions of the GNU General Public | |
| 7 | * License. See the file "COPYING" in the main directory of this archive | |
| 8 | * for more details. | |
| 9 | * | |
| 10 | * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions | |
| 11 | * are by courtesy of Chris Fraser. | |
| 64dac503 | 12 | * Copyright (C) 2000, 2002, 2003, 2005 Maciej W. Rozycki |
| 1da177e4 LT |
13 | * |
| 14 | * These are addresses which have to be known early in the boot process. | |
| 15 | * For other addresses refer to tc.h, ioasic_addrs.h and friends. | |
| 16 | */ | |
| 17 | #ifndef __ASM_MIPS_DEC_KN02XA_H | |
| 18 | #define __ASM_MIPS_DEC_KN02XA_H | |
| 19 | ||
| 1da177e4 LT |
20 | #include <asm/dec/ioasic_addrs.h> |
| 21 | ||
| a5fc9c0b | 22 | #define KN02XA_SLOT_BASE 0x1c000000 |
| 1da177e4 LT |
23 | |
| 24 | /* | |
| 25 | * Memory control ASIC registers. | |
| 26 | */ | |
| a5fc9c0b MR |
27 | #define KN02XA_MER 0x0c400000 /* memory error register */ |
| 28 | #define KN02XA_MSR 0x0c800000 /* memory size register */ | |
| 1da177e4 LT |
29 | |
| 30 | /* | |
| 31 | * CPU control ASIC registers. | |
| 32 | */ | |
| a5fc9c0b MR |
33 | #define KN02XA_MEM_CONF 0x0e000000 /* write timeout config */ |
| 34 | #define KN02XA_EAR 0x0e000004 /* error address register */ | |
| 35 | #define KN02XA_BOOT0 0x0e000008 /* boot 0 register */ | |
| 36 | #define KN02XA_MEM_INTR 0x0e00000c /* write err IRQ stat & ack */ | |
| 1da177e4 LT |
37 | |
| 38 | /* | |
| 39 | * Memory Error Register bits, common definitions. | |
| 40 | * The rest is defined in system-specific headers. | |
| 41 | */ | |
| 42 | #define KN02XA_MER_RES_28 (0xf<<28) /* unused */ | |
| 43 | #define KN02XA_MER_RES_17 (0x3ff<<17) /* unused */ | |
| 44 | #define KN02XA_MER_PAGERR (1<<16) /* 2k page boundary error */ | |
| 45 | #define KN02XA_MER_TRANSERR (1<<15) /* transfer length error */ | |
| 46 | #define KN02XA_MER_PARDIS (1<<14) /* parity error disable */ | |
| 64dac503 MR |
47 | #define KN02XA_MER_SIZE (1<<13) /* r/o mirror of MSR_SIZE */ |
| 48 | #define KN02XA_MER_RES_12 (1<<12) /* unused */ | |
| 49 | #define KN02XA_MER_BYTERR (0xf<<8) /* byte lane error bitmask: */ | |
| 50 | #define KN02XA_MER_BYTERR_3 (0x8<<8) /* byte lane #3 */ | |
| 51 | #define KN02XA_MER_BYTERR_2 (0x4<<8) /* byte lane #2 */ | |
| 52 | #define KN02XA_MER_BYTERR_1 (0x2<<8) /* byte lane #1 */ | |
| 53 | #define KN02XA_MER_BYTERR_0 (0x1<<8) /* byte lane #0 */ | |
| 1da177e4 LT |
54 | #define KN02XA_MER_RES_0 (0xff<<0) /* unused */ |
| 55 | ||
| 56 | /* | |
| 57 | * Memory Size Register bits, common definitions. | |
| 58 | * The rest is defined in system-specific headers. | |
| 59 | */ | |
| 60 | #define KN02XA_MSR_RES_27 (0x1f<<27) /* unused */ | |
| 61 | #define KN02XA_MSR_RES_14 (0x7<<14) /* unused */ | |
| 62 | #define KN02XA_MSR_SIZE (1<<13) /* 16M/4M stride */ | |
| 63 | #define KN02XA_MSR_RES_0 (0x1fff<<0) /* unused */ | |
| 64 | ||
| 65 | /* | |
| 66 | * Error Address Register bits. | |
| 67 | */ | |
| 68 | #define KN02XA_EAR_RES_29 (0x7<<29) /* unused */ | |
| 69 | #define KN02XA_EAR_ADDRESS (0x7ffffff<<2) /* address involved */ | |
| 70 | #define KN02XA_EAR_RES_0 (0x3<<0) /* unused */ | |
| 71 | ||
| 64dac503 MR |
72 | |
| 73 | #ifndef __ASSEMBLY__ | |
| 74 | ||
| 75 | #include <linux/interrupt.h> | |
| 76 | ||
| 77 | struct pt_regs; | |
| 78 | ||
| 79 | extern void dec_kn02xa_be_init(void); | |
| 80 | extern int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup); | |
| 6dab2f45 | 81 | extern irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id); |
| 64dac503 MR |
82 | #endif |
| 83 | ||
| 1da177e4 | 84 | #endif /* __ASM_MIPS_DEC_KN02XA_H */ |