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1da177e4 LT |
1 | /* |
2 | * Copyright (C) 2002 MontaVista Software Inc. | |
3 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2 of the License, or (at your | |
8 | * option) any later version. | |
9 | */ | |
10 | #ifndef _ASM_FPU_H | |
11 | #define _ASM_FPU_H | |
12 | ||
1da177e4 LT |
13 | #include <linux/sched.h> |
14 | #include <linux/thread_info.h> | |
1977f032 | 15 | #include <linux/bitops.h> |
1da177e4 LT |
16 | |
17 | #include <asm/mipsregs.h> | |
18 | #include <asm/cpu.h> | |
19 | #include <asm/cpu-features.h> | |
e0cc3a42 | 20 | #include <asm/fpu_emulator.h> |
0b624956 | 21 | #include <asm/hazards.h> |
1da177e4 LT |
22 | #include <asm/processor.h> |
23 | #include <asm/current.h> | |
33c771ba | 24 | #include <asm/msa.h> |
1da177e4 | 25 | |
f088fc84 RB |
26 | #ifdef CONFIG_MIPS_MT_FPAFF |
27 | #include <asm/mips_mt.h> | |
28 | #endif | |
29 | ||
1da177e4 LT |
30 | struct sigcontext; |
31 | struct sigcontext32; | |
32 | ||
9b26616c | 33 | extern void _init_fpu(unsigned int); |
1da177e4 LT |
34 | extern void _save_fp(struct task_struct *); |
35 | extern void _restore_fp(struct task_struct *); | |
36 | ||
597ce172 PB |
37 | /* |
38 | * This enum specifies a mode in which we want the FPU to operate, for cores | |
4227a2d4 PB |
39 | * which implement the Status.FR bit. Note that the bottom bit of the value |
40 | * purposefully matches the desired value of the Status.FR bit. | |
597ce172 PB |
41 | */ |
42 | enum fpu_mode { | |
43 | FPU_32BIT = 0, /* FR = 0 */ | |
4227a2d4 | 44 | FPU_64BIT, /* FR = 1, FRE = 0 */ |
597ce172 | 45 | FPU_AS_IS, |
4227a2d4 PB |
46 | FPU_HYBRID, /* FR = 1, FRE = 1 */ |
47 | ||
48 | #define FPU_FR_MASK 0x1 | |
597ce172 PB |
49 | }; |
50 | ||
84ab45b3 PB |
51 | #define __disable_fpu() \ |
52 | do { \ | |
53 | clear_c0_status(ST0_CU1); \ | |
54 | disable_fpu_hazard(); \ | |
55 | } while (0) | |
56 | ||
597ce172 PB |
57 | static inline int __enable_fpu(enum fpu_mode mode) |
58 | { | |
59 | int fr; | |
60 | ||
61 | switch (mode) { | |
62 | case FPU_AS_IS: | |
63 | /* just enable the FPU in its current mode */ | |
64 | set_c0_status(ST0_CU1); | |
65 | enable_fpu_hazard(); | |
66 | return 0; | |
67 | ||
4227a2d4 PB |
68 | case FPU_HYBRID: |
69 | if (!cpu_has_fre) | |
70 | return SIGFPE; | |
71 | ||
72 | /* set FRE */ | |
d33e6fe3 | 73 | set_c0_config5(MIPS_CONF5_FRE); |
4227a2d4 PB |
74 | goto fr_common; |
75 | ||
597ce172 | 76 | case FPU_64BIT: |
fcc53b5f | 77 | #if !(defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) \ |
6134d949 | 78 | || defined(CONFIG_64BIT)) |
597ce172 PB |
79 | /* we only have a 32-bit FPU */ |
80 | return SIGFPE; | |
81 | #endif | |
82 | /* fall through */ | |
83 | case FPU_32BIT: | |
b0c34f61 RB |
84 | if (cpu_has_fre) { |
85 | /* clear FRE */ | |
d33e6fe3 | 86 | clear_c0_config5(MIPS_CONF5_FRE); |
b0c34f61 | 87 | } |
4227a2d4 | 88 | fr_common: |
597ce172 | 89 | /* set CU1 & change FR appropriately */ |
4227a2d4 | 90 | fr = (int)mode & FPU_FR_MASK; |
597ce172 PB |
91 | change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0)); |
92 | enable_fpu_hazard(); | |
93 | ||
94 | /* check FR has the desired value */ | |
84ab45b3 PB |
95 | if (!!(read_c0_status() & ST0_FR) == !!fr) |
96 | return 0; | |
97 | ||
98 | /* unsupported FR value */ | |
99 | __disable_fpu(); | |
100 | return SIGFPE; | |
597ce172 PB |
101 | |
102 | default: | |
103 | BUG(); | |
104 | } | |
97b8b16b AK |
105 | |
106 | return SIGFPE; | |
597ce172 | 107 | } |
1da177e4 | 108 | |
1da177e4 LT |
109 | #define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU) |
110 | ||
1d74f6bc RB |
111 | static inline int __is_fpu_owner(void) |
112 | { | |
113 | return test_thread_flag(TIF_USEDFPU); | |
114 | } | |
115 | ||
1da177e4 LT |
116 | static inline int is_fpu_owner(void) |
117 | { | |
1d74f6bc | 118 | return cpu_has_fpu && __is_fpu_owner(); |
1da177e4 LT |
119 | } |
120 | ||
597ce172 | 121 | static inline int __own_fpu(void) |
1da177e4 | 122 | { |
597ce172 PB |
123 | enum fpu_mode mode; |
124 | int ret; | |
125 | ||
4227a2d4 PB |
126 | if (test_thread_flag(TIF_HYBRID_FPREGS)) |
127 | mode = FPU_HYBRID; | |
128 | else | |
129 | mode = !test_thread_flag(TIF_32BIT_FPREGS); | |
130 | ||
597ce172 PB |
131 | ret = __enable_fpu(mode); |
132 | if (ret) | |
133 | return ret; | |
134 | ||
53dc8028 | 135 | KSTK_STATUS(current) |= ST0_CU1; |
4227a2d4 | 136 | if (mode == FPU_64BIT || mode == FPU_HYBRID) |
597ce172 PB |
137 | KSTK_STATUS(current) |= ST0_FR; |
138 | else /* mode == FPU_32BIT */ | |
139 | KSTK_STATUS(current) &= ~ST0_FR; | |
140 | ||
53dc8028 | 141 | set_thread_flag(TIF_USEDFPU); |
597ce172 | 142 | return 0; |
53dc8028 AN |
143 | } |
144 | ||
597ce172 | 145 | static inline int own_fpu_inatomic(int restore) |
53dc8028 | 146 | { |
597ce172 PB |
147 | int ret = 0; |
148 | ||
53dc8028 | 149 | if (cpu_has_fpu && !__is_fpu_owner()) { |
597ce172 PB |
150 | ret = __own_fpu(); |
151 | if (restore && !ret) | |
53dc8028 | 152 | _restore_fp(current); |
1da177e4 | 153 | } |
597ce172 | 154 | return ret; |
faea6234 AN |
155 | } |
156 | ||
597ce172 | 157 | static inline int own_fpu(int restore) |
faea6234 | 158 | { |
597ce172 PB |
159 | int ret; |
160 | ||
faea6234 | 161 | preempt_disable(); |
597ce172 | 162 | ret = own_fpu_inatomic(restore); |
53dc8028 | 163 | preempt_enable(); |
597ce172 | 164 | return ret; |
1da177e4 LT |
165 | } |
166 | ||
1a3d5957 | 167 | static inline void lose_fpu_inatomic(int save, struct task_struct *tsk) |
1da177e4 | 168 | { |
33c771ba PB |
169 | if (is_msa_enabled()) { |
170 | if (save) { | |
1a3d5957 PB |
171 | save_msa(tsk); |
172 | tsk->thread.fpu.fcr31 = | |
842dfc11 | 173 | read_32bit_cp1_register(CP1_STATUS); |
33c771ba PB |
174 | } |
175 | disable_msa(); | |
1a3d5957 | 176 | clear_tsk_thread_flag(tsk, TIF_USEDMSA); |
acaf6a97 | 177 | __disable_fpu(); |
33c771ba | 178 | } else if (is_fpu_owner()) { |
53dc8028 | 179 | if (save) |
1a3d5957 | 180 | _save_fp(tsk); |
1da177e4 | 181 | __disable_fpu(); |
00fe56dc JH |
182 | } else { |
183 | /* FPU should not have been left enabled with no owner */ | |
184 | WARN(read_c0_status() & ST0_CU1, | |
185 | "Orphaned FPU left enabled"); | |
1da177e4 | 186 | } |
1a3d5957 PB |
187 | KSTK_STATUS(tsk) &= ~ST0_CU1; |
188 | clear_tsk_thread_flag(tsk, TIF_USEDFPU); | |
189 | } | |
190 | ||
191 | static inline void lose_fpu(int save) | |
192 | { | |
193 | preempt_disable(); | |
194 | lose_fpu_inatomic(save, current); | |
53dc8028 | 195 | preempt_enable(); |
1da177e4 LT |
196 | } |
197 | ||
597ce172 | 198 | static inline int init_fpu(void) |
1da177e4 | 199 | { |
9b26616c | 200 | unsigned int fcr31 = current->thread.fpu.fcr31; |
597ce172 PB |
201 | int ret = 0; |
202 | ||
1da177e4 | 203 | if (cpu_has_fpu) { |
b0c34f61 RB |
204 | unsigned int config5; |
205 | ||
597ce172 | 206 | ret = __own_fpu(); |
b0c34f61 RB |
207 | if (ret) |
208 | return ret; | |
4227a2d4 | 209 | |
b0c34f61 | 210 | if (!cpu_has_fre) { |
9b26616c | 211 | _init_fpu(fcr31); |
4227a2d4 | 212 | |
b0c34f61 | 213 | return 0; |
4227a2d4 | 214 | } |
b0c34f61 | 215 | |
b0c34f61 RB |
216 | /* |
217 | * Ensure FRE is clear whilst running _init_fpu, since | |
218 | * single precision FP instructions are used. If FRE | |
219 | * was set then we'll just end up initialising all 32 | |
220 | * 64b registers. | |
221 | */ | |
d33e6fe3 | 222 | config5 = clear_c0_config5(MIPS_CONF5_FRE); |
b0c34f61 RB |
223 | enable_fpu_hazard(); |
224 | ||
9b26616c | 225 | _init_fpu(fcr31); |
b0c34f61 RB |
226 | |
227 | /* Restore FRE */ | |
228 | write_c0_config5(config5); | |
229 | enable_fpu_hazard(); | |
e0cc3a42 | 230 | } else |
1da177e4 | 231 | fpu_emulator_init_fpu(); |
597ce172 | 232 | |
597ce172 | 233 | return ret; |
1da177e4 LT |
234 | } |
235 | ||
236 | static inline void save_fp(struct task_struct *tsk) | |
237 | { | |
238 | if (cpu_has_fpu) | |
239 | _save_fp(tsk); | |
240 | } | |
241 | ||
242 | static inline void restore_fp(struct task_struct *tsk) | |
243 | { | |
244 | if (cpu_has_fpu) | |
245 | _restore_fp(tsk); | |
246 | } | |
247 | ||
bbd426f5 | 248 | static inline union fpureg *get_fpu_regs(struct task_struct *tsk) |
1da177e4 | 249 | { |
e04582b7 AN |
250 | if (tsk == current) { |
251 | preempt_disable(); | |
252 | if (is_fpu_owner()) | |
1da177e4 | 253 | _save_fp(current); |
e04582b7 | 254 | preempt_enable(); |
1da177e4 LT |
255 | } |
256 | ||
eae89076 | 257 | return tsk->thread.fpu.fpr; |
1da177e4 LT |
258 | } |
259 | ||
260 | #endif /* _ASM_FPU_H */ |