[deliverable/linux.git] / arch / mips / include / asm / futex.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (c) 2006  Ralf Baechle (ralf@linux-mips.org)
 */
#ifndef _ASM_FUTEX_H
#define _ASM_FUTEX_H

#ifdef __KERNEL__

#include <linux/futex.h>
#include <linux/uaccess.h>
#include <asm/asm-eva.h>
#include <asm/barrier.h>
#include <asm/errno.h>
#include <asm/war.h>

#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg)		\
{									\
	if (cpu_has_llsc && R10000_LLSC_WAR) {				\
		__asm__ __volatile__(					\
		"	.set	push				\n"	\
		"	.set	noat				\n"	\
		"	.set	arch=r4000			\n"	\
		"1:	ll	%1, %4	# __futex_atomic_op	\n"	\
		"	.set	mips0				\n"	\
		"	" insn	"				\n"	\
		"	.set	arch=r4000			\n"	\
		"2:	sc	$1, %2				\n"	\
		"	beqzl	$1, 1b				\n"	\
		__WEAK_LLSC_MB						\
		"3:						\n"	\
		"	.set	pop				\n"	\
		"	.set	mips0				\n"	\
		"	.section .fixup,\"ax\"			\n"	\
		"4:	li	%0, %6				\n"	\
		"	j	3b				\n"	\
		"	.previous				\n"	\
		"	.section __ex_table,\"a\"		\n"	\
		"	"__UA_ADDR "\t1b, 4b			\n"	\
		"	"__UA_ADDR "\t2b, 4b			\n"	\
		"	.previous				\n"	\
		: "=r" (ret), "=&r" (oldval), "=R" (*uaddr)		\
		: "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT)	\
		: "memory");						\
	} else if (cpu_has_llsc) {					\
		__asm__ __volatile__(					\
		"	.set	push				\n"	\
		"	.set	noat				\n"	\
		"	.set	arch=r4000			\n"	\
		"1:	"user_ll("%1", "%4")" # __futex_atomic_op\n"	\
		"	.set	mips0				\n"	\
		"	" insn	"				\n"	\
		"	.set	arch=r4000			\n"	\
		"2:	"user_sc("$1", "%2")"			\n"	\
		"	beqz	$1, 1b				\n"	\
		__WEAK_LLSC_MB						\
		"3:						\n"	\
		"	.set	pop				\n"	\
		"	.set	mips0				\n"	\
		"	.section .fixup,\"ax\"			\n"	\
		"4:	li	%0, %6				\n"	\
		"	j	3b				\n"	\
		"	.previous				\n"	\
		"	.section __ex_table,\"a\"		\n"	\
		"	"__UA_ADDR "\t1b, 4b			\n"	\
		"	"__UA_ADDR "\t2b, 4b			\n"	\
		"	.previous				\n"	\
		: "=r" (ret), "=&r" (oldval), "=R" (*uaddr)		\
		: "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT)	\
		: "memory");						\
	} else								\
		ret = -ENOSYS;						\
}

static inline int
futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr)
{
	int op = (encoded_op >> 28) & 7;
	int cmp = (encoded_op >> 24) & 15;
	int oparg = (encoded_op << 8) >> 20;
	int cmparg = (encoded_op << 20) >> 20;
	int oldval = 0, ret;
	if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
		oparg = 1 << oparg;

	if (! access_ok (VERIFY_WRITE, uaddr, sizeof(u32)))
		return -EFAULT;

	pagefault_disable();

	switch (op) {
	case FUTEX_OP_SET:
		__futex_atomic_op("move $1, %z5", ret, oldval, uaddr, oparg);
		break;

	case FUTEX_OP_ADD:
		__futex_atomic_op("addu $1, %1, %z5",
				  ret, oldval, uaddr, oparg);
		break;
	case FUTEX_OP_OR:
		__futex_atomic_op("or	$1, %1, %z5",
				  ret, oldval, uaddr, oparg);
		break;
	case FUTEX_OP_ANDN:
		__futex_atomic_op("and	$1, %1, %z5",
				  ret, oldval, uaddr, ~oparg);
		break;
	case FUTEX_OP_XOR:
		__futex_atomic_op("xor	$1, %1, %z5",
				  ret, oldval, uaddr, oparg);
		break;
	default:
		ret = -ENOSYS;
	}

	pagefault_enable();

	if (!ret) {
		switch (cmp) {
		case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
		case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
		case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
		case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
		case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
		case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
		default: ret = -ENOSYS;
		}
	}
	return ret;
}

static inline int
futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
			      u32 oldval, u32 newval)
{
	int ret = 0;
	u32 val;

	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
		return -EFAULT;

	if (cpu_has_llsc && R10000_LLSC_WAR) {
		__asm__ __volatile__(
		"# futex_atomic_cmpxchg_inatomic			\n"
		"	.set	push					\n"
		"	.set	noat					\n"
		"	.set	arch=r4000				\n"
		"1:	ll	%1, %3					\n"
		"	bne	%1, %z4, 3f				\n"
		"	.set	mips0					\n"
		"	move	$1, %z5					\n"
		"	.set	arch=r4000				\n"
		"2:	sc	$1, %2					\n"
		"	beqzl	$1, 1b					\n"
		__WEAK_LLSC_MB
		"3:							\n"
		"	.set	pop					\n"
		"	.section .fixup,\"ax\"				\n"
		"4:	li	%0, %6					\n"
		"	j	3b					\n"
		"	.previous					\n"
		"	.section __ex_table,\"a\"			\n"
		"	"__UA_ADDR "\t1b, 4b				\n"
		"	"__UA_ADDR "\t2b, 4b				\n"
		"	.previous					\n"
		: "+r" (ret), "=&r" (val), "=R" (*uaddr)
		: "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT)
		: "memory");
	} else if (cpu_has_llsc) {
		__asm__ __volatile__(
		"# futex_atomic_cmpxchg_inatomic			\n"
		"	.set	push					\n"
		"	.set	noat					\n"
		"	.set	arch=r4000				\n"
		"1:	"user_ll("%1", "%3")"				\n"
		"	bne	%1, %z4, 3f				\n"
		"	.set	mips0					\n"
		"	move	$1, %z5					\n"
		"	.set	arch=r4000				\n"
		"2:	"user_sc("$1", "%2")"				\n"
		"	beqz	$1, 1b					\n"
		__WEAK_LLSC_MB
		"3:							\n"
		"	.set	pop					\n"
		"	.section .fixup,\"ax\"				\n"
		"4:	li	%0, %6					\n"
		"	j	3b					\n"
		"	.previous					\n"
		"	.section __ex_table,\"a\"			\n"
		"	"__UA_ADDR "\t1b, 4b				\n"
		"	"__UA_ADDR "\t2b, 4b				\n"
		"	.previous					\n"
		: "+r" (ret), "=&r" (val), "=R" (*uaddr)
		: "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT)
		: "memory");
	} else
		return -ENOSYS;

	*uval = val;
	return ret;
}

#endif
#endif /* _ASM_FUTEX_H */
Commit	Line	Data
0004a9df RB	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (c) 2006 Ralf Baechle (ralf@linux-mips.org)
	7	*/
4732efbe JJ	8	#ifndef _ASM_FUTEX_H
	9	#define _ASM_FUTEX_H
	10
	11	#ifdef __KERNEL__
	12
	13	#include <linux/futex.h>
730f412c	14	#include <linux/uaccess.h>
a6813fe5	15	#include <asm/asm-eva.h>
0004a9df	16	#include <asm/barrier.h>
4732efbe	17	#include <asm/errno.h>
6ee1da94	18	#include <asm/war.h>
4732efbe	19
ebfaebae RB	20	#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
ebfaebae RB	21	{ \
6ee1da94 RB	22	if (cpu_has_llsc && R10000_LLSC_WAR) { \
	23	__asm__ __volatile__( \
	24	" .set push \n" \
	25	" .set noat \n" \
a809d460	26	" .set arch=r4000 \n" \
0307e8d0	27	"1: ll %1, %4 # __futex_atomic_op \n" \
6ee1da94 RB	28	" .set mips0 \n" \
6ee1da94 RB	29	" " insn " \n" \
a809d460	30	" .set arch=r4000 \n" \
0307e8d0	31	"2: sc $1, %2 \n" \
6ee1da94	32	" beqzl $1, 1b \n" \
17099b11	33	__WEAK_LLSC_MB \
6ee1da94 RB	34	"3: \n" \
	35	" .set pop \n" \
	36	" .set mips0 \n" \
	37	" .section .fixup,\"ax\" \n" \
0307e8d0	38	"4: li %0, %6 \n" \
0f67e90e	39	" j 3b \n" \
6ee1da94 RB	40	" .previous \n" \
	41	" .section __ex_table,\"a\" \n" \
	42	" "__UA_ADDR "\t1b, 4b \n" \
	43	" "__UA_ADDR "\t2b, 4b \n" \
	44	" .previous \n" \
0307e8d0 AN	45	: "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \
	46	: "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \
	47	: "memory"); \
6ee1da94 RB	48	} else if (cpu_has_llsc) { \
	49	__asm__ __volatile__( \
	50	" .set push \n" \
	51	" .set noat \n" \
a809d460	52	" .set arch=r4000 \n" \
a6813fe5	53	"1: "user_ll("%1", "%4")" # __futex_atomic_op\n" \
6ee1da94 RB	54	" .set mips0 \n" \
6ee1da94 RB	55	" " insn " \n" \
a809d460	56	" .set arch=r4000 \n" \
a6813fe5	57	"2: "user_sc("$1", "%2")" \n" \
6ee1da94	58	" beqz $1, 1b \n" \
17099b11	59	__WEAK_LLSC_MB \
6ee1da94 RB	60	"3: \n" \
	61	" .set pop \n" \
	62	" .set mips0 \n" \
	63	" .section .fixup,\"ax\" \n" \
0307e8d0	64	"4: li %0, %6 \n" \
0f67e90e	65	" j 3b \n" \
6ee1da94 RB	66	" .previous \n" \
	67	" .section __ex_table,\"a\" \n" \
	68	" "__UA_ADDR "\t1b, 4b \n" \
	69	" "__UA_ADDR "\t2b, 4b \n" \
	70	" .previous \n" \
0307e8d0 AN	71	: "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \
	72	: "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \
	73	: "memory"); \
6ee1da94 RB	74	} else \
6ee1da94 RB	75	ret = -ENOSYS; \
ebfaebae RB	76	}
ebfaebae RB	77
4732efbe	78	static inline int
8d7718aa	79	futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr)
4732efbe JJ	80	{
	81	int op = (encoded_op >> 28) & 7;
	82	int cmp = (encoded_op >> 24) & 15;
	83	int oparg = (encoded_op << 8) >> 20;
	84	int cmparg = (encoded_op << 20) >> 20;
	85	int oldval = 0, ret;
	86	if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
	87	oparg = 1 << oparg;
	88
8d7718aa	89	if (! access_ok (VERIFY_WRITE, uaddr, sizeof(u32)))
4732efbe JJ	90	return -EFAULT;
4732efbe JJ	91
a866374a	92	pagefault_disable();
4732efbe JJ	93
	94	switch (op) {
	95	case FUTEX_OP_SET:
70342287	96	__futex_atomic_op("move $1, %z5", ret, oldval, uaddr, oparg);
ebfaebae RB	97	break;
ebfaebae RB	98
4732efbe	99	case FUTEX_OP_ADD:
70342287 RB	100	__futex_atomic_op("addu $1, %1, %z5",
70342287 RB	101	ret, oldval, uaddr, oparg);
ebfaebae	102	break;
4732efbe	103	case FUTEX_OP_OR:
0307e8d0	104	__futex_atomic_op("or $1, %1, %z5",
70342287	105	ret, oldval, uaddr, oparg);
ebfaebae	106	break;
4732efbe	107	case FUTEX_OP_ANDN:
0307e8d0	108	__futex_atomic_op("and $1, %1, %z5",
70342287	109	ret, oldval, uaddr, ~oparg);
ebfaebae	110	break;
4732efbe	111	case FUTEX_OP_XOR:
0307e8d0	112	__futex_atomic_op("xor $1, %1, %z5",
70342287	113	ret, oldval, uaddr, oparg);
ebfaebae	114	break;
4732efbe JJ	115	default:
	116	ret = -ENOSYS;
	117	}
	118
a866374a	119	pagefault_enable();
4732efbe JJ	120
	121	if (!ret) {
	122	switch (cmp) {
	123	case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
	124	case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
	125	case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
	126	case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
	127	case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
	128	case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
	129	default: ret = -ENOSYS;
	130	}
	131	}
	132	return ret;
	133	}
	134
e9056f13	135	static inline int
8d7718aa ML	136	futex_atomic_cmpxchg_inatomic(u32 uval, u32 __user uaddr,
8d7718aa ML	137	u32 oldval, u32 newval)
e9056f13	138	{
8d7718aa ML	139	int ret = 0;
8d7718aa ML	140	u32 val;
6ee1da94	141
8d7718aa	142	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
6ee1da94 RB	143	return -EFAULT;
	144
	145	if (cpu_has_llsc && R10000_LLSC_WAR) {
	146	__asm__ __volatile__(
	147	"# futex_atomic_cmpxchg_inatomic \n"
	148	" .set push \n"
	149	" .set noat \n"
a809d460	150	" .set arch=r4000 \n"
37a9d912 ML	151	"1: ll %1, %3 \n"
37a9d912 ML	152	" bne %1, %z4, 3f \n"
6ee1da94	153	" .set mips0 \n"
37a9d912	154	" move $1, %z5 \n"
a809d460	155	" .set arch=r4000 \n"
37a9d912	156	"2: sc $1, %2 \n"
6ee1da94	157	" beqzl $1, 1b \n"
17099b11	158	__WEAK_LLSC_MB
6ee1da94 RB	159	"3: \n"
	160	" .set pop \n"
	161	" .section .fixup,\"ax\" \n"
37a9d912	162	"4: li %0, %6 \n"
6ee1da94 RB	163	" j 3b \n"
	164	" .previous \n"
	165	" .section __ex_table,\"a\" \n"
	166	" "__UA_ADDR "\t1b, 4b \n"
	167	" "__UA_ADDR "\t2b, 4b \n"
	168	" .previous \n"
37a9d912	169	: "+r" (ret), "=&r" (val), "=R" (*uaddr)
6ee1da94 RB	170	: "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT)
	171	: "memory");
	172	} else if (cpu_has_llsc) {
	173	__asm__ __volatile__(
	174	"# futex_atomic_cmpxchg_inatomic \n"
	175	" .set push \n"
	176	" .set noat \n"
a809d460	177	" .set arch=r4000 \n"
a6813fe5	178	"1: "user_ll("%1", "%3")" \n"
37a9d912	179	" bne %1, %z4, 3f \n"
6ee1da94	180	" .set mips0 \n"
37a9d912	181	" move $1, %z5 \n"
a809d460	182	" .set arch=r4000 \n"
a6813fe5	183	"2: "user_sc("$1", "%2")" \n"
6ee1da94	184	" beqz $1, 1b \n"
17099b11	185	__WEAK_LLSC_MB
6ee1da94 RB	186	"3: \n"
	187	" .set pop \n"
	188	" .section .fixup,\"ax\" \n"
37a9d912	189	"4: li %0, %6 \n"
6ee1da94 RB	190	" j 3b \n"
	191	" .previous \n"
	192	" .section __ex_table,\"a\" \n"
	193	" "__UA_ADDR "\t1b, 4b \n"
	194	" "__UA_ADDR "\t2b, 4b \n"
	195	" .previous \n"
37a9d912	196	: "+r" (ret), "=&r" (val), "=R" (*uaddr)
6ee1da94 RB	197	: "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT)
	198	: "memory");
	199	} else
	200	return -ENOSYS;
	201
37a9d912 ML	202	*uval = val;
37a9d912 ML	203	return ret;
e9056f13 IM	204	}
e9056f13 IM	205
4732efbe	206	#endif
0f67e90e	207	#endif /* _ASM_FUTEX_H */