[deliverable/linux.git] / arch / mips / include / asm / gic.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
 *
 * GIC Register Definitions
 *
 */
#ifndef _ASM_GICREGS_H
#define _ASM_GICREGS_H

#include <linux/bitmap.h>
#include <linux/threads.h>

#include <irq.h>

#undef	GICISBYTELITTLEENDIAN

#define GIC_MAX_INTRS			256

/* Constants */
#define GIC_POL_POS			1
#define GIC_POL_NEG			0
#define GIC_TRIG_EDGE			1
#define GIC_TRIG_LEVEL			0
#define GIC_TRIG_DUAL_ENABLE		1
#define GIC_TRIG_DUAL_DISABLE		0

#define MSK(n) ((1 << (n)) - 1)
#define REG32(addr)		(*(volatile unsigned int *) (addr))
#define REG(base, offs)		REG32((unsigned long)(base) + offs##_##OFS)
#define REGP(base, phys)	REG32((unsigned long)(base) + (phys))

/* Accessors */
#define GIC_REG(segment, offset) \
	REG32(_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
#define GIC_REG_ADDR(segment, offset) \
	REG32(_gic_base + segment##_##SECTION_OFS + offset)

#define GIC_ABS_REG(segment, offset) \
	(_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
#define GIC_REG_ABS_ADDR(segment, offset) \
	(_gic_base + segment##_##SECTION_OFS + offset)

#ifdef GICISBYTELITTLEENDIAN
#define GICREAD(reg, data)	((data) = (reg), (data) = le32_to_cpu(data))
#define GICWRITE(reg, data)	((reg) = cpu_to_le32(data))
#else
#define GICREAD(reg, data)	((data) = (reg))
#define GICWRITE(reg, data)	((reg) = (data))
#endif
#define GICBIS(reg, mask, bits)			\
	do { u32 data;				\
		GICREAD(reg, data);		\
		data &= ~(mask);		\
		data |= ((bits) & (mask));	\
		GICWRITE((reg), data);		\
	} while (0)


/* GIC Address Space */
#define SHARED_SECTION_OFS		0x0000
#define SHARED_SECTION_SIZE		0x8000
#define VPE_LOCAL_SECTION_OFS		0x8000
#define VPE_LOCAL_SECTION_SIZE		0x4000
#define VPE_OTHER_SECTION_OFS		0xc000
#define VPE_OTHER_SECTION_SIZE		0x4000
#define USM_VISIBLE_SECTION_OFS		0x10000
#define USM_VISIBLE_SECTION_SIZE	0x10000

/* Register Map for Shared Section */

#define GIC_SH_CONFIG_OFS		0x0000

/* Shared Global Counter */
#define GIC_SH_COUNTER_31_00_OFS	0x0010
#define GIC_SH_COUNTER_63_32_OFS	0x0014
#define GIC_SH_REVISIONID_OFS		0x0020

/* Interrupt Polarity */
#define GIC_SH_POL_31_0_OFS		0x0100
#define GIC_SH_POL_63_32_OFS		0x0104
#define GIC_SH_POL_95_64_OFS		0x0108
#define GIC_SH_POL_127_96_OFS		0x010c
#define GIC_SH_POL_159_128_OFS		0x0110
#define GIC_SH_POL_191_160_OFS		0x0114
#define GIC_SH_POL_223_192_OFS		0x0118
#define GIC_SH_POL_255_224_OFS		0x011c

/* Edge/Level Triggering */
#define GIC_SH_TRIG_31_0_OFS		0x0180
#define GIC_SH_TRIG_63_32_OFS		0x0184
#define GIC_SH_TRIG_95_64_OFS		0x0188
#define GIC_SH_TRIG_127_96_OFS		0x018c
#define GIC_SH_TRIG_159_128_OFS		0x0190
#define GIC_SH_TRIG_191_160_OFS		0x0194
#define GIC_SH_TRIG_223_192_OFS		0x0198
#define GIC_SH_TRIG_255_224_OFS		0x019c

/* Dual Edge Triggering */
#define GIC_SH_DUAL_31_0_OFS		0x0200
#define GIC_SH_DUAL_63_32_OFS		0x0204
#define GIC_SH_DUAL_95_64_OFS		0x0208
#define GIC_SH_DUAL_127_96_OFS		0x020c
#define GIC_SH_DUAL_159_128_OFS		0x0210
#define GIC_SH_DUAL_191_160_OFS		0x0214
#define GIC_SH_DUAL_223_192_OFS		0x0218
#define GIC_SH_DUAL_255_224_OFS		0x021c

/* Set/Clear corresponding bit in Edge Detect Register */
#define GIC_SH_WEDGE_OFS		0x0280

/* Reset Mask - Disables Interrupt */
#define GIC_SH_RMASK_31_0_OFS		0x0300
#define GIC_SH_RMASK_63_32_OFS		0x0304
#define GIC_SH_RMASK_95_64_OFS		0x0308
#define GIC_SH_RMASK_127_96_OFS		0x030c
#define GIC_SH_RMASK_159_128_OFS	0x0310
#define GIC_SH_RMASK_191_160_OFS	0x0314
#define GIC_SH_RMASK_223_192_OFS	0x0318
#define GIC_SH_RMASK_255_224_OFS	0x031c

/* Set Mask (WO) - Enables Interrupt */
#define GIC_SH_SMASK_31_0_OFS		0x0380
#define GIC_SH_SMASK_63_32_OFS		0x0384
#define GIC_SH_SMASK_95_64_OFS		0x0388
#define GIC_SH_SMASK_127_96_OFS		0x038c
#define GIC_SH_SMASK_159_128_OFS	0x0390
#define GIC_SH_SMASK_191_160_OFS	0x0394
#define GIC_SH_SMASK_223_192_OFS	0x0398
#define GIC_SH_SMASK_255_224_OFS	0x039c

/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
#define GIC_SH_MASK_31_0_OFS		0x0400
#define GIC_SH_MASK_63_32_OFS		0x0404
#define GIC_SH_MASK_95_64_OFS		0x0408
#define GIC_SH_MASK_127_96_OFS		0x040c
#define GIC_SH_MASK_159_128_OFS		0x0410
#define GIC_SH_MASK_191_160_OFS		0x0414
#define GIC_SH_MASK_223_192_OFS		0x0418
#define GIC_SH_MASK_255_224_OFS		0x041c

/* Pending Global Interrupts (RO) */
#define GIC_SH_PEND_31_0_OFS		0x0480
#define GIC_SH_PEND_63_32_OFS		0x0484
#define GIC_SH_PEND_95_64_OFS		0x0488
#define GIC_SH_PEND_127_96_OFS		0x048c
#define GIC_SH_PEND_159_128_OFS		0x0490
#define GIC_SH_PEND_191_160_OFS		0x0494
#define GIC_SH_PEND_223_192_OFS		0x0498
#define GIC_SH_PEND_255_224_OFS		0x049c

#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500

/* Maps Interrupt X to a Pin */
#define GIC_SH_MAP_TO_PIN(intr) \
	(GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))

#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000

/* Maps Interrupt X to a VPE */
#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
	(GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4))
#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe)	(1 << ((vpe) % 32))

/* Convert an interrupt number to a byte offset/bit for multi-word registers */
#define GIC_INTR_OFS(intr) (((intr) / 32)*4)
#define GIC_INTR_BIT(intr) ((intr) % 32)

/* Polarity : Reset Value is always 0 */
#define GIC_SH_SET_POLARITY_OFS		0x0100
#define GIC_SET_POLARITY(intr, pol) \
	GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + \
		GIC_INTR_OFS(intr)), (1 << GIC_INTR_BIT(intr)), \
		(pol) << GIC_INTR_BIT(intr))

/* Triggering : Reset Value is always 0 */
#define GIC_SH_SET_TRIGGER_OFS		0x0180
#define GIC_SET_TRIGGER(intr, trig) \
	GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + \
		GIC_INTR_OFS(intr)), (1 << GIC_INTR_BIT(intr)), \
		(trig) << GIC_INTR_BIT(intr))

/* Dual edge triggering : Reset Value is always 0 */
#define GIC_SH_SET_DUAL_OFS		0x0200
#define GIC_SET_DUAL(intr, dual) \
	GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_DUAL_OFS + \
		GIC_INTR_OFS(intr)), (1 << GIC_INTR_BIT(intr)), \
		(dual) << GIC_INTR_BIT(intr))

/* Mask manipulation */
#define GIC_SH_SMASK_OFS		0x0380
#define GIC_SET_INTR_MASK(intr) \
	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + \
		GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
#define GIC_SH_RMASK_OFS		0x0300
#define GIC_CLR_INTR_MASK(intr) \
	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + \
		GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))

/* Register Map for Local Section */
#define GIC_VPE_CTL_OFS			0x0000
#define GIC_VPE_PEND_OFS		0x0004
#define GIC_VPE_MASK_OFS		0x0008
#define GIC_VPE_RMASK_OFS		0x000c
#define GIC_VPE_SMASK_OFS		0x0010
#define GIC_VPE_WD_MAP_OFS		0x0040
#define GIC_VPE_COMPARE_MAP_OFS		0x0044
#define GIC_VPE_TIMER_MAP_OFS		0x0048
#define GIC_VPE_FDC_MAP_OFS		0x004c
#define GIC_VPE_PERFCTR_MAP_OFS		0x0050
#define GIC_VPE_SWINT0_MAP_OFS		0x0054
#define GIC_VPE_SWINT1_MAP_OFS		0x0058
#define GIC_VPE_OTHER_ADDR_OFS		0x0080
#define GIC_VPE_WD_CONFIG0_OFS		0x0090
#define GIC_VPE_WD_COUNT0_OFS		0x0094
#define GIC_VPE_WD_INITIAL0_OFS		0x0098
#define GIC_VPE_COMPARE_LO_OFS		0x00a0
#define GIC_VPE_COMPARE_HI_OFS		0x00a4

#define GIC_VPE_EIC_SHADOW_SET_BASE	0x0100
#define GIC_VPE_EIC_SS(intr) \
	(GIC_VPE_EIC_SHADOW_SET_BASE + (4 * intr))

#define GIC_VPE_EIC_VEC_BASE		0x0800
#define GIC_VPE_EIC_VEC(intr) \
	(GIC_VPE_EIC_VEC_BASE + (4 * intr))

#define GIC_VPE_TENABLE_NMI_OFS		0x1000
#define GIC_VPE_TENABLE_YQ_OFS		0x1004
#define GIC_VPE_TENABLE_INT_31_0_OFS	0x1080
#define GIC_VPE_TENABLE_INT_63_32_OFS	0x1084

/* User Mode Visible Section Register Map */
#define GIC_UMV_SH_COUNTER_31_00_OFS	0x0000
#define GIC_UMV_SH_COUNTER_63_32_OFS	0x0004

/* Masks */
#define GIC_SH_CONFIG_COUNTSTOP_SHF	28
#define GIC_SH_CONFIG_COUNTSTOP_MSK	(MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)

#define GIC_SH_CONFIG_COUNTBITS_SHF	24
#define GIC_SH_CONFIG_COUNTBITS_MSK	(MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)

#define GIC_SH_CONFIG_NUMINTRS_SHF	16
#define GIC_SH_CONFIG_NUMINTRS_MSK	(MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)

#define GIC_SH_CONFIG_NUMVPES_SHF	0
#define GIC_SH_CONFIG_NUMVPES_MSK	(MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF)

#define GIC_SH_WEDGE_SET(intr)		(intr | (0x1 << 31))
#define GIC_SH_WEDGE_CLR(intr)		(intr & ~(0x1 << 31))

#define GIC_MAP_TO_PIN_SHF		31
#define GIC_MAP_TO_PIN_MSK		(MSK(1) << GIC_MAP_TO_PIN_SHF)
#define GIC_MAP_TO_NMI_SHF		30
#define GIC_MAP_TO_NMI_MSK		(MSK(1) << GIC_MAP_TO_NMI_SHF)
#define GIC_MAP_TO_YQ_SHF		29
#define GIC_MAP_TO_YQ_MSK		(MSK(1) << GIC_MAP_TO_YQ_SHF)
#define GIC_MAP_SHF			0
#define GIC_MAP_MSK			(MSK(6) << GIC_MAP_SHF)

/* GIC_VPE_CTL Masks */
#define GIC_VPE_CTL_FDC_RTBL_SHF	4
#define GIC_VPE_CTL_FDC_RTBL_MSK	(MSK(1) << GIC_VPE_CTL_FDC_RTBL_SHF)
#define GIC_VPE_CTL_SWINT_RTBL_SHF	3
#define GIC_VPE_CTL_SWINT_RTBL_MSK	(MSK(1) << GIC_VPE_CTL_SWINT_RTBL_SHF)
#define GIC_VPE_CTL_PERFCNT_RTBL_SHF	2
#define GIC_VPE_CTL_PERFCNT_RTBL_MSK	(MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF)
#define GIC_VPE_CTL_TIMER_RTBL_SHF	1
#define GIC_VPE_CTL_TIMER_RTBL_MSK	(MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF)
#define GIC_VPE_CTL_EIC_MODE_SHF	0
#define GIC_VPE_CTL_EIC_MODE_MSK	(MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF)

/* GIC_VPE_PEND Masks */
#define GIC_VPE_PEND_WD_SHF		0
#define GIC_VPE_PEND_WD_MSK		(MSK(1) << GIC_VPE_PEND_WD_SHF)
#define GIC_VPE_PEND_CMP_SHF		1
#define GIC_VPE_PEND_CMP_MSK		(MSK(1) << GIC_VPE_PEND_CMP_SHF)
#define GIC_VPE_PEND_TIMER_SHF		2
#define GIC_VPE_PEND_TIMER_MSK		(MSK(1) << GIC_VPE_PEND_TIMER_SHF)
#define GIC_VPE_PEND_PERFCOUNT_SHF	3
#define GIC_VPE_PEND_PERFCOUNT_MSK	(MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF)
#define GIC_VPE_PEND_SWINT0_SHF		4
#define GIC_VPE_PEND_SWINT0_MSK		(MSK(1) << GIC_VPE_PEND_SWINT0_SHF)
#define GIC_VPE_PEND_SWINT1_SHF		5
#define GIC_VPE_PEND_SWINT1_MSK		(MSK(1) << GIC_VPE_PEND_SWINT1_SHF)

/* GIC_VPE_RMASK Masks */
#define GIC_VPE_RMASK_WD_SHF		0
#define GIC_VPE_RMASK_WD_MSK		(MSK(1) << GIC_VPE_RMASK_WD_SHF)
#define GIC_VPE_RMASK_CMP_SHF		1
#define GIC_VPE_RMASK_CMP_MSK		(MSK(1) << GIC_VPE_RMASK_CMP_SHF)
#define GIC_VPE_RMASK_TIMER_SHF		2
#define GIC_VPE_RMASK_TIMER_MSK		(MSK(1) << GIC_VPE_RMASK_TIMER_SHF)
#define GIC_VPE_RMASK_PERFCNT_SHF	3
#define GIC_VPE_RMASK_PERFCNT_MSK	(MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF)
#define GIC_VPE_RMASK_SWINT0_SHF	4
#define GIC_VPE_RMASK_SWINT0_MSK	(MSK(1) << GIC_VPE_RMASK_SWINT0_SHF)
#define GIC_VPE_RMASK_SWINT1_SHF	5
#define GIC_VPE_RMASK_SWINT1_MSK	(MSK(1) << GIC_VPE_RMASK_SWINT1_SHF)

/* GIC_VPE_SMASK Masks */
#define GIC_VPE_SMASK_WD_SHF		0
#define GIC_VPE_SMASK_WD_MSK		(MSK(1) << GIC_VPE_SMASK_WD_SHF)
#define GIC_VPE_SMASK_CMP_SHF		1
#define GIC_VPE_SMASK_CMP_MSK		(MSK(1) << GIC_VPE_SMASK_CMP_SHF)
#define GIC_VPE_SMASK_TIMER_SHF		2
#define GIC_VPE_SMASK_TIMER_MSK		(MSK(1) << GIC_VPE_SMASK_TIMER_SHF)
#define GIC_VPE_SMASK_PERFCNT_SHF	3
#define GIC_VPE_SMASK_PERFCNT_MSK	(MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF)
#define GIC_VPE_SMASK_SWINT0_SHF	4
#define GIC_VPE_SMASK_SWINT0_MSK	(MSK(1) << GIC_VPE_SMASK_SWINT0_SHF)
#define GIC_VPE_SMASK_SWINT1_SHF	5
#define GIC_VPE_SMASK_SWINT1_MSK	(MSK(1) << GIC_VPE_SMASK_SWINT1_SHF)

/*
 * Set the Mapping of Interrupt X to a VPE.
 */
#define GIC_SH_MAP_TO_VPE_SMASK(intr, vpe) \
	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe)), \
		 GIC_SH_MAP_TO_VPE_REG_BIT(vpe))

/* GIC nomenclature for Core Interrupt Pins. */
#define GIC_CPU_INT0		0 /* Core Interrupt 2 */
#define GIC_CPU_INT1		1 /* .		      */
#define GIC_CPU_INT2		2 /* .		      */
#define GIC_CPU_INT3		3 /* .		      */
#define GIC_CPU_INT4		4 /* .		      */
#define GIC_CPU_INT5		5 /* Core Interrupt 7 */

/* Add 2 to convert GIC CPU pin to core interrupt */
#define GIC_CPU_PIN_OFFSET	2

/* Add 2 to convert non-EIC hardware interrupt to EIC vector number. */
#define GIC_CPU_TO_VEC_OFFSET	(2)

/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
#define GIC_PIN_TO_VEC_OFFSET	(1)

/* Local GIC interrupts. */
#define GIC_LOCAL_INT_WD	0 /* GIC watchdog */
#define GIC_LOCAL_INT_COMPARE	1 /* GIC count and compare timer */
#define GIC_LOCAL_INT_TIMER	2 /* CPU timer interrupt */
#define GIC_LOCAL_INT_PERFCTR	3 /* CPU performance counter */
#define GIC_LOCAL_INT_SWINT0	4 /* CPU software interrupt 0 */
#define GIC_LOCAL_INT_SWINT1	5 /* CPU software interrupt 1 */
#define GIC_LOCAL_INT_FDC	6 /* CPU fast debug channel */
#define GIC_NUM_LOCAL_INTRS	7

/* Convert between local/shared IRQ number and GIC HW IRQ number. */
#define GIC_LOCAL_HWIRQ_BASE	0
#define GIC_LOCAL_TO_HWIRQ(x)	(GIC_LOCAL_HWIRQ_BASE + (x))
#define GIC_HWIRQ_TO_LOCAL(x)	((x) - GIC_LOCAL_HWIRQ_BASE)
#define GIC_SHARED_HWIRQ_BASE	GIC_NUM_LOCAL_INTRS
#define GIC_SHARED_TO_HWIRQ(x)	(GIC_SHARED_HWIRQ_BASE + (x))
#define GIC_HWIRQ_TO_SHARED(x)	((x) - GIC_SHARED_HWIRQ_BASE)

#include <linux/clocksource.h>
#include <linux/irq.h>

extern unsigned int gic_present;
extern unsigned int gic_frequency;
extern unsigned long _gic_base;

extern void gic_init(unsigned long gic_base_addr,
	unsigned long gic_addrspace_size, unsigned int cpu_vec,
	unsigned int irqbase);
extern void gic_clocksource_init(unsigned int);
extern cycle_t gic_read_count(void);
extern unsigned int gic_get_count_width(void);
extern cycle_t gic_read_compare(void);
extern void gic_write_compare(cycle_t cnt);
extern void gic_write_cpu_compare(cycle_t cnt, int cpu);
extern void gic_send_ipi(unsigned int intr);
extern unsigned int plat_ipi_call_int_xlate(unsigned int);
extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
extern unsigned int gic_get_timer_pending(void);
extern int gic_get_c0_compare_int(void);
extern int gic_get_c0_perfcount_int(void);
#endif /* _ASM_GICREGS_H */
Commit	Line	Data
39b8d525 RB	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2000, 07 MIPS Technologies, Inc.
	7	*
	8	* GIC Register Definitions
	9	*
	10	*/
	11	#ifndef _ASM_GICREGS_H
	12	#define _ASM_GICREGS_H
	13
6d9727a7 PB	14	#include <linux/bitmap.h>
	15	#include <linux/threads.h>
	16
c9750481 JD	17	#include <irq.h>
c9750481 JD	18
39b8d525	19	#undef GICISBYTELITTLEENDIAN
39b8d525	20
fbd55241 AB	21	#define GIC_MAX_INTRS 256
fbd55241 AB	22
39b8d525 RB	23	/* Constants */
	24	#define GIC_POL_POS 1
	25	#define GIC_POL_NEG 0
	26	#define GIC_TRIG_EDGE 1
	27	#define GIC_TRIG_LEVEL 0
95150ae8 AB	28	#define GIC_TRIG_DUAL_ENABLE 1
95150ae8 AB	29	#define GIC_TRIG_DUAL_DISABLE 0
39b8d525	30
39b8d525 RB	31	#define MSK(n) ((1 << (n)) - 1)
39b8d525 RB	32	#define REG32(addr) ((volatile unsigned int ) (addr))
938b2b14 TB	33	#define REG(base, offs) REG32((unsigned long)(base) + offs##_##OFS)
938b2b14 TB	34	#define REGP(base, phys) REG32((unsigned long)(base) + (phys))
39b8d525 RB	35
	36	/* Accessors */
	37	#define GIC_REG(segment, offset) \
	38	REG32(_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
	39	#define GIC_REG_ADDR(segment, offset) \
	40	REG32(_gic_base + segment##_##SECTION_OFS + offset)
	41
	42	#define GIC_ABS_REG(segment, offset) \
2299c49d	43	(_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
39b8d525	44	#define GIC_REG_ABS_ADDR(segment, offset) \
2299c49d	45	(_gic_base + segment##_##SECTION_OFS + offset)
39b8d525 RB	46
39b8d525 RB	47	#ifdef GICISBYTELITTLEENDIAN
2299c49d SH	48	#define GICREAD(reg, data) ((data) = (reg), (data) = le32_to_cpu(data))
2299c49d SH	49	#define GICWRITE(reg, data) ((reg) = cpu_to_le32(data))
39b8d525	50	#else
2299c49d SH	51	#define GICREAD(reg, data) ((data) = (reg))
2299c49d SH	52	#define GICWRITE(reg, data) ((reg) = (data))
39b8d525	53	#endif
c55b2851 JD	54	#define GICBIS(reg, mask, bits) \
c55b2851 JD	55	do { u32 data; \
f28ff3d1	56	GICREAD(reg, data); \
c55b2851 JD	57	data &= ~(mask); \
	58	data \|= ((bits) & (mask)); \
	59	GICWRITE((reg), data); \
	60	} while (0)
39b8d525 RB	61
	62
	63	/* GIC Address Space */
	64	#define SHARED_SECTION_OFS 0x0000
	65	#define SHARED_SECTION_SIZE 0x8000
	66	#define VPE_LOCAL_SECTION_OFS 0x8000
	67	#define VPE_LOCAL_SECTION_SIZE 0x4000
	68	#define VPE_OTHER_SECTION_OFS 0xc000
	69	#define VPE_OTHER_SECTION_SIZE 0x4000
	70	#define USM_VISIBLE_SECTION_OFS 0x10000
	71	#define USM_VISIBLE_SECTION_SIZE 0x10000
	72
	73	/* Register Map for Shared Section */
39b8d525	74
70342287	75	#define GIC_SH_CONFIG_OFS 0x0000
39b8d525 RB	76
	77	/* Shared Global Counter */
	78	#define GIC_SH_COUNTER_31_00_OFS 0x0010
	79	#define GIC_SH_COUNTER_63_32_OFS 0x0014
7098f748	80	#define GIC_SH_REVISIONID_OFS 0x0020
39b8d525 RB	81
	82	/* Interrupt Polarity */
	83	#define GIC_SH_POL_31_0_OFS 0x0100
	84	#define GIC_SH_POL_63_32_OFS 0x0104
	85	#define GIC_SH_POL_95_64_OFS 0x0108
	86	#define GIC_SH_POL_127_96_OFS 0x010c
	87	#define GIC_SH_POL_159_128_OFS 0x0110
	88	#define GIC_SH_POL_191_160_OFS 0x0114
	89	#define GIC_SH_POL_223_192_OFS 0x0118
	90	#define GIC_SH_POL_255_224_OFS 0x011c
	91
	92	/* Edge/Level Triggering */
	93	#define GIC_SH_TRIG_31_0_OFS 0x0180
	94	#define GIC_SH_TRIG_63_32_OFS 0x0184
	95	#define GIC_SH_TRIG_95_64_OFS 0x0188
	96	#define GIC_SH_TRIG_127_96_OFS 0x018c
	97	#define GIC_SH_TRIG_159_128_OFS 0x0190
	98	#define GIC_SH_TRIG_191_160_OFS 0x0194
	99	#define GIC_SH_TRIG_223_192_OFS 0x0198
	100	#define GIC_SH_TRIG_255_224_OFS 0x019c
	101
	102	/* Dual Edge Triggering */
	103	#define GIC_SH_DUAL_31_0_OFS 0x0200
	104	#define GIC_SH_DUAL_63_32_OFS 0x0204
	105	#define GIC_SH_DUAL_95_64_OFS 0x0208
	106	#define GIC_SH_DUAL_127_96_OFS 0x020c
	107	#define GIC_SH_DUAL_159_128_OFS 0x0210
	108	#define GIC_SH_DUAL_191_160_OFS 0x0214
	109	#define GIC_SH_DUAL_223_192_OFS 0x0218
	110	#define GIC_SH_DUAL_255_224_OFS 0x021c
	111
	112	/* Set/Clear corresponding bit in Edge Detect Register */
	113	#define GIC_SH_WEDGE_OFS 0x0280
	114
	115	/* Reset Mask - Disables Interrupt */
	116	#define GIC_SH_RMASK_31_0_OFS 0x0300
	117	#define GIC_SH_RMASK_63_32_OFS 0x0304
	118	#define GIC_SH_RMASK_95_64_OFS 0x0308
	119	#define GIC_SH_RMASK_127_96_OFS 0x030c
	120	#define GIC_SH_RMASK_159_128_OFS 0x0310
	121	#define GIC_SH_RMASK_191_160_OFS 0x0314
	122	#define GIC_SH_RMASK_223_192_OFS 0x0318
	123	#define GIC_SH_RMASK_255_224_OFS 0x031c
	124
	125	/* Set Mask (WO) - Enables Interrupt */
	126	#define GIC_SH_SMASK_31_0_OFS 0x0380
	127	#define GIC_SH_SMASK_63_32_OFS 0x0384
	128	#define GIC_SH_SMASK_95_64_OFS 0x0388
	129	#define GIC_SH_SMASK_127_96_OFS 0x038c
	130	#define GIC_SH_SMASK_159_128_OFS 0x0390
	131	#define GIC_SH_SMASK_191_160_OFS 0x0394
	132	#define GIC_SH_SMASK_223_192_OFS 0x0398
	133	#define GIC_SH_SMASK_255_224_OFS 0x039c
	134
	135	/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
	136	#define GIC_SH_MASK_31_0_OFS 0x0400
	137	#define GIC_SH_MASK_63_32_OFS 0x0404
	138	#define GIC_SH_MASK_95_64_OFS 0x0408
	139	#define GIC_SH_MASK_127_96_OFS 0x040c
	140	#define GIC_SH_MASK_159_128_OFS 0x0410
	141	#define GIC_SH_MASK_191_160_OFS 0x0414
	142	#define GIC_SH_MASK_223_192_OFS 0x0418
	143	#define GIC_SH_MASK_255_224_OFS 0x041c
	144
145	/* Pending Global Interrupts (RO) */
146	#define GIC_SH_PEND_31_0_OFS 0x0480
147	#define GIC_SH_PEND_63_32_OFS 0x0484
148	#define GIC_SH_PEND_95_64_OFS 0x0488
149	#define GIC_SH_PEND_127_96_OFS 0x048c
150	#define GIC_SH_PEND_159_128_OFS 0x0490
151	#define GIC_SH_PEND_191_160_OFS 0x0494
152	#define GIC_SH_PEND_223_192_OFS 0x0498
153	#define GIC_SH_PEND_255_224_OFS 0x049c
154
70342287	155	#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
39b8d525 RB	156
	157	/* Maps Interrupt X to a Pin */
	158	#define GIC_SH_MAP_TO_PIN(intr) \
	159	(GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
	160
70342287	161	#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000
39b8d525 RB	162
	163	/* Maps Interrupt X to a VPE */
	164	#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
	165	(GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4))
	166	#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
	167
7098f748 CD	168	/* Convert an interrupt number to a byte offset/bit for multi-word registers */
	169	#define GIC_INTR_OFS(intr) (((intr) / 32)*4)
	170	#define GIC_INTR_BIT(intr) ((intr) % 32)
	171
39b8d525 RB	172	/* Polarity : Reset Value is always 0 */
	173	#define GIC_SH_SET_POLARITY_OFS 0x0100
	174	#define GIC_SET_POLARITY(intr, pol) \
7098f748	175	GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + \
c55b2851 JD	176	GIC_INTR_OFS(intr)), (1 << GIC_INTR_BIT(intr)), \
c55b2851 JD	177	(pol) << GIC_INTR_BIT(intr))
39b8d525 RB	178
	179	/* Triggering : Reset Value is always 0 */
	180	#define GIC_SH_SET_TRIGGER_OFS 0x0180
	181	#define GIC_SET_TRIGGER(intr, trig) \
7098f748	182	GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + \
c55b2851 JD	183	GIC_INTR_OFS(intr)), (1 << GIC_INTR_BIT(intr)), \
c55b2851 JD	184	(trig) << GIC_INTR_BIT(intr))
39b8d525	185
95150ae8 AB	186	/* Dual edge triggering : Reset Value is always 0 */
	187	#define GIC_SH_SET_DUAL_OFS 0x0200
	188	#define GIC_SET_DUAL(intr, dual) \
	189	GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_DUAL_OFS + \
	190	GIC_INTR_OFS(intr)), (1 << GIC_INTR_BIT(intr)), \
	191	(dual) << GIC_INTR_BIT(intr))
	192
39b8d525 RB	193	/* Mask manipulation */
39b8d525 RB	194	#define GIC_SH_SMASK_OFS 0x0380
7098f748 CD	195	#define GIC_SET_INTR_MASK(intr) \
	196	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + \
	197	GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
39b8d525	198	#define GIC_SH_RMASK_OFS 0x0300
7098f748 CD	199	#define GIC_CLR_INTR_MASK(intr) \
	200	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + \
	201	GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
39b8d525 RB	202
	203	/* Register Map for Local Section */
	204	#define GIC_VPE_CTL_OFS 0x0000
	205	#define GIC_VPE_PEND_OFS 0x0004
	206	#define GIC_VPE_MASK_OFS 0x0008
	207	#define GIC_VPE_RMASK_OFS 0x000c
	208	#define GIC_VPE_SMASK_OFS 0x0010
	209	#define GIC_VPE_WD_MAP_OFS 0x0040
	210	#define GIC_VPE_COMPARE_MAP_OFS 0x0044
	211	#define GIC_VPE_TIMER_MAP_OFS 0x0048
e9de688d	212	#define GIC_VPE_FDC_MAP_OFS 0x004c
39b8d525 RB	213	#define GIC_VPE_PERFCTR_MAP_OFS 0x0050
	214	#define GIC_VPE_SWINT0_MAP_OFS 0x0054
	215	#define GIC_VPE_SWINT1_MAP_OFS 0x0058
	216	#define GIC_VPE_OTHER_ADDR_OFS 0x0080
	217	#define GIC_VPE_WD_CONFIG0_OFS 0x0090
	218	#define GIC_VPE_WD_COUNT0_OFS 0x0094
	219	#define GIC_VPE_WD_INITIAL0_OFS 0x0098
	220	#define GIC_VPE_COMPARE_LO_OFS 0x00a0
0ab2b7d0	221	#define GIC_VPE_COMPARE_HI_OFS 0x00a4
39b8d525 RB	222
	223	#define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100
	224	#define GIC_VPE_EIC_SS(intr) \
f0b77f2c	225	(GIC_VPE_EIC_SHADOW_SET_BASE + (4 * intr))
39b8d525 RB	226
	227	#define GIC_VPE_EIC_VEC_BASE 0x0800
	228	#define GIC_VPE_EIC_VEC(intr) \
	229	(GIC_VPE_EIC_VEC_BASE + (4 * intr))
	230
	231	#define GIC_VPE_TENABLE_NMI_OFS 0x1000
	232	#define GIC_VPE_TENABLE_YQ_OFS 0x1004
	233	#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080
	234	#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084
	235
	236	/* User Mode Visible Section Register Map */
	237	#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000
	238	#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004
	239
39b8d525 RB	240	/* Masks */
	241	#define GIC_SH_CONFIG_COUNTSTOP_SHF 28
	242	#define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
	243
	244	#define GIC_SH_CONFIG_COUNTBITS_SHF 24
	245	#define GIC_SH_CONFIG_COUNTBITS_MSK (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)
	246
	247	#define GIC_SH_CONFIG_NUMINTRS_SHF 16
	248	#define GIC_SH_CONFIG_NUMINTRS_MSK (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)
	249
	250	#define GIC_SH_CONFIG_NUMVPES_SHF 0
	251	#define GIC_SH_CONFIG_NUMVPES_MSK (MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF)
	252
	253	#define GIC_SH_WEDGE_SET(intr) (intr \| (0x1 << 31))
	254	#define GIC_SH_WEDGE_CLR(intr) (intr & ~(0x1 << 31))
	255
	256	#define GIC_MAP_TO_PIN_SHF 31
	257	#define GIC_MAP_TO_PIN_MSK (MSK(1) << GIC_MAP_TO_PIN_SHF)
	258	#define GIC_MAP_TO_NMI_SHF 30
	259	#define GIC_MAP_TO_NMI_MSK (MSK(1) << GIC_MAP_TO_NMI_SHF)
	260	#define GIC_MAP_TO_YQ_SHF 29
	261	#define GIC_MAP_TO_YQ_MSK (MSK(1) << GIC_MAP_TO_YQ_SHF)
	262	#define GIC_MAP_SHF 0
	263	#define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF)
	264
	265	/* GIC_VPE_CTL Masks */
e9de688d AB	266	#define GIC_VPE_CTL_FDC_RTBL_SHF 4
	267	#define GIC_VPE_CTL_FDC_RTBL_MSK (MSK(1) << GIC_VPE_CTL_FDC_RTBL_SHF)
	268	#define GIC_VPE_CTL_SWINT_RTBL_SHF 3
	269	#define GIC_VPE_CTL_SWINT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_SWINT_RTBL_SHF)
39b8d525 RB	270	#define GIC_VPE_CTL_PERFCNT_RTBL_SHF 2
	271	#define GIC_VPE_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF)
	272	#define GIC_VPE_CTL_TIMER_RTBL_SHF 1
	273	#define GIC_VPE_CTL_TIMER_RTBL_MSK (MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF)
	274	#define GIC_VPE_CTL_EIC_MODE_SHF 0
	275	#define GIC_VPE_CTL_EIC_MODE_MSK (MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF)
	276
	277	/* GIC_VPE_PEND Masks */
	278	#define GIC_VPE_PEND_WD_SHF 0
	279	#define GIC_VPE_PEND_WD_MSK (MSK(1) << GIC_VPE_PEND_WD_SHF)
	280	#define GIC_VPE_PEND_CMP_SHF 1
	281	#define GIC_VPE_PEND_CMP_MSK (MSK(1) << GIC_VPE_PEND_CMP_SHF)
	282	#define GIC_VPE_PEND_TIMER_SHF 2
	283	#define GIC_VPE_PEND_TIMER_MSK (MSK(1) << GIC_VPE_PEND_TIMER_SHF)
	284	#define GIC_VPE_PEND_PERFCOUNT_SHF 3
	285	#define GIC_VPE_PEND_PERFCOUNT_MSK (MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF)
	286	#define GIC_VPE_PEND_SWINT0_SHF 4
	287	#define GIC_VPE_PEND_SWINT0_MSK (MSK(1) << GIC_VPE_PEND_SWINT0_SHF)
	288	#define GIC_VPE_PEND_SWINT1_SHF 5
	289	#define GIC_VPE_PEND_SWINT1_MSK (MSK(1) << GIC_VPE_PEND_SWINT1_SHF)
	290
	291	/* GIC_VPE_RMASK Masks */
	292	#define GIC_VPE_RMASK_WD_SHF 0
	293	#define GIC_VPE_RMASK_WD_MSK (MSK(1) << GIC_VPE_RMASK_WD_SHF)
	294	#define GIC_VPE_RMASK_CMP_SHF 1
	295	#define GIC_VPE_RMASK_CMP_MSK (MSK(1) << GIC_VPE_RMASK_CMP_SHF)
	296	#define GIC_VPE_RMASK_TIMER_SHF 2
	297	#define GIC_VPE_RMASK_TIMER_MSK (MSK(1) << GIC_VPE_RMASK_TIMER_SHF)
	298	#define GIC_VPE_RMASK_PERFCNT_SHF 3
	299	#define GIC_VPE_RMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF)
	300	#define GIC_VPE_RMASK_SWINT0_SHF 4
	301	#define GIC_VPE_RMASK_SWINT0_MSK (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF)
	302	#define GIC_VPE_RMASK_SWINT1_SHF 5
	303	#define GIC_VPE_RMASK_SWINT1_MSK (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF)
	304
	305	/* GIC_VPE_SMASK Masks */
	306	#define GIC_VPE_SMASK_WD_SHF 0
	307	#define GIC_VPE_SMASK_WD_MSK (MSK(1) << GIC_VPE_SMASK_WD_SHF)
	308	#define GIC_VPE_SMASK_CMP_SHF 1
	309	#define GIC_VPE_SMASK_CMP_MSK (MSK(1) << GIC_VPE_SMASK_CMP_SHF)
	310	#define GIC_VPE_SMASK_TIMER_SHF 2
	311	#define GIC_VPE_SMASK_TIMER_MSK (MSK(1) << GIC_VPE_SMASK_TIMER_SHF)
	312	#define GIC_VPE_SMASK_PERFCNT_SHF 3
	313	#define GIC_VPE_SMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF)
	314	#define GIC_VPE_SMASK_SWINT0_SHF 4
	315	#define GIC_VPE_SMASK_SWINT0_MSK (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF)
	316	#define GIC_VPE_SMASK_SWINT1_SHF 5
	317	#define GIC_VPE_SMASK_SWINT1_MSK (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF)
	318
	319	/*
	320	* Set the Mapping of Interrupt X to a VPE.
	321	*/
	322	#define GIC_SH_MAP_TO_VPE_SMASK(intr, vpe) \
	323	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe)), \
	324	GIC_SH_MAP_TO_VPE_REG_BIT(vpe))
	325
0b271f56 SH	326	/* GIC nomenclature for Core Interrupt Pins. */
0b271f56 SH	327	#define GIC_CPU_INT0 0 /* Core Interrupt 2 */
70342287 RB	328	#define GIC_CPU_INT1 1 /* . */
	329	#define GIC_CPU_INT2 2 /* . */
	330	#define GIC_CPU_INT3 3 /* . */
	331	#define GIC_CPU_INT4 4 /* . */
42a11179	332	#define GIC_CPU_INT5 5 /* Core Interrupt 7 */
0b271f56	333
18743d27 AB	334	/* Add 2 to convert GIC CPU pin to core interrupt */
	335	#define GIC_CPU_PIN_OFFSET 2
	336
0b271f56 SH	337	/* Add 2 to convert non-EIC hardware interrupt to EIC vector number. */
	338	#define GIC_CPU_TO_VEC_OFFSET (2)
	339
	340	/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
	341	#define GIC_PIN_TO_VEC_OFFSET (1)
	342
e9de688d AB	343	/* Local GIC interrupts. */
	344	#define GIC_LOCAL_INT_WD 0 /* GIC watchdog */
	345	#define GIC_LOCAL_INT_COMPARE 1 /* GIC count and compare timer */
	346	#define GIC_LOCAL_INT_TIMER 2 /* CPU timer interrupt */
	347	#define GIC_LOCAL_INT_PERFCTR 3 /* CPU performance counter */
	348	#define GIC_LOCAL_INT_SWINT0 4 /* CPU software interrupt 0 */
	349	#define GIC_LOCAL_INT_SWINT1 5 /* CPU software interrupt 1 */
	350	#define GIC_LOCAL_INT_FDC 6 /* CPU fast debug channel */
	351	#define GIC_NUM_LOCAL_INTRS 7
	352
	353	/* Convert between local/shared IRQ number and GIC HW IRQ number. */
	354	#define GIC_LOCAL_HWIRQ_BASE 0
	355	#define GIC_LOCAL_TO_HWIRQ(x) (GIC_LOCAL_HWIRQ_BASE + (x))
	356	#define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
	357	#define GIC_SHARED_HWIRQ_BASE GIC_NUM_LOCAL_INTRS
	358	#define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x))
	359	#define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
	360
dfa762e1 SH	361	#include <linux/clocksource.h>
	362	#include <linux/irq.h>
	363
ff86714f	364	extern unsigned int gic_present;
28ea2151	365	extern unsigned int gic_frequency;
0b271f56	366	extern unsigned long _gic_base;
0b271f56	367
39b8d525	368	extern void gic_init(unsigned long gic_base_addr,
18743d27 AB	369	unsigned long gic_addrspace_size, unsigned int cpu_vec,
18743d27 AB	370	unsigned int irqbase);
0b271f56	371	extern void gic_clocksource_init(unsigned int);
dfa762e1	372	extern cycle_t gic_read_count(void);
387904ff	373	extern unsigned int gic_get_count_width(void);
0ab2b7d0 RG	374	extern cycle_t gic_read_compare(void);
0ab2b7d0 RG	375	extern void gic_write_compare(cycle_t cnt);
414408d0	376	extern void gic_write_cpu_compare(cycle_t cnt, int cpu);
39b8d525	377	extern void gic_send_ipi(unsigned int intr);
0365070f TA	378	extern unsigned int plat_ipi_call_int_xlate(unsigned int);
0365070f TA	379	extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
f0b77f2c	380	extern unsigned int gic_get_timer_pending(void);
e9de688d AB	381	extern int gic_get_c0_compare_int(void);
e9de688d AB	382	extern int gic_get_c0_perfcount_int(void);
39b8d525	383	#endif /* _ASM_GICREGS_H */