projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * include/asm-mips/i8259.h | |
| 3 | * | |
| 4 | * i8259A interrupt definitions. | |
| 5 | * | |
| 6 | * Copyright (C) 2003 Maciej W. Rozycki | |
| 7 | * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or | |
| 10 | * modify it under the terms of the GNU General Public License | |
| 11 | * as published by the Free Software Foundation; either version | |
| 12 | * 2 of the License, or (at your option) any later version. | |
| 13 | */ | |
| 14 | #ifndef _ASM_I8259_H | |
| 15 | #define _ASM_I8259_H | |
| 16 | ||
| 17 | #include <linux/compiler.h> | |
| 18 | #include <linux/spinlock.h> | |
| 19 | ||
| 20 | #include <asm/io.h> | |
| 2fa7937b | 21 | #include <irq.h> |
| 1da177e4 | 22 | |
| 2cafe978 AN |
23 | /* i8259A PIC registers */ |
| 24 | #define PIC_MASTER_CMD 0x20 | |
| 25 | #define PIC_MASTER_IMR 0x21 | |
| 26 | #define PIC_MASTER_ISR PIC_MASTER_CMD | |
| 27 | #define PIC_MASTER_POLL PIC_MASTER_ISR | |
| 28 | #define PIC_MASTER_OCW3 PIC_MASTER_ISR | |
| 29 | #define PIC_SLAVE_CMD 0xa0 | |
| 30 | #define PIC_SLAVE_IMR 0xa1 | |
| 31 | ||
| 32 | /* i8259A PIC related value */ | |
| 33 | #define PIC_CASCADE_IR 2 | |
| 34 | #define MASTER_ICW4_DEFAULT 0x01 | |
| 35 | #define SLAVE_ICW4_DEFAULT 0x01 | |
| 36 | #define PIC_ICW4_AEOI 2 | |
| 37 | ||
| 89650870 | 38 | extern raw_spinlock_t i8259A_lock; |
| 1da177e4 | 39 | |
| d80c1c0b YY |
40 | extern int i8259A_irq_pending(unsigned int irq); |
| 41 | extern void make_8259A_irq(unsigned int irq); | |
| 2cafe978 | 42 | |
| 1da177e4 | 43 | extern void init_i8259_irqs(void); |
| 5f93ef5c | 44 | extern int i8259_of_init(struct device_node *node, struct device_node *parent); |
| 1da177e4 LT |
45 | |
| 46 | /* | |
| 47 | * Do the traditional i8259 interrupt polling thing. This is for the few | |
| 48 | * cases where no better interrupt acknowledge method is available and we | |
| 49 | * absolutely must touch the i8259. | |
| 50 | */ | |
| 51 | static inline int i8259_irq(void) | |
| 52 | { | |
| 53 | int irq; | |
| 54 | ||
| 89650870 | 55 | raw_spin_lock(&i8259A_lock); |
| 1da177e4 LT |
56 | |
| 57 | /* Perform an interrupt acknowledge cycle on controller 1. */ | |
| 2cafe978 AN |
58 | outb(0x0C, PIC_MASTER_CMD); /* prepare for poll */ |
| 59 | irq = inb(PIC_MASTER_CMD) & 7; | |
| 60 | if (irq == PIC_CASCADE_IR) { | |
| 1da177e4 LT |
61 | /* |
| 62 | * Interrupt is cascaded so perform interrupt | |
| 63 | * acknowledge on controller 2. | |
| 64 | */ | |
| 2cafe978 AN |
65 | outb(0x0C, PIC_SLAVE_CMD); /* prepare for poll */ |
| 66 | irq = (inb(PIC_SLAVE_CMD) & 7) + 8; | |
| 1da177e4 LT |
67 | } |
| 68 | ||
| 69 | if (unlikely(irq == 7)) { | |
| 70 | /* | |
| 71 | * This may be a spurious interrupt. | |
| 72 | * | |
| 73 | * Read the interrupt status register (ISR). If the most | |
| 74 | * significant bit is not set then there is no valid | |
| 75 | * interrupt. | |
| 76 | */ | |
| 2cafe978 AN |
77 | outb(0x0B, PIC_MASTER_ISR); /* ISR register */ |
| 78 | if(~inb(PIC_MASTER_ISR) & 0x80) | |
| 1da177e4 LT |
79 | irq = -1; |
| 80 | } | |
| 81 | ||
| 89650870 | 82 | raw_spin_unlock(&i8259A_lock); |
| 1da177e4 | 83 | |
| 2cafe978 | 84 | return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq; |
| 1da177e4 LT |
85 | } |
| 86 | ||
| 87 | #endif /* _ASM_I8259_H */ |