[deliverable/linux.git] / arch / mips / include / asm / mach-ath79 / ar71xx_regs.h

/*
 *  Atheros AR71XX/AR724X/AR913X SoC register definitions
 *
 *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
 *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
 *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 *
 *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 */

#ifndef __ASM_MACH_AR71XX_REGS_H
#define __ASM_MACH_AR71XX_REGS_H

#include <linux/types.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/bitops.h>

#define AR71XX_APB_BASE		0x18000000
#define AR71XX_EHCI_BASE	0x1b000000
#define AR71XX_EHCI_SIZE	0x1000
#define AR71XX_OHCI_BASE	0x1c000000
#define AR71XX_OHCI_SIZE	0x1000
#define AR71XX_SPI_BASE		0x1f000000
#define AR71XX_SPI_SIZE		0x01000000

#define AR71XX_DDR_CTRL_BASE	(AR71XX_APB_BASE + 0x00000000)
#define AR71XX_DDR_CTRL_SIZE	0x100
#define AR71XX_UART_BASE	(AR71XX_APB_BASE + 0x00020000)
#define AR71XX_UART_SIZE	0x100
#define AR71XX_USB_CTRL_BASE	(AR71XX_APB_BASE + 0x00030000)
#define AR71XX_USB_CTRL_SIZE	0x100
#define AR71XX_GPIO_BASE        (AR71XX_APB_BASE + 0x00040000)
#define AR71XX_GPIO_SIZE        0x100
#define AR71XX_PLL_BASE		(AR71XX_APB_BASE + 0x00050000)
#define AR71XX_PLL_SIZE		0x100
#define AR71XX_RESET_BASE	(AR71XX_APB_BASE + 0x00060000)
#define AR71XX_RESET_SIZE	0x100

#define AR7240_USB_CTRL_BASE	(AR71XX_APB_BASE + 0x00030000)
#define AR7240_USB_CTRL_SIZE	0x100
#define AR7240_OHCI_BASE	0x1b000000
#define AR7240_OHCI_SIZE	0x1000

#define AR724X_EHCI_BASE	0x1b000000
#define AR724X_EHCI_SIZE	0x1000

#define AR913X_EHCI_BASE	0x1b000000
#define AR913X_EHCI_SIZE	0x1000
#define AR913X_WMAC_BASE	(AR71XX_APB_BASE + 0x000C0000)
#define AR913X_WMAC_SIZE	0x30000

#define AR933X_UART_BASE	(AR71XX_APB_BASE + 0x00020000)
#define AR933X_UART_SIZE	0x14
#define AR933X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
#define AR933X_WMAC_SIZE	0x20000
#define AR933X_EHCI_BASE	0x1b000000
#define AR933X_EHCI_SIZE	0x1000

#define AR934X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
#define AR934X_WMAC_SIZE	0x20000

/*
 * DDR_CTRL block
 */
#define AR71XX_DDR_REG_PCI_WIN0		0x7c
#define AR71XX_DDR_REG_PCI_WIN1		0x80
#define AR71XX_DDR_REG_PCI_WIN2		0x84
#define AR71XX_DDR_REG_PCI_WIN3		0x88
#define AR71XX_DDR_REG_PCI_WIN4		0x8c
#define AR71XX_DDR_REG_PCI_WIN5		0x90
#define AR71XX_DDR_REG_PCI_WIN6		0x94
#define AR71XX_DDR_REG_PCI_WIN7		0x98
#define AR71XX_DDR_REG_FLUSH_GE0	0x9c
#define AR71XX_DDR_REG_FLUSH_GE1	0xa0
#define AR71XX_DDR_REG_FLUSH_USB	0xa4
#define AR71XX_DDR_REG_FLUSH_PCI	0xa8

#define AR724X_DDR_REG_FLUSH_GE0	0x7c
#define AR724X_DDR_REG_FLUSH_GE1	0x80
#define AR724X_DDR_REG_FLUSH_USB	0x84
#define AR724X_DDR_REG_FLUSH_PCIE	0x88

#define AR913X_DDR_REG_FLUSH_GE0	0x7c
#define AR913X_DDR_REG_FLUSH_GE1	0x80
#define AR913X_DDR_REG_FLUSH_USB	0x84
#define AR913X_DDR_REG_FLUSH_WMAC	0x88

#define AR933X_DDR_REG_FLUSH_GE0	0x7c
#define AR933X_DDR_REG_FLUSH_GE1	0x80
#define AR933X_DDR_REG_FLUSH_USB	0x84
#define AR933X_DDR_REG_FLUSH_WMAC	0x88

#define AR934X_DDR_REG_FLUSH_GE0	0x9c
#define AR934X_DDR_REG_FLUSH_GE1	0xa0
#define AR934X_DDR_REG_FLUSH_USB	0xa4
#define AR934X_DDR_REG_FLUSH_PCIE	0xa8
#define AR934X_DDR_REG_FLUSH_WMAC	0xac

/*
 * PLL block
 */
#define AR71XX_PLL_REG_CPU_CONFIG	0x00
#define AR71XX_PLL_REG_SEC_CONFIG	0x04
#define AR71XX_PLL_REG_ETH0_INT_CLOCK	0x10
#define AR71XX_PLL_REG_ETH1_INT_CLOCK	0x14

#define AR71XX_PLL_DIV_SHIFT		3
#define AR71XX_PLL_DIV_MASK		0x1f
#define AR71XX_CPU_DIV_SHIFT		16
#define AR71XX_CPU_DIV_MASK		0x3
#define AR71XX_DDR_DIV_SHIFT		18
#define AR71XX_DDR_DIV_MASK		0x3
#define AR71XX_AHB_DIV_SHIFT		20
#define AR71XX_AHB_DIV_MASK		0x7

#define AR724X_PLL_REG_CPU_CONFIG	0x00
#define AR724X_PLL_REG_PCIE_CONFIG	0x18

#define AR724X_PLL_DIV_SHIFT		0
#define AR724X_PLL_DIV_MASK		0x3ff
#define AR724X_PLL_REF_DIV_SHIFT	10
#define AR724X_PLL_REF_DIV_MASK		0xf
#define AR724X_AHB_DIV_SHIFT		19
#define AR724X_AHB_DIV_MASK		0x1
#define AR724X_DDR_DIV_SHIFT		22
#define AR724X_DDR_DIV_MASK		0x3

#define AR913X_PLL_REG_CPU_CONFIG	0x00
#define AR913X_PLL_REG_ETH_CONFIG	0x04
#define AR913X_PLL_REG_ETH0_INT_CLOCK	0x14
#define AR913X_PLL_REG_ETH1_INT_CLOCK	0x18

#define AR913X_PLL_DIV_SHIFT		0
#define AR913X_PLL_DIV_MASK		0x3ff
#define AR913X_DDR_DIV_SHIFT		22
#define AR913X_DDR_DIV_MASK		0x3
#define AR913X_AHB_DIV_SHIFT		19
#define AR913X_AHB_DIV_MASK		0x1

#define AR933X_PLL_CPU_CONFIG_REG	0x00
#define AR933X_PLL_CLOCK_CTRL_REG	0x08

#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT	10
#define AR933X_PLL_CPU_CONFIG_NINT_MASK		0x3f
#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT	16
#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT	23
#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK	0x7

#define AR933X_PLL_CLOCK_CTRL_BYPASS		BIT(2)
#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT	5
#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK	0x3
#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT	10
#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK	0x3
#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT	15
#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK	0x7

#define AR934X_PLL_CPU_CONFIG_REG		0x00
#define AR934X_PLL_DDR_CONFIG_REG		0x04
#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG		0x08

#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT	6
#define AR934X_PLL_CPU_CONFIG_NINT_MASK		0x3f
#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT	12
#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT	19
#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK	0x3

#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT	0
#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK	0x3ff
#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT	10
#define AR934X_PLL_DDR_CONFIG_NINT_MASK		0x3f
#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT	16
#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK	0x1f
#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT	23
#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK	0x7

#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS	BIT(2)
#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS	BIT(3)
#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS	BIT(4)
#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT	5
#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK	0x1f
#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT	10
#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK	0x1f
#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT	15
#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK	0x1f
#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL	BIT(20)
#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL	BIT(21)
#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL	BIT(24)

/*
 * USB_CONFIG block
 */
#define AR71XX_USB_CTRL_REG_FLADJ	0x00
#define AR71XX_USB_CTRL_REG_CONFIG	0x04

/*
 * RESET block
 */
#define AR71XX_RESET_REG_TIMER			0x00
#define AR71XX_RESET_REG_TIMER_RELOAD		0x04
#define AR71XX_RESET_REG_WDOG_CTRL		0x08
#define AR71XX_RESET_REG_WDOG			0x0c
#define AR71XX_RESET_REG_MISC_INT_STATUS	0x10
#define AR71XX_RESET_REG_MISC_INT_ENABLE	0x14
#define AR71XX_RESET_REG_PCI_INT_STATUS		0x18
#define AR71XX_RESET_REG_PCI_INT_ENABLE		0x1c
#define AR71XX_RESET_REG_GLOBAL_INT_STATUS	0x20
#define AR71XX_RESET_REG_RESET_MODULE		0x24
#define AR71XX_RESET_REG_PERFC_CTRL		0x2c
#define AR71XX_RESET_REG_PERFC0			0x30
#define AR71XX_RESET_REG_PERFC1			0x34
#define AR71XX_RESET_REG_REV_ID			0x90

#define AR913X_RESET_REG_GLOBAL_INT_STATUS	0x18
#define AR913X_RESET_REG_RESET_MODULE		0x1c
#define AR913X_RESET_REG_PERF_CTRL		0x20
#define AR913X_RESET_REG_PERFC0			0x24
#define AR913X_RESET_REG_PERFC1			0x28

#define AR724X_RESET_REG_RESET_MODULE		0x1c

#define AR933X_RESET_REG_RESET_MODULE		0x1c
#define AR933X_RESET_REG_BOOTSTRAP		0xac

#define AR934X_RESET_REG_RESET_MODULE		0x1c
#define AR934X_RESET_REG_BOOTSTRAP		0xb0
#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS	0xac

#define MISC_INT_ETHSW			BIT(12)
#define MISC_INT_TIMER4			BIT(10)
#define MISC_INT_TIMER3			BIT(9)
#define MISC_INT_TIMER2			BIT(8)
#define MISC_INT_DMA			BIT(7)
#define MISC_INT_OHCI			BIT(6)
#define MISC_INT_PERFC			BIT(5)
#define MISC_INT_WDOG			BIT(4)
#define MISC_INT_UART			BIT(3)
#define MISC_INT_GPIO			BIT(2)
#define MISC_INT_ERROR			BIT(1)
#define MISC_INT_TIMER			BIT(0)

#define AR71XX_RESET_EXTERNAL		BIT(28)
#define AR71XX_RESET_FULL_CHIP		BIT(24)
#define AR71XX_RESET_CPU_NMI		BIT(21)
#define AR71XX_RESET_CPU_COLD		BIT(20)
#define AR71XX_RESET_DMA		BIT(19)
#define AR71XX_RESET_SLIC		BIT(18)
#define AR71XX_RESET_STEREO		BIT(17)
#define AR71XX_RESET_DDR		BIT(16)
#define AR71XX_RESET_GE1_MAC		BIT(13)
#define AR71XX_RESET_GE1_PHY		BIT(12)
#define AR71XX_RESET_USBSUS_OVERRIDE	BIT(10)
#define AR71XX_RESET_GE0_MAC		BIT(9)
#define AR71XX_RESET_GE0_PHY		BIT(8)
#define AR71XX_RESET_USB_OHCI_DLL	BIT(6)
#define AR71XX_RESET_USB_HOST		BIT(5)
#define AR71XX_RESET_USB_PHY		BIT(4)
#define AR71XX_RESET_PCI_BUS		BIT(1)
#define AR71XX_RESET_PCI_CORE		BIT(0)

#define AR7240_RESET_USB_HOST		BIT(5)
#define AR7240_RESET_OHCI_DLL		BIT(3)

#define AR724X_RESET_GE1_MDIO		BIT(23)
#define AR724X_RESET_GE0_MDIO		BIT(22)
#define AR724X_RESET_PCIE_PHY_SERIAL	BIT(10)
#define AR724X_RESET_PCIE_PHY		BIT(7)
#define AR724X_RESET_PCIE		BIT(6)
#define AR724X_RESET_USB_HOST		BIT(5)
#define AR724X_RESET_USB_PHY		BIT(4)
#define AR724X_RESET_USBSUS_OVERRIDE	BIT(3)

#define AR913X_RESET_AMBA2WMAC		BIT(22)
#define AR913X_RESET_USBSUS_OVERRIDE	BIT(10)
#define AR913X_RESET_USB_HOST		BIT(5)
#define AR913X_RESET_USB_PHY		BIT(4)

#define AR933X_RESET_WMAC		BIT(11)
#define AR933X_RESET_USB_HOST		BIT(5)
#define AR933X_RESET_USB_PHY		BIT(4)
#define AR933X_RESET_USBSUS_OVERRIDE	BIT(3)

#define AR933X_BOOTSTRAP_REF_CLK_40	BIT(0)

#define AR934X_BOOTSTRAP_SW_OPTION8	BIT(23)
#define AR934X_BOOTSTRAP_SW_OPTION7	BIT(22)
#define AR934X_BOOTSTRAP_SW_OPTION6	BIT(21)
#define AR934X_BOOTSTRAP_SW_OPTION5	BIT(20)
#define AR934X_BOOTSTRAP_SW_OPTION4	BIT(19)
#define AR934X_BOOTSTRAP_SW_OPTION3	BIT(18)
#define AR934X_BOOTSTRAP_SW_OPTION2	BIT(17)
#define AR934X_BOOTSTRAP_SW_OPTION1	BIT(16)
#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
#define AR934X_BOOTSTRAP_PCIE_RC	BIT(6)
#define AR934X_BOOTSTRAP_EJTAG_MODE	BIT(5)
#define AR934X_BOOTSTRAP_REF_CLK_40	BIT(4)
#define AR934X_BOOTSTRAP_BOOT_FROM_SPI	BIT(2)
#define AR934X_BOOTSTRAP_SDRAM_DISABLED	BIT(1)
#define AR934X_BOOTSTRAP_DDR1		BIT(0)

#define AR934X_PCIE_WMAC_INT_WMAC_MISC		BIT(0)
#define AR934X_PCIE_WMAC_INT_WMAC_TX		BIT(1)
#define AR934X_PCIE_WMAC_INT_WMAC_RXLP		BIT(2)
#define AR934X_PCIE_WMAC_INT_WMAC_RXHP		BIT(3)
#define AR934X_PCIE_WMAC_INT_PCIE_RC		BIT(4)
#define AR934X_PCIE_WMAC_INT_PCIE_RC0		BIT(5)
#define AR934X_PCIE_WMAC_INT_PCIE_RC1		BIT(6)
#define AR934X_PCIE_WMAC_INT_PCIE_RC2		BIT(7)
#define AR934X_PCIE_WMAC_INT_PCIE_RC3		BIT(8)
#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
	(AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
	 AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)

#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
	(AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
	 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
	 AR934X_PCIE_WMAC_INT_PCIE_RC3)

#define REV_ID_MAJOR_MASK		0xfff0
#define REV_ID_MAJOR_AR71XX		0x00a0
#define REV_ID_MAJOR_AR913X		0x00b0
#define REV_ID_MAJOR_AR7240		0x00c0
#define REV_ID_MAJOR_AR7241		0x0100
#define REV_ID_MAJOR_AR7242		0x1100
#define REV_ID_MAJOR_AR9330		0x0110
#define REV_ID_MAJOR_AR9331		0x1110
#define REV_ID_MAJOR_AR9341		0x0120
#define REV_ID_MAJOR_AR9342		0x1120
#define REV_ID_MAJOR_AR9344		0x2120

#define AR71XX_REV_ID_MINOR_MASK	0x3
#define AR71XX_REV_ID_MINOR_AR7130	0x0
#define AR71XX_REV_ID_MINOR_AR7141	0x1
#define AR71XX_REV_ID_MINOR_AR7161	0x2
#define AR71XX_REV_ID_REVISION_MASK	0x3
#define AR71XX_REV_ID_REVISION_SHIFT	2

#define AR913X_REV_ID_MINOR_MASK	0x3
#define AR913X_REV_ID_MINOR_AR9130	0x0
#define AR913X_REV_ID_MINOR_AR9132	0x1
#define AR913X_REV_ID_REVISION_MASK	0x3
#define AR913X_REV_ID_REVISION_SHIFT	2

#define AR933X_REV_ID_REVISION_MASK	0x3

#define AR724X_REV_ID_REVISION_MASK	0x3

#define AR934X_REV_ID_REVISION_MASK     0xf

/*
 * SPI block
 */
#define AR71XX_SPI_REG_FS	0x00	/* Function Select */
#define AR71XX_SPI_REG_CTRL	0x04	/* SPI Control */
#define AR71XX_SPI_REG_IOC	0x08	/* SPI I/O Control */
#define AR71XX_SPI_REG_RDS	0x0c	/* Read Data Shift */

#define AR71XX_SPI_FS_GPIO	BIT(0)	/* Enable GPIO mode */

#define AR71XX_SPI_CTRL_RD	BIT(6)	/* Remap Disable */
#define AR71XX_SPI_CTRL_DIV_MASK 0x3f

#define AR71XX_SPI_IOC_DO	BIT(0)	/* Data Out pin */
#define AR71XX_SPI_IOC_CLK	BIT(8)	/* CLK pin */
#define AR71XX_SPI_IOC_CS(n)	BIT(16 + (n))
#define AR71XX_SPI_IOC_CS0	AR71XX_SPI_IOC_CS(0)
#define AR71XX_SPI_IOC_CS1	AR71XX_SPI_IOC_CS(1)
#define AR71XX_SPI_IOC_CS2	AR71XX_SPI_IOC_CS(2)
#define AR71XX_SPI_IOC_CS_ALL	(AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \
				 AR71XX_SPI_IOC_CS2)

/*
 * GPIO block
 */
#define AR71XX_GPIO_REG_OE		0x00
#define AR71XX_GPIO_REG_IN		0x04
#define AR71XX_GPIO_REG_OUT		0x08
#define AR71XX_GPIO_REG_SET		0x0c
#define AR71XX_GPIO_REG_CLEAR		0x10
#define AR71XX_GPIO_REG_INT_MODE	0x14
#define AR71XX_GPIO_REG_INT_TYPE	0x18
#define AR71XX_GPIO_REG_INT_POLARITY	0x1c
#define AR71XX_GPIO_REG_INT_PENDING	0x20
#define AR71XX_GPIO_REG_INT_ENABLE	0x24
#define AR71XX_GPIO_REG_FUNC		0x28

#define AR71XX_GPIO_COUNT		16
#define AR7240_GPIO_COUNT		18
#define AR7241_GPIO_COUNT		20
#define AR913X_GPIO_COUNT		22
#define AR933X_GPIO_COUNT		30
#define AR934X_GPIO_COUNT		23

#endif /* __ASM_MACH_AR71XX_REGS_H */
Commit	Line	Data
d4a67d9d GJ	1	/*
	2	* Atheros AR71XX/AR724X/AR913X SoC register definitions
	3	*
703327dd	4	* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
d4a67d9d GJ	5	* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
	6	* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
	7	*
703327dd	8	* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
d4a67d9d GJ	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License version 2 as published
	12	* by the Free Software Foundation.
	13	*/
	14
	15	#ifndef __ASM_MACH_AR71XX_REGS_H
	16	#define __ASM_MACH_AR71XX_REGS_H
	17
	18	#include <linux/types.h>
	19	#include <linux/init.h>
	20	#include <linux/io.h>
	21	#include <linux/bitops.h>
	22
	23	#define AR71XX_APB_BASE 0x18000000
7e98aa46 GJ	24	#define AR71XX_EHCI_BASE 0x1b000000
	25	#define AR71XX_EHCI_SIZE 0x1000
	26	#define AR71XX_OHCI_BASE 0x1c000000
	27	#define AR71XX_OHCI_SIZE 0x1000
68a1d316 GJ	28	#define AR71XX_SPI_BASE 0x1f000000
68a1d316 GJ	29	#define AR71XX_SPI_SIZE 0x01000000
d4a67d9d GJ	30
	31	#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
	32	#define AR71XX_DDR_CTRL_SIZE 0x100
	33	#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
	34	#define AR71XX_UART_SIZE 0x100
7e98aa46 GJ	35	#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
7e98aa46 GJ	36	#define AR71XX_USB_CTRL_SIZE 0x100
6eae43c5 GJ	37	#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
6eae43c5 GJ	38	#define AR71XX_GPIO_SIZE 0x100
d4a67d9d GJ	39	#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
	40	#define AR71XX_PLL_SIZE 0x100
	41	#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
	42	#define AR71XX_RESET_SIZE 0x100
	43
7e98aa46 GJ	44	#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
	45	#define AR7240_USB_CTRL_SIZE 0x100
	46	#define AR7240_OHCI_BASE 0x1b000000
	47	#define AR7240_OHCI_SIZE 0x1000
	48
	49	#define AR724X_EHCI_BASE 0x1b000000
	50	#define AR724X_EHCI_SIZE 0x1000
	51
	52	#define AR913X_EHCI_BASE 0x1b000000
	53	#define AR913X_EHCI_SIZE 0x1000
f5b35d0b GJ	54	#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
	55	#define AR913X_WMAC_SIZE 0x30000
	56
0bd3acdf GJ	57	#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
0bd3acdf GJ	58	#define AR933X_UART_SIZE 0x14
34cfcd26 GJ	59	#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
34cfcd26 GJ	60	#define AR933X_WMAC_SIZE 0x20000
c279b775 GJ	61	#define AR933X_EHCI_BASE 0x1b000000
	62	#define AR933X_EHCI_SIZE 0x1000
	63
574d6e70 GJ	64	#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
	65	#define AR934X_WMAC_SIZE 0x20000
	66
d4a67d9d GJ	67	/*
	68	* DDR_CTRL block
	69	*/
	70	#define AR71XX_DDR_REG_PCI_WIN0 0x7c
	71	#define AR71XX_DDR_REG_PCI_WIN1 0x80
	72	#define AR71XX_DDR_REG_PCI_WIN2 0x84
	73	#define AR71XX_DDR_REG_PCI_WIN3 0x88
	74	#define AR71XX_DDR_REG_PCI_WIN4 0x8c
	75	#define AR71XX_DDR_REG_PCI_WIN5 0x90
	76	#define AR71XX_DDR_REG_PCI_WIN6 0x94
	77	#define AR71XX_DDR_REG_PCI_WIN7 0x98
	78	#define AR71XX_DDR_REG_FLUSH_GE0 0x9c
	79	#define AR71XX_DDR_REG_FLUSH_GE1 0xa0
	80	#define AR71XX_DDR_REG_FLUSH_USB 0xa4
	81	#define AR71XX_DDR_REG_FLUSH_PCI 0xa8
	82
	83	#define AR724X_DDR_REG_FLUSH_GE0 0x7c
	84	#define AR724X_DDR_REG_FLUSH_GE1 0x80
	85	#define AR724X_DDR_REG_FLUSH_USB 0x84
	86	#define AR724X_DDR_REG_FLUSH_PCIE 0x88
	87
	88	#define AR913X_DDR_REG_FLUSH_GE0 0x7c
	89	#define AR913X_DDR_REG_FLUSH_GE1 0x80
	90	#define AR913X_DDR_REG_FLUSH_USB 0x84
	91	#define AR913X_DDR_REG_FLUSH_WMAC 0x88
	92
54eed4c7 GJ	93	#define AR933X_DDR_REG_FLUSH_GE0 0x7c
	94	#define AR933X_DDR_REG_FLUSH_GE1 0x80
	95	#define AR933X_DDR_REG_FLUSH_USB 0x84
	96	#define AR933X_DDR_REG_FLUSH_WMAC 0x88
	97
fce5cc6e GJ	98	#define AR934X_DDR_REG_FLUSH_GE0 0x9c
	99	#define AR934X_DDR_REG_FLUSH_GE1 0xa0
	100	#define AR934X_DDR_REG_FLUSH_USB 0xa4
	101	#define AR934X_DDR_REG_FLUSH_PCIE 0xa8
	102	#define AR934X_DDR_REG_FLUSH_WMAC 0xac
	103
d4a67d9d GJ	104	/*
	105	* PLL block
	106	*/
	107	#define AR71XX_PLL_REG_CPU_CONFIG 0x00
	108	#define AR71XX_PLL_REG_SEC_CONFIG 0x04
	109	#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
	110	#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
	111
	112	#define AR71XX_PLL_DIV_SHIFT 3
	113	#define AR71XX_PLL_DIV_MASK 0x1f
	114	#define AR71XX_CPU_DIV_SHIFT 16
	115	#define AR71XX_CPU_DIV_MASK 0x3
	116	#define AR71XX_DDR_DIV_SHIFT 18
	117	#define AR71XX_DDR_DIV_MASK 0x3
	118	#define AR71XX_AHB_DIV_SHIFT 20
	119	#define AR71XX_AHB_DIV_MASK 0x7
	120
	121	#define AR724X_PLL_REG_CPU_CONFIG 0x00
	122	#define AR724X_PLL_REG_PCIE_CONFIG 0x18
	123
	124	#define AR724X_PLL_DIV_SHIFT 0
	125	#define AR724X_PLL_DIV_MASK 0x3ff
	126	#define AR724X_PLL_REF_DIV_SHIFT 10
	127	#define AR724X_PLL_REF_DIV_MASK 0xf
	128	#define AR724X_AHB_DIV_SHIFT 19
	129	#define AR724X_AHB_DIV_MASK 0x1
	130	#define AR724X_DDR_DIV_SHIFT 22
	131	#define AR724X_DDR_DIV_MASK 0x3
	132
	133	#define AR913X_PLL_REG_CPU_CONFIG 0x00
	134	#define AR913X_PLL_REG_ETH_CONFIG 0x04
	135	#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
	136	#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18
	137
	138	#define AR913X_PLL_DIV_SHIFT 0
	139	#define AR913X_PLL_DIV_MASK 0x3ff
	140	#define AR913X_DDR_DIV_SHIFT 22
	141	#define AR913X_DDR_DIV_MASK 0x3
	142	#define AR913X_AHB_DIV_SHIFT 19
	143	#define AR913X_AHB_DIV_MASK 0x1
	144
04225e1d GJ	145	#define AR933X_PLL_CPU_CONFIG_REG 0x00
	146	#define AR933X_PLL_CLOCK_CTRL_REG 0x08
	147
	148	#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
	149	#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
	150	#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
	151	#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
	152	#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
	153	#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
	154
	155	#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
	156	#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
	157	#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
	158	#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10
	159	#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
	160	#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
	161	#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
	162
8889612b GJ	163	#define AR934X_PLL_CPU_CONFIG_REG 0x00
	164	#define AR934X_PLL_DDR_CONFIG_REG 0x04
	165	#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
	166
	167	#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
	168	#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
	169	#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6
	170	#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f
	171	#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
	172	#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
	173	#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
	174	#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
	175
	176	#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
	177	#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
	178	#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10
	179	#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f
	180	#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
	181	#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
	182	#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
	183	#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
	184
	185	#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
	186	#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
	187	#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
	188	#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5
	189	#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
	190	#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10
	191	#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
	192	#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15
	193	#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
	194	#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
	195	#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
	196	#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
	197
7e98aa46 GJ	198	/*
	199	* USB_CONFIG block
	200	*/
	201	#define AR71XX_USB_CTRL_REG_FLADJ 0x00
	202	#define AR71XX_USB_CTRL_REG_CONFIG 0x04
	203
d4a67d9d GJ	204	/*
	205	* RESET block
	206	*/
	207	#define AR71XX_RESET_REG_TIMER 0x00
	208	#define AR71XX_RESET_REG_TIMER_RELOAD 0x04
	209	#define AR71XX_RESET_REG_WDOG_CTRL 0x08
	210	#define AR71XX_RESET_REG_WDOG 0x0c
	211	#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
	212	#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
	213	#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
	214	#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
	215	#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
	216	#define AR71XX_RESET_REG_RESET_MODULE 0x24
	217	#define AR71XX_RESET_REG_PERFC_CTRL 0x2c
	218	#define AR71XX_RESET_REG_PERFC0 0x30
	219	#define AR71XX_RESET_REG_PERFC1 0x34
	220	#define AR71XX_RESET_REG_REV_ID 0x90
	221
	222	#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18
	223	#define AR913X_RESET_REG_RESET_MODULE 0x1c
	224	#define AR913X_RESET_REG_PERF_CTRL 0x20
	225	#define AR913X_RESET_REG_PERFC0 0x24
	226	#define AR913X_RESET_REG_PERFC1 0x28
	227
	228	#define AR724X_RESET_REG_RESET_MODULE 0x1c
	229
7ee15d8a	230	#define AR933X_RESET_REG_RESET_MODULE 0x1c
04225e1d GJ	231	#define AR933X_RESET_REG_BOOTSTRAP 0xac
04225e1d GJ	232
42184768	233	#define AR934X_RESET_REG_RESET_MODULE 0x1c
8889612b	234	#define AR934X_RESET_REG_BOOTSTRAP 0xb0
fce5cc6e	235	#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
8889612b	236
d2b4ac1e GJ	237	#define MISC_INT_ETHSW BIT(12)
	238	#define MISC_INT_TIMER4 BIT(10)
	239	#define MISC_INT_TIMER3 BIT(9)
	240	#define MISC_INT_TIMER2 BIT(8)
d4a67d9d GJ	241	#define MISC_INT_DMA BIT(7)
	242	#define MISC_INT_OHCI BIT(6)
	243	#define MISC_INT_PERFC BIT(5)
	244	#define MISC_INT_WDOG BIT(4)
	245	#define MISC_INT_UART BIT(3)
	246	#define MISC_INT_GPIO BIT(2)
	247	#define MISC_INT_ERROR BIT(1)
	248	#define MISC_INT_TIMER BIT(0)
	249
	250	#define AR71XX_RESET_EXTERNAL BIT(28)
	251	#define AR71XX_RESET_FULL_CHIP BIT(24)
	252	#define AR71XX_RESET_CPU_NMI BIT(21)
	253	#define AR71XX_RESET_CPU_COLD BIT(20)
	254	#define AR71XX_RESET_DMA BIT(19)
	255	#define AR71XX_RESET_SLIC BIT(18)
	256	#define AR71XX_RESET_STEREO BIT(17)
	257	#define AR71XX_RESET_DDR BIT(16)
	258	#define AR71XX_RESET_GE1_MAC BIT(13)
	259	#define AR71XX_RESET_GE1_PHY BIT(12)
	260	#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10)
	261	#define AR71XX_RESET_GE0_MAC BIT(9)
	262	#define AR71XX_RESET_GE0_PHY BIT(8)
	263	#define AR71XX_RESET_USB_OHCI_DLL BIT(6)
	264	#define AR71XX_RESET_USB_HOST BIT(5)
	265	#define AR71XX_RESET_USB_PHY BIT(4)
	266	#define AR71XX_RESET_PCI_BUS BIT(1)
	267	#define AR71XX_RESET_PCI_CORE BIT(0)
	268
7e98aa46 GJ	269	#define AR7240_RESET_USB_HOST BIT(5)
	270	#define AR7240_RESET_OHCI_DLL BIT(3)
	271
d4a67d9d GJ	272	#define AR724X_RESET_GE1_MDIO BIT(23)
	273	#define AR724X_RESET_GE0_MDIO BIT(22)
	274	#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
	275	#define AR724X_RESET_PCIE_PHY BIT(7)
	276	#define AR724X_RESET_PCIE BIT(6)
7e98aa46 GJ	277	#define AR724X_RESET_USB_HOST BIT(5)
	278	#define AR724X_RESET_USB_PHY BIT(4)
	279	#define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
d4a67d9d GJ	280
d4a67d9d GJ	281	#define AR913X_RESET_AMBA2WMAC BIT(22)
7e98aa46 GJ	282	#define AR913X_RESET_USBSUS_OVERRIDE BIT(10)
	283	#define AR913X_RESET_USB_HOST BIT(5)
	284	#define AR913X_RESET_USB_PHY BIT(4)
d4a67d9d	285
34cfcd26	286	#define AR933X_RESET_WMAC BIT(11)
c279b775 GJ	287	#define AR933X_RESET_USB_HOST BIT(5)
	288	#define AR933X_RESET_USB_PHY BIT(4)
	289	#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
	290
04225e1d GJ	291	#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
04225e1d GJ	292
8889612b GJ	293	#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
	294	#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22)
	295	#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21)
	296	#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20)
	297	#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19)
	298	#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18)
	299	#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17)
	300	#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16)
	301	#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
	302	#define AR934X_BOOTSTRAP_PCIE_RC BIT(6)
	303	#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5)
	304	#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4)
	305	#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2)
	306	#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
	307	#define AR934X_BOOTSTRAP_DDR1 BIT(0)
	308
fce5cc6e GJ	309	#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
	310	#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
	311	#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
	312	#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
	313	#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4)
	314	#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
	315	#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
	316	#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
	317	#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
	318	#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
	319	(AR934X_PCIE_WMAC_INT_WMAC_MISC \| AR934X_PCIE_WMAC_INT_WMAC_TX \| \
	320	AR934X_PCIE_WMAC_INT_WMAC_RXLP \| AR934X_PCIE_WMAC_INT_WMAC_RXHP)
	321
	322	#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
	323	(AR934X_PCIE_WMAC_INT_PCIE_RC \| AR934X_PCIE_WMAC_INT_PCIE_RC0 \| \
	324	AR934X_PCIE_WMAC_INT_PCIE_RC1 \| AR934X_PCIE_WMAC_INT_PCIE_RC2 \| \
	325	AR934X_PCIE_WMAC_INT_PCIE_RC3)
	326
d4a67d9d GJ	327	#define REV_ID_MAJOR_MASK 0xfff0
	328	#define REV_ID_MAJOR_AR71XX 0x00a0
	329	#define REV_ID_MAJOR_AR913X 0x00b0
	330	#define REV_ID_MAJOR_AR7240 0x00c0
	331	#define REV_ID_MAJOR_AR7241 0x0100
	332	#define REV_ID_MAJOR_AR7242 0x1100
6d1c8fde GJ	333	#define REV_ID_MAJOR_AR9330 0x0110
6d1c8fde GJ	334	#define REV_ID_MAJOR_AR9331 0x1110
703327dd GJ	335	#define REV_ID_MAJOR_AR9341 0x0120
	336	#define REV_ID_MAJOR_AR9342 0x1120
	337	#define REV_ID_MAJOR_AR9344 0x2120
d4a67d9d GJ	338
	339	#define AR71XX_REV_ID_MINOR_MASK 0x3
	340	#define AR71XX_REV_ID_MINOR_AR7130 0x0
	341	#define AR71XX_REV_ID_MINOR_AR7141 0x1
	342	#define AR71XX_REV_ID_MINOR_AR7161 0x2
	343	#define AR71XX_REV_ID_REVISION_MASK 0x3
	344	#define AR71XX_REV_ID_REVISION_SHIFT 2
	345
	346	#define AR913X_REV_ID_MINOR_MASK 0x3
	347	#define AR913X_REV_ID_MINOR_AR9130 0x0
	348	#define AR913X_REV_ID_MINOR_AR9132 0x1
	349	#define AR913X_REV_ID_REVISION_MASK 0x3
	350	#define AR913X_REV_ID_REVISION_SHIFT 2
	351
6d1c8fde GJ	352	#define AR933X_REV_ID_REVISION_MASK 0x3
6d1c8fde GJ	353
d4a67d9d GJ	354	#define AR724X_REV_ID_REVISION_MASK 0x3
d4a67d9d GJ	355
d8411466 GJ	356	#define AR934X_REV_ID_REVISION_MASK 0xf
d8411466 GJ	357
d4a67d9d GJ	358	/*
	359	* SPI block
	360	*/
	361	#define AR71XX_SPI_REG_FS 0x00 /* Function Select */
	362	#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */
	363	#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */
	364	#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */
	365
	366	#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
	367
	368	#define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */
	369	#define AR71XX_SPI_CTRL_DIV_MASK 0x3f
	370
	371	#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */
	372	#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */
	373	#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n))
	374	#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0)
	375	#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1)
	376	#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2)
	377	#define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 \| AR71XX_SPI_IOC_CS1 \| \
	378	AR71XX_SPI_IOC_CS2)
	379
6eae43c5 GJ	380	/*
	381	* GPIO block
	382	*/
	383	#define AR71XX_GPIO_REG_OE 0x00
	384	#define AR71XX_GPIO_REG_IN 0x04
	385	#define AR71XX_GPIO_REG_OUT 0x08
	386	#define AR71XX_GPIO_REG_SET 0x0c
	387	#define AR71XX_GPIO_REG_CLEAR 0x10
	388	#define AR71XX_GPIO_REG_INT_MODE 0x14
	389	#define AR71XX_GPIO_REG_INT_TYPE 0x18
	390	#define AR71XX_GPIO_REG_INT_POLARITY 0x1c
	391	#define AR71XX_GPIO_REG_INT_PENDING 0x20
	392	#define AR71XX_GPIO_REG_INT_ENABLE 0x24
	393	#define AR71XX_GPIO_REG_FUNC 0x28
	394
	395	#define AR71XX_GPIO_COUNT 16
b4da14ab GJ	396	#define AR7240_GPIO_COUNT 18
b4da14ab GJ	397	#define AR7241_GPIO_COUNT 20
6eae43c5	398	#define AR913X_GPIO_COUNT 22
fdfbcf47	399	#define AR933X_GPIO_COUNT 30
5b5b544e	400	#define AR934X_GPIO_COUNT 23
6eae43c5	401
d4a67d9d	402	#endif /* __ASM_MACH_AR71XX_REGS_H */