Commit | Line | Data |
---|---|---|
d4a67d9d GJ |
1 | /* |
2 | * Atheros AR71XX/AR724X/AR913X SoC register definitions | |
3 | * | |
4 | * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> | |
5 | * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> | |
6 | * | |
7 | * Parts of this file are based on Atheros' 2.6.15 BSP | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License version 2 as published | |
11 | * by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #ifndef __ASM_MACH_AR71XX_REGS_H | |
15 | #define __ASM_MACH_AR71XX_REGS_H | |
16 | ||
17 | #include <linux/types.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/bitops.h> | |
21 | ||
22 | #define AR71XX_APB_BASE 0x18000000 | |
7e98aa46 GJ |
23 | #define AR71XX_EHCI_BASE 0x1b000000 |
24 | #define AR71XX_EHCI_SIZE 0x1000 | |
25 | #define AR71XX_OHCI_BASE 0x1c000000 | |
26 | #define AR71XX_OHCI_SIZE 0x1000 | |
68a1d316 GJ |
27 | #define AR71XX_SPI_BASE 0x1f000000 |
28 | #define AR71XX_SPI_SIZE 0x01000000 | |
d4a67d9d GJ |
29 | |
30 | #define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) | |
31 | #define AR71XX_DDR_CTRL_SIZE 0x100 | |
32 | #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) | |
33 | #define AR71XX_UART_SIZE 0x100 | |
7e98aa46 GJ |
34 | #define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) |
35 | #define AR71XX_USB_CTRL_SIZE 0x100 | |
6eae43c5 GJ |
36 | #define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) |
37 | #define AR71XX_GPIO_SIZE 0x100 | |
d4a67d9d GJ |
38 | #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) |
39 | #define AR71XX_PLL_SIZE 0x100 | |
40 | #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) | |
41 | #define AR71XX_RESET_SIZE 0x100 | |
42 | ||
7e98aa46 GJ |
43 | #define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) |
44 | #define AR7240_USB_CTRL_SIZE 0x100 | |
45 | #define AR7240_OHCI_BASE 0x1b000000 | |
46 | #define AR7240_OHCI_SIZE 0x1000 | |
47 | ||
48 | #define AR724X_EHCI_BASE 0x1b000000 | |
49 | #define AR724X_EHCI_SIZE 0x1000 | |
50 | ||
51 | #define AR913X_EHCI_BASE 0x1b000000 | |
52 | #define AR913X_EHCI_SIZE 0x1000 | |
f5b35d0b GJ |
53 | #define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) |
54 | #define AR913X_WMAC_SIZE 0x30000 | |
55 | ||
0bd3acdf GJ |
56 | #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) |
57 | #define AR933X_UART_SIZE 0x14 | |
34cfcd26 GJ |
58 | #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) |
59 | #define AR933X_WMAC_SIZE 0x20000 | |
c279b775 GJ |
60 | #define AR933X_EHCI_BASE 0x1b000000 |
61 | #define AR933X_EHCI_SIZE 0x1000 | |
62 | ||
d4a67d9d GJ |
63 | /* |
64 | * DDR_CTRL block | |
65 | */ | |
66 | #define AR71XX_DDR_REG_PCI_WIN0 0x7c | |
67 | #define AR71XX_DDR_REG_PCI_WIN1 0x80 | |
68 | #define AR71XX_DDR_REG_PCI_WIN2 0x84 | |
69 | #define AR71XX_DDR_REG_PCI_WIN3 0x88 | |
70 | #define AR71XX_DDR_REG_PCI_WIN4 0x8c | |
71 | #define AR71XX_DDR_REG_PCI_WIN5 0x90 | |
72 | #define AR71XX_DDR_REG_PCI_WIN6 0x94 | |
73 | #define AR71XX_DDR_REG_PCI_WIN7 0x98 | |
74 | #define AR71XX_DDR_REG_FLUSH_GE0 0x9c | |
75 | #define AR71XX_DDR_REG_FLUSH_GE1 0xa0 | |
76 | #define AR71XX_DDR_REG_FLUSH_USB 0xa4 | |
77 | #define AR71XX_DDR_REG_FLUSH_PCI 0xa8 | |
78 | ||
79 | #define AR724X_DDR_REG_FLUSH_GE0 0x7c | |
80 | #define AR724X_DDR_REG_FLUSH_GE1 0x80 | |
81 | #define AR724X_DDR_REG_FLUSH_USB 0x84 | |
82 | #define AR724X_DDR_REG_FLUSH_PCIE 0x88 | |
83 | ||
84 | #define AR913X_DDR_REG_FLUSH_GE0 0x7c | |
85 | #define AR913X_DDR_REG_FLUSH_GE1 0x80 | |
86 | #define AR913X_DDR_REG_FLUSH_USB 0x84 | |
87 | #define AR913X_DDR_REG_FLUSH_WMAC 0x88 | |
88 | ||
54eed4c7 GJ |
89 | #define AR933X_DDR_REG_FLUSH_GE0 0x7c |
90 | #define AR933X_DDR_REG_FLUSH_GE1 0x80 | |
91 | #define AR933X_DDR_REG_FLUSH_USB 0x84 | |
92 | #define AR933X_DDR_REG_FLUSH_WMAC 0x88 | |
93 | ||
d4a67d9d GJ |
94 | /* |
95 | * PLL block | |
96 | */ | |
97 | #define AR71XX_PLL_REG_CPU_CONFIG 0x00 | |
98 | #define AR71XX_PLL_REG_SEC_CONFIG 0x04 | |
99 | #define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 | |
100 | #define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 | |
101 | ||
102 | #define AR71XX_PLL_DIV_SHIFT 3 | |
103 | #define AR71XX_PLL_DIV_MASK 0x1f | |
104 | #define AR71XX_CPU_DIV_SHIFT 16 | |
105 | #define AR71XX_CPU_DIV_MASK 0x3 | |
106 | #define AR71XX_DDR_DIV_SHIFT 18 | |
107 | #define AR71XX_DDR_DIV_MASK 0x3 | |
108 | #define AR71XX_AHB_DIV_SHIFT 20 | |
109 | #define AR71XX_AHB_DIV_MASK 0x7 | |
110 | ||
111 | #define AR724X_PLL_REG_CPU_CONFIG 0x00 | |
112 | #define AR724X_PLL_REG_PCIE_CONFIG 0x18 | |
113 | ||
114 | #define AR724X_PLL_DIV_SHIFT 0 | |
115 | #define AR724X_PLL_DIV_MASK 0x3ff | |
116 | #define AR724X_PLL_REF_DIV_SHIFT 10 | |
117 | #define AR724X_PLL_REF_DIV_MASK 0xf | |
118 | #define AR724X_AHB_DIV_SHIFT 19 | |
119 | #define AR724X_AHB_DIV_MASK 0x1 | |
120 | #define AR724X_DDR_DIV_SHIFT 22 | |
121 | #define AR724X_DDR_DIV_MASK 0x3 | |
122 | ||
123 | #define AR913X_PLL_REG_CPU_CONFIG 0x00 | |
124 | #define AR913X_PLL_REG_ETH_CONFIG 0x04 | |
125 | #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 | |
126 | #define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 | |
127 | ||
128 | #define AR913X_PLL_DIV_SHIFT 0 | |
129 | #define AR913X_PLL_DIV_MASK 0x3ff | |
130 | #define AR913X_DDR_DIV_SHIFT 22 | |
131 | #define AR913X_DDR_DIV_MASK 0x3 | |
132 | #define AR913X_AHB_DIV_SHIFT 19 | |
133 | #define AR913X_AHB_DIV_MASK 0x1 | |
134 | ||
04225e1d GJ |
135 | #define AR933X_PLL_CPU_CONFIG_REG 0x00 |
136 | #define AR933X_PLL_CLOCK_CTRL_REG 0x08 | |
137 | ||
138 | #define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 | |
139 | #define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f | |
140 | #define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 | |
141 | #define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f | |
142 | #define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 | |
143 | #define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 | |
144 | ||
145 | #define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2) | |
146 | #define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5 | |
147 | #define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3 | |
148 | #define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10 | |
149 | #define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3 | |
150 | #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15 | |
151 | #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7 | |
152 | ||
7e98aa46 GJ |
153 | /* |
154 | * USB_CONFIG block | |
155 | */ | |
156 | #define AR71XX_USB_CTRL_REG_FLADJ 0x00 | |
157 | #define AR71XX_USB_CTRL_REG_CONFIG 0x04 | |
158 | ||
d4a67d9d GJ |
159 | /* |
160 | * RESET block | |
161 | */ | |
162 | #define AR71XX_RESET_REG_TIMER 0x00 | |
163 | #define AR71XX_RESET_REG_TIMER_RELOAD 0x04 | |
164 | #define AR71XX_RESET_REG_WDOG_CTRL 0x08 | |
165 | #define AR71XX_RESET_REG_WDOG 0x0c | |
166 | #define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 | |
167 | #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 | |
168 | #define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 | |
169 | #define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c | |
170 | #define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 | |
171 | #define AR71XX_RESET_REG_RESET_MODULE 0x24 | |
172 | #define AR71XX_RESET_REG_PERFC_CTRL 0x2c | |
173 | #define AR71XX_RESET_REG_PERFC0 0x30 | |
174 | #define AR71XX_RESET_REG_PERFC1 0x34 | |
175 | #define AR71XX_RESET_REG_REV_ID 0x90 | |
176 | ||
177 | #define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 | |
178 | #define AR913X_RESET_REG_RESET_MODULE 0x1c | |
179 | #define AR913X_RESET_REG_PERF_CTRL 0x20 | |
180 | #define AR913X_RESET_REG_PERFC0 0x24 | |
181 | #define AR913X_RESET_REG_PERFC1 0x28 | |
182 | ||
183 | #define AR724X_RESET_REG_RESET_MODULE 0x1c | |
184 | ||
7ee15d8a | 185 | #define AR933X_RESET_REG_RESET_MODULE 0x1c |
04225e1d GJ |
186 | #define AR933X_RESET_REG_BOOTSTRAP 0xac |
187 | ||
d2b4ac1e GJ |
188 | #define MISC_INT_ETHSW BIT(12) |
189 | #define MISC_INT_TIMER4 BIT(10) | |
190 | #define MISC_INT_TIMER3 BIT(9) | |
191 | #define MISC_INT_TIMER2 BIT(8) | |
d4a67d9d GJ |
192 | #define MISC_INT_DMA BIT(7) |
193 | #define MISC_INT_OHCI BIT(6) | |
194 | #define MISC_INT_PERFC BIT(5) | |
195 | #define MISC_INT_WDOG BIT(4) | |
196 | #define MISC_INT_UART BIT(3) | |
197 | #define MISC_INT_GPIO BIT(2) | |
198 | #define MISC_INT_ERROR BIT(1) | |
199 | #define MISC_INT_TIMER BIT(0) | |
200 | ||
201 | #define AR71XX_RESET_EXTERNAL BIT(28) | |
202 | #define AR71XX_RESET_FULL_CHIP BIT(24) | |
203 | #define AR71XX_RESET_CPU_NMI BIT(21) | |
204 | #define AR71XX_RESET_CPU_COLD BIT(20) | |
205 | #define AR71XX_RESET_DMA BIT(19) | |
206 | #define AR71XX_RESET_SLIC BIT(18) | |
207 | #define AR71XX_RESET_STEREO BIT(17) | |
208 | #define AR71XX_RESET_DDR BIT(16) | |
209 | #define AR71XX_RESET_GE1_MAC BIT(13) | |
210 | #define AR71XX_RESET_GE1_PHY BIT(12) | |
211 | #define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) | |
212 | #define AR71XX_RESET_GE0_MAC BIT(9) | |
213 | #define AR71XX_RESET_GE0_PHY BIT(8) | |
214 | #define AR71XX_RESET_USB_OHCI_DLL BIT(6) | |
215 | #define AR71XX_RESET_USB_HOST BIT(5) | |
216 | #define AR71XX_RESET_USB_PHY BIT(4) | |
217 | #define AR71XX_RESET_PCI_BUS BIT(1) | |
218 | #define AR71XX_RESET_PCI_CORE BIT(0) | |
219 | ||
7e98aa46 GJ |
220 | #define AR7240_RESET_USB_HOST BIT(5) |
221 | #define AR7240_RESET_OHCI_DLL BIT(3) | |
222 | ||
d4a67d9d GJ |
223 | #define AR724X_RESET_GE1_MDIO BIT(23) |
224 | #define AR724X_RESET_GE0_MDIO BIT(22) | |
225 | #define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) | |
226 | #define AR724X_RESET_PCIE_PHY BIT(7) | |
227 | #define AR724X_RESET_PCIE BIT(6) | |
7e98aa46 GJ |
228 | #define AR724X_RESET_USB_HOST BIT(5) |
229 | #define AR724X_RESET_USB_PHY BIT(4) | |
230 | #define AR724X_RESET_USBSUS_OVERRIDE BIT(3) | |
d4a67d9d GJ |
231 | |
232 | #define AR913X_RESET_AMBA2WMAC BIT(22) | |
7e98aa46 GJ |
233 | #define AR913X_RESET_USBSUS_OVERRIDE BIT(10) |
234 | #define AR913X_RESET_USB_HOST BIT(5) | |
235 | #define AR913X_RESET_USB_PHY BIT(4) | |
d4a67d9d | 236 | |
34cfcd26 | 237 | #define AR933X_RESET_WMAC BIT(11) |
c279b775 GJ |
238 | #define AR933X_RESET_USB_HOST BIT(5) |
239 | #define AR933X_RESET_USB_PHY BIT(4) | |
240 | #define AR933X_RESET_USBSUS_OVERRIDE BIT(3) | |
241 | ||
04225e1d GJ |
242 | #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) |
243 | ||
d4a67d9d GJ |
244 | #define REV_ID_MAJOR_MASK 0xfff0 |
245 | #define REV_ID_MAJOR_AR71XX 0x00a0 | |
246 | #define REV_ID_MAJOR_AR913X 0x00b0 | |
247 | #define REV_ID_MAJOR_AR7240 0x00c0 | |
248 | #define REV_ID_MAJOR_AR7241 0x0100 | |
249 | #define REV_ID_MAJOR_AR7242 0x1100 | |
6d1c8fde GJ |
250 | #define REV_ID_MAJOR_AR9330 0x0110 |
251 | #define REV_ID_MAJOR_AR9331 0x1110 | |
d4a67d9d GJ |
252 | |
253 | #define AR71XX_REV_ID_MINOR_MASK 0x3 | |
254 | #define AR71XX_REV_ID_MINOR_AR7130 0x0 | |
255 | #define AR71XX_REV_ID_MINOR_AR7141 0x1 | |
256 | #define AR71XX_REV_ID_MINOR_AR7161 0x2 | |
257 | #define AR71XX_REV_ID_REVISION_MASK 0x3 | |
258 | #define AR71XX_REV_ID_REVISION_SHIFT 2 | |
259 | ||
260 | #define AR913X_REV_ID_MINOR_MASK 0x3 | |
261 | #define AR913X_REV_ID_MINOR_AR9130 0x0 | |
262 | #define AR913X_REV_ID_MINOR_AR9132 0x1 | |
263 | #define AR913X_REV_ID_REVISION_MASK 0x3 | |
264 | #define AR913X_REV_ID_REVISION_SHIFT 2 | |
265 | ||
6d1c8fde GJ |
266 | #define AR933X_REV_ID_REVISION_MASK 0x3 |
267 | ||
d4a67d9d GJ |
268 | #define AR724X_REV_ID_REVISION_MASK 0x3 |
269 | ||
270 | /* | |
271 | * SPI block | |
272 | */ | |
273 | #define AR71XX_SPI_REG_FS 0x00 /* Function Select */ | |
274 | #define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */ | |
275 | #define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */ | |
276 | #define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */ | |
277 | ||
278 | #define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ | |
279 | ||
280 | #define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */ | |
281 | #define AR71XX_SPI_CTRL_DIV_MASK 0x3f | |
282 | ||
283 | #define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */ | |
284 | #define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */ | |
285 | #define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) | |
286 | #define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) | |
287 | #define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) | |
288 | #define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) | |
289 | #define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \ | |
290 | AR71XX_SPI_IOC_CS2) | |
291 | ||
6eae43c5 GJ |
292 | /* |
293 | * GPIO block | |
294 | */ | |
295 | #define AR71XX_GPIO_REG_OE 0x00 | |
296 | #define AR71XX_GPIO_REG_IN 0x04 | |
297 | #define AR71XX_GPIO_REG_OUT 0x08 | |
298 | #define AR71XX_GPIO_REG_SET 0x0c | |
299 | #define AR71XX_GPIO_REG_CLEAR 0x10 | |
300 | #define AR71XX_GPIO_REG_INT_MODE 0x14 | |
301 | #define AR71XX_GPIO_REG_INT_TYPE 0x18 | |
302 | #define AR71XX_GPIO_REG_INT_POLARITY 0x1c | |
303 | #define AR71XX_GPIO_REG_INT_PENDING 0x20 | |
304 | #define AR71XX_GPIO_REG_INT_ENABLE 0x24 | |
305 | #define AR71XX_GPIO_REG_FUNC 0x28 | |
306 | ||
307 | #define AR71XX_GPIO_COUNT 16 | |
308 | #define AR724X_GPIO_COUNT 18 | |
309 | #define AR913X_GPIO_COUNT 22 | |
fdfbcf47 | 310 | #define AR933X_GPIO_COUNT 30 |
6eae43c5 | 311 | |
d4a67d9d | 312 | #endif /* __ASM_MACH_AR71XX_REGS_H */ |