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1da177e4 LT |
1 | /* |
2 | * | |
3 | * BRIEF MODULE DESCRIPTION | |
4 | * Include file for Alchemy Semiconductor's Au1k CPU. | |
5 | * | |
01675095 SS |
6 | * Copyright 2000-2001, 2006-2008 MontaVista Software Inc. |
7 | * Author: MontaVista Software, Inc. <source@mvista.com> | |
1da177e4 LT |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | * | |
14 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
15 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
16 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
17 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
18 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
19 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
20 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
21 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
22 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
23 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License along | |
26 | * with this program; if not, write to the Free Software Foundation, Inc., | |
27 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
28 | */ | |
29 | ||
30 | /* | |
31 | * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp | |
32 | */ | |
33 | ||
34 | #ifndef _AU1000_H_ | |
35 | #define _AU1000_H_ | |
36 | ||
1da177e4 LT |
37 | |
38 | #ifndef _LANGUAGE_ASSEMBLY | |
39 | ||
40 | #include <linux/delay.h> | |
786d7cdd | 41 | #include <linux/types.h> |
9d360ab4 | 42 | |
ff6814d5 SS |
43 | #include <linux/io.h> |
44 | #include <linux/irq.h> | |
1da177e4 LT |
45 | |
46 | /* cpu pipeline flush */ | |
47 | void static inline au_sync(void) | |
48 | { | |
49 | __asm__ volatile ("sync"); | |
50 | } | |
51 | ||
52 | void static inline au_sync_udelay(int us) | |
53 | { | |
54 | __asm__ volatile ("sync"); | |
55 | udelay(us); | |
56 | } | |
57 | ||
58 | void static inline au_sync_delay(int ms) | |
59 | { | |
60 | __asm__ volatile ("sync"); | |
61 | mdelay(ms); | |
62 | } | |
63 | ||
7de8d232 | 64 | void static inline au_writeb(u8 val, unsigned long reg) |
1da177e4 | 65 | { |
ff6814d5 | 66 | *(volatile u8 *)reg = val; |
1da177e4 LT |
67 | } |
68 | ||
7de8d232 | 69 | void static inline au_writew(u16 val, unsigned long reg) |
1da177e4 | 70 | { |
ff6814d5 | 71 | *(volatile u16 *)reg = val; |
1da177e4 LT |
72 | } |
73 | ||
7de8d232 | 74 | void static inline au_writel(u32 val, unsigned long reg) |
1da177e4 | 75 | { |
ff6814d5 | 76 | *(volatile u32 *)reg = val; |
1da177e4 LT |
77 | } |
78 | ||
7de8d232 | 79 | static inline u8 au_readb(unsigned long reg) |
1da177e4 | 80 | { |
ff6814d5 | 81 | return *(volatile u8 *)reg; |
1da177e4 LT |
82 | } |
83 | ||
7de8d232 | 84 | static inline u16 au_readw(unsigned long reg) |
1da177e4 | 85 | { |
ff6814d5 | 86 | return *(volatile u16 *)reg; |
1da177e4 LT |
87 | } |
88 | ||
7de8d232 | 89 | static inline u32 au_readl(unsigned long reg) |
1da177e4 | 90 | { |
ff6814d5 | 91 | return *(volatile u32 *)reg; |
1da177e4 LT |
92 | } |
93 | ||
074cf656 ML |
94 | /* Early Au1000 have a write-only SYS_CPUPLL register. */ |
95 | static inline int au1xxx_cpu_has_pll_wo(void) | |
96 | { | |
97 | switch (read_c0_prid()) { | |
98 | case 0x00030100: /* Au1000 DA */ | |
99 | case 0x00030201: /* Au1000 HA */ | |
100 | case 0x00030202: /* Au1000 HB */ | |
101 | return 1; | |
102 | } | |
103 | return 0; | |
104 | } | |
105 | ||
106 | /* does CPU need CONFIG[OD] set to fix tons of errata? */ | |
107 | static inline int au1xxx_cpu_needs_config_od(void) | |
108 | { | |
109 | /* | |
110 | * c0_config.od (bit 19) was write only (and read as 0) on the | |
111 | * early revisions of Alchemy SOCs. It disables the bus trans- | |
112 | * action overlapping and needs to be set to fix various errata. | |
113 | */ | |
114 | switch (read_c0_prid()) { | |
115 | case 0x00030100: /* Au1000 DA */ | |
116 | case 0x00030201: /* Au1000 HA */ | |
117 | case 0x00030202: /* Au1000 HB */ | |
118 | case 0x01030200: /* Au1500 AB */ | |
119 | /* | |
120 | * Au1100/Au1200 errata actually keep silence about this bit, | |
121 | * so we set it just in case for those revisions that require | |
122 | * it to be set according to the (now gone) cpu_table. | |
123 | */ | |
124 | case 0x02030200: /* Au1100 AB */ | |
125 | case 0x02030201: /* Au1100 BA */ | |
126 | case 0x02030202: /* Au1100 BC */ | |
127 | case 0x04030201: /* Au1200 AC */ | |
128 | return 1; | |
129 | } | |
130 | return 0; | |
131 | } | |
1da177e4 | 132 | |
1da177e4 LT |
133 | /* arch/mips/au1000/common/clocks.c */ |
134 | extern void set_au1x00_speed(unsigned int new_freq); | |
135 | extern unsigned int get_au1x00_speed(void); | |
136 | extern void set_au1x00_uart_baud_base(unsigned long new_baud_base); | |
137 | extern unsigned long get_au1x00_uart_baud_base(void); | |
2699cdfb | 138 | extern unsigned long au1xxx_calc_clock(void); |
1da177e4 | 139 | |
564365b0 ML |
140 | /* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */ |
141 | void au1xxx_save_and_sleep(void); | |
142 | void au_sleep(void); | |
143 | void save_au1xxx_intctl(void); | |
144 | void restore_au1xxx_intctl(void); | |
145 | ||
1da177e4 LT |
146 | /* |
147 | * Every board describes its IRQ mapping with this table. | |
148 | */ | |
0e6799ed | 149 | struct au1xxx_irqmap { |
1da177e4 LT |
150 | int im_irq; |
151 | int im_type; | |
152 | int im_request; | |
0e6799ed | 153 | }; |
1da177e4 | 154 | |
785e3268 ML |
155 | /* core calls this function to let boards initialize other IRQ sources */ |
156 | void board_init_irq(void); | |
157 | ||
158 | /* boards call this to register additional (GPIO) interrupts */ | |
159 | void au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count); | |
1da177e4 LT |
160 | |
161 | #endif /* !defined (_LANGUAGE_ASSEMBLY) */ | |
162 | ||
e3ad1c23 | 163 | /* |
ff6814d5 | 164 | * SDRAM register offsets |
e3ad1c23 | 165 | */ |
ff6814d5 SS |
166 | #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \ |
167 | defined(CONFIG_SOC_AU1100) | |
168 | #define MEM_SDMODE0 0x0000 | |
169 | #define MEM_SDMODE1 0x0004 | |
170 | #define MEM_SDMODE2 0x0008 | |
171 | #define MEM_SDADDR0 0x000C | |
172 | #define MEM_SDADDR1 0x0010 | |
173 | #define MEM_SDADDR2 0x0014 | |
174 | #define MEM_SDREFCFG 0x0018 | |
175 | #define MEM_SDPRECMD 0x001C | |
176 | #define MEM_SDAUTOREF 0x0020 | |
177 | #define MEM_SDWRMD0 0x0024 | |
178 | #define MEM_SDWRMD1 0x0028 | |
179 | #define MEM_SDWRMD2 0x002C | |
180 | #define MEM_SDSLEEP 0x0030 | |
181 | #define MEM_SDSMCKE 0x0034 | |
e3ad1c23 | 182 | |
e3ad1c23 PP |
183 | /* |
184 | * MEM_SDMODE register content definitions | |
185 | */ | |
ff6814d5 SS |
186 | #define MEM_SDMODE_F (1 << 22) |
187 | #define MEM_SDMODE_SR (1 << 21) | |
188 | #define MEM_SDMODE_BS (1 << 20) | |
189 | #define MEM_SDMODE_RS (3 << 18) | |
190 | #define MEM_SDMODE_CS (7 << 15) | |
191 | #define MEM_SDMODE_TRAS (15 << 11) | |
192 | #define MEM_SDMODE_TMRD (3 << 9) | |
193 | #define MEM_SDMODE_TWR (3 << 7) | |
194 | #define MEM_SDMODE_TRP (3 << 5) | |
195 | #define MEM_SDMODE_TRCD (3 << 3) | |
196 | #define MEM_SDMODE_TCL (7 << 0) | |
197 | ||
198 | #define MEM_SDMODE_BS_2Bank (0 << 20) | |
199 | #define MEM_SDMODE_BS_4Bank (1 << 20) | |
200 | #define MEM_SDMODE_RS_11Row (0 << 18) | |
201 | #define MEM_SDMODE_RS_12Row (1 << 18) | |
202 | #define MEM_SDMODE_RS_13Row (2 << 18) | |
203 | #define MEM_SDMODE_RS_N(N) ((N) << 18) | |
204 | #define MEM_SDMODE_CS_7Col (0 << 15) | |
205 | #define MEM_SDMODE_CS_8Col (1 << 15) | |
206 | #define MEM_SDMODE_CS_9Col (2 << 15) | |
207 | #define MEM_SDMODE_CS_10Col (3 << 15) | |
208 | #define MEM_SDMODE_CS_11Col (4 << 15) | |
209 | #define MEM_SDMODE_CS_N(N) ((N) << 15) | |
210 | #define MEM_SDMODE_TRAS_N(N) ((N) << 11) | |
211 | #define MEM_SDMODE_TMRD_N(N) ((N) << 9) | |
212 | #define MEM_SDMODE_TWR_N(N) ((N) << 7) | |
213 | #define MEM_SDMODE_TRP_N(N) ((N) << 5) | |
214 | #define MEM_SDMODE_TRCD_N(N) ((N) << 3) | |
215 | #define MEM_SDMODE_TCL_N(N) ((N) << 0) | |
e3ad1c23 PP |
216 | |
217 | /* | |
218 | * MEM_SDADDR register contents definitions | |
219 | */ | |
ff6814d5 SS |
220 | #define MEM_SDADDR_E (1 << 20) |
221 | #define MEM_SDADDR_CSBA (0x03FF << 10) | |
222 | #define MEM_SDADDR_CSMASK (0x03FF << 0) | |
223 | #define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12) | |
224 | #define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22) | |
e3ad1c23 PP |
225 | |
226 | /* | |
227 | * MEM_SDREFCFG register content definitions | |
228 | */ | |
ff6814d5 SS |
229 | #define MEM_SDREFCFG_TRC (15 << 28) |
230 | #define MEM_SDREFCFG_TRPM (3 << 26) | |
231 | #define MEM_SDREFCFG_E (1 << 25) | |
232 | #define MEM_SDREFCFG_RE (0x1ffffff << 0) | |
233 | #define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC) | |
234 | #define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM) | |
e3ad1c23 PP |
235 | #define MEM_SDREFCFG_REF_N(N) (N) |
236 | #endif | |
1da177e4 | 237 | |
e3ad1c23 | 238 | /***********************************************************************/ |
1da177e4 | 239 | |
e3ad1c23 PP |
240 | /* |
241 | * Au1550 SDRAM Register Offsets | |
242 | */ | |
1da177e4 | 243 | |
e3ad1c23 | 244 | /***********************************************************************/ |
1da177e4 | 245 | |
e3ad1c23 | 246 | #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) |
ff6814d5 SS |
247 | #define MEM_SDMODE0 0x0800 |
248 | #define MEM_SDMODE1 0x0808 | |
249 | #define MEM_SDMODE2 0x0810 | |
250 | #define MEM_SDADDR0 0x0820 | |
251 | #define MEM_SDADDR1 0x0828 | |
252 | #define MEM_SDADDR2 0x0830 | |
253 | #define MEM_SDCONFIGA 0x0840 | |
254 | #define MEM_SDCONFIGB 0x0848 | |
255 | #define MEM_SDSTAT 0x0850 | |
256 | #define MEM_SDERRADDR 0x0858 | |
257 | #define MEM_SDSTRIDE0 0x0860 | |
258 | #define MEM_SDSTRIDE1 0x0868 | |
259 | #define MEM_SDSTRIDE2 0x0870 | |
260 | #define MEM_SDWRMD0 0x0880 | |
261 | #define MEM_SDWRMD1 0x0888 | |
262 | #define MEM_SDWRMD2 0x0890 | |
263 | #define MEM_SDPRECMD 0x08C0 | |
264 | #define MEM_SDAUTOREF 0x08C8 | |
265 | #define MEM_SDSREF 0x08D0 | |
e3ad1c23 PP |
266 | #define MEM_SDSLEEP MEM_SDSREF |
267 | ||
e3ad1c23 PP |
268 | #endif |
269 | ||
270 | /* | |
271 | * Physical base addresses for integrated peripherals | |
272 | */ | |
273 | ||
274 | #ifdef CONFIG_SOC_AU1000 | |
275 | #define MEM_PHYS_ADDR 0x14000000 | |
276 | #define STATIC_MEM_PHYS_ADDR 0x14001000 | |
277 | #define DMA0_PHYS_ADDR 0x14002000 | |
278 | #define DMA1_PHYS_ADDR 0x14002100 | |
279 | #define DMA2_PHYS_ADDR 0x14002200 | |
280 | #define DMA3_PHYS_ADDR 0x14002300 | |
281 | #define DMA4_PHYS_ADDR 0x14002400 | |
282 | #define DMA5_PHYS_ADDR 0x14002500 | |
283 | #define DMA6_PHYS_ADDR 0x14002600 | |
284 | #define DMA7_PHYS_ADDR 0x14002700 | |
285 | #define IC0_PHYS_ADDR 0x10400000 | |
286 | #define IC1_PHYS_ADDR 0x11800000 | |
287 | #define AC97_PHYS_ADDR 0x10000000 | |
288 | #define USBH_PHYS_ADDR 0x10100000 | |
289 | #define USBD_PHYS_ADDR 0x10200000 | |
290 | #define IRDA_PHYS_ADDR 0x10300000 | |
291 | #define MAC0_PHYS_ADDR 0x10500000 | |
292 | #define MAC1_PHYS_ADDR 0x10510000 | |
293 | #define MACEN_PHYS_ADDR 0x10520000 | |
294 | #define MACDMA0_PHYS_ADDR 0x14004000 | |
295 | #define MACDMA1_PHYS_ADDR 0x14004200 | |
296 | #define I2S_PHYS_ADDR 0x11000000 | |
297 | #define UART0_PHYS_ADDR 0x11100000 | |
298 | #define UART1_PHYS_ADDR 0x11200000 | |
299 | #define UART2_PHYS_ADDR 0x11300000 | |
300 | #define UART3_PHYS_ADDR 0x11400000 | |
301 | #define SSI0_PHYS_ADDR 0x11600000 | |
302 | #define SSI1_PHYS_ADDR 0x11680000 | |
303 | #define SYS_PHYS_ADDR 0x11900000 | |
ff6814d5 SS |
304 | #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL |
305 | #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL | |
306 | #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL | |
e3ad1c23 PP |
307 | #endif |
308 | ||
309 | /********************************************************************/ | |
310 | ||
311 | #ifdef CONFIG_SOC_AU1500 | |
312 | #define MEM_PHYS_ADDR 0x14000000 | |
313 | #define STATIC_MEM_PHYS_ADDR 0x14001000 | |
314 | #define DMA0_PHYS_ADDR 0x14002000 | |
315 | #define DMA1_PHYS_ADDR 0x14002100 | |
316 | #define DMA2_PHYS_ADDR 0x14002200 | |
317 | #define DMA3_PHYS_ADDR 0x14002300 | |
318 | #define DMA4_PHYS_ADDR 0x14002400 | |
319 | #define DMA5_PHYS_ADDR 0x14002500 | |
320 | #define DMA6_PHYS_ADDR 0x14002600 | |
321 | #define DMA7_PHYS_ADDR 0x14002700 | |
322 | #define IC0_PHYS_ADDR 0x10400000 | |
323 | #define IC1_PHYS_ADDR 0x11800000 | |
324 | #define AC97_PHYS_ADDR 0x10000000 | |
325 | #define USBH_PHYS_ADDR 0x10100000 | |
326 | #define USBD_PHYS_ADDR 0x10200000 | |
327 | #define PCI_PHYS_ADDR 0x14005000 | |
328 | #define MAC0_PHYS_ADDR 0x11500000 | |
329 | #define MAC1_PHYS_ADDR 0x11510000 | |
330 | #define MACEN_PHYS_ADDR 0x11520000 | |
331 | #define MACDMA0_PHYS_ADDR 0x14004000 | |
332 | #define MACDMA1_PHYS_ADDR 0x14004200 | |
333 | #define I2S_PHYS_ADDR 0x11000000 | |
334 | #define UART0_PHYS_ADDR 0x11100000 | |
335 | #define UART3_PHYS_ADDR 0x11400000 | |
336 | #define GPIO2_PHYS_ADDR 0x11700000 | |
337 | #define SYS_PHYS_ADDR 0x11900000 | |
ff6814d5 SS |
338 | #define PCI_MEM_PHYS_ADDR 0x400000000ULL |
339 | #define PCI_IO_PHYS_ADDR 0x500000000ULL | |
340 | #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL | |
341 | #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL | |
342 | #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL | |
343 | #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL | |
344 | #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL | |
e3ad1c23 PP |
345 | #endif |
346 | ||
347 | /********************************************************************/ | |
348 | ||
349 | #ifdef CONFIG_SOC_AU1100 | |
350 | #define MEM_PHYS_ADDR 0x14000000 | |
351 | #define STATIC_MEM_PHYS_ADDR 0x14001000 | |
352 | #define DMA0_PHYS_ADDR 0x14002000 | |
353 | #define DMA1_PHYS_ADDR 0x14002100 | |
354 | #define DMA2_PHYS_ADDR 0x14002200 | |
355 | #define DMA3_PHYS_ADDR 0x14002300 | |
356 | #define DMA4_PHYS_ADDR 0x14002400 | |
357 | #define DMA5_PHYS_ADDR 0x14002500 | |
358 | #define DMA6_PHYS_ADDR 0x14002600 | |
359 | #define DMA7_PHYS_ADDR 0x14002700 | |
360 | #define IC0_PHYS_ADDR 0x10400000 | |
361 | #define SD0_PHYS_ADDR 0x10600000 | |
362 | #define SD1_PHYS_ADDR 0x10680000 | |
363 | #define IC1_PHYS_ADDR 0x11800000 | |
364 | #define AC97_PHYS_ADDR 0x10000000 | |
365 | #define USBH_PHYS_ADDR 0x10100000 | |
366 | #define USBD_PHYS_ADDR 0x10200000 | |
367 | #define IRDA_PHYS_ADDR 0x10300000 | |
368 | #define MAC0_PHYS_ADDR 0x10500000 | |
369 | #define MACEN_PHYS_ADDR 0x10520000 | |
370 | #define MACDMA0_PHYS_ADDR 0x14004000 | |
371 | #define MACDMA1_PHYS_ADDR 0x14004200 | |
372 | #define I2S_PHYS_ADDR 0x11000000 | |
373 | #define UART0_PHYS_ADDR 0x11100000 | |
374 | #define UART1_PHYS_ADDR 0x11200000 | |
375 | #define UART3_PHYS_ADDR 0x11400000 | |
376 | #define SSI0_PHYS_ADDR 0x11600000 | |
377 | #define SSI1_PHYS_ADDR 0x11680000 | |
378 | #define GPIO2_PHYS_ADDR 0x11700000 | |
379 | #define SYS_PHYS_ADDR 0x11900000 | |
380 | #define LCD_PHYS_ADDR 0x15000000 | |
ff6814d5 SS |
381 | #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL |
382 | #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL | |
383 | #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL | |
e3ad1c23 PP |
384 | #endif |
385 | ||
386 | /***********************************************************************/ | |
387 | ||
388 | #ifdef CONFIG_SOC_AU1550 | |
389 | #define MEM_PHYS_ADDR 0x14000000 | |
390 | #define STATIC_MEM_PHYS_ADDR 0x14001000 | |
391 | #define IC0_PHYS_ADDR 0x10400000 | |
392 | #define IC1_PHYS_ADDR 0x11800000 | |
393 | #define USBH_PHYS_ADDR 0x14020000 | |
394 | #define USBD_PHYS_ADDR 0x10200000 | |
395 | #define PCI_PHYS_ADDR 0x14005000 | |
396 | #define MAC0_PHYS_ADDR 0x10500000 | |
397 | #define MAC1_PHYS_ADDR 0x10510000 | |
398 | #define MACEN_PHYS_ADDR 0x10520000 | |
399 | #define MACDMA0_PHYS_ADDR 0x14004000 | |
400 | #define MACDMA1_PHYS_ADDR 0x14004200 | |
401 | #define UART0_PHYS_ADDR 0x11100000 | |
402 | #define UART1_PHYS_ADDR 0x11200000 | |
403 | #define UART3_PHYS_ADDR 0x11400000 | |
404 | #define GPIO2_PHYS_ADDR 0x11700000 | |
405 | #define SYS_PHYS_ADDR 0x11900000 | |
406 | #define DDMA_PHYS_ADDR 0x14002000 | |
407 | #define PE_PHYS_ADDR 0x14008000 | |
ff6814d5 SS |
408 | #define PSC0_PHYS_ADDR 0x11A00000 |
409 | #define PSC1_PHYS_ADDR 0x11B00000 | |
410 | #define PSC2_PHYS_ADDR 0x10A00000 | |
411 | #define PSC3_PHYS_ADDR 0x10B00000 | |
412 | #define PCI_MEM_PHYS_ADDR 0x400000000ULL | |
413 | #define PCI_IO_PHYS_ADDR 0x500000000ULL | |
414 | #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL | |
415 | #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL | |
416 | #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL | |
417 | #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL | |
418 | #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL | |
e3ad1c23 PP |
419 | #endif |
420 | ||
421 | /***********************************************************************/ | |
422 | ||
423 | #ifdef CONFIG_SOC_AU1200 | |
424 | #define MEM_PHYS_ADDR 0x14000000 | |
425 | #define STATIC_MEM_PHYS_ADDR 0x14001000 | |
426 | #define AES_PHYS_ADDR 0x10300000 | |
427 | #define CIM_PHYS_ADDR 0x14004000 | |
428 | #define IC0_PHYS_ADDR 0x10400000 | |
429 | #define IC1_PHYS_ADDR 0x11800000 | |
430 | #define USBM_PHYS_ADDR 0x14020000 | |
431 | #define USBH_PHYS_ADDR 0x14020100 | |
432 | #define UART0_PHYS_ADDR 0x11100000 | |
433 | #define UART1_PHYS_ADDR 0x11200000 | |
434 | #define GPIO2_PHYS_ADDR 0x11700000 | |
435 | #define SYS_PHYS_ADDR 0x11900000 | |
436 | #define DDMA_PHYS_ADDR 0x14002000 | |
437 | #define PSC0_PHYS_ADDR 0x11A00000 | |
438 | #define PSC1_PHYS_ADDR 0x11B00000 | |
e3ad1c23 PP |
439 | #define SD0_PHYS_ADDR 0x10600000 |
440 | #define SD1_PHYS_ADDR 0x10680000 | |
441 | #define LCD_PHYS_ADDR 0x15000000 | |
442 | #define SWCNT_PHYS_ADDR 0x1110010C | |
443 | #define MAEFE_PHYS_ADDR 0x14012000 | |
444 | #define MAEBE_PHYS_ADDR 0x14010000 | |
ff6814d5 SS |
445 | #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL |
446 | #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL | |
447 | #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL | |
e3ad1c23 PP |
448 | #endif |
449 | ||
1da177e4 | 450 | /* Static Bus Controller */ |
ff6814d5 SS |
451 | #define MEM_STCFG0 0xB4001000 |
452 | #define MEM_STTIME0 0xB4001004 | |
453 | #define MEM_STADDR0 0xB4001008 | |
1da177e4 | 454 | |
ff6814d5 SS |
455 | #define MEM_STCFG1 0xB4001010 |
456 | #define MEM_STTIME1 0xB4001014 | |
457 | #define MEM_STADDR1 0xB4001018 | |
1da177e4 | 458 | |
ff6814d5 SS |
459 | #define MEM_STCFG2 0xB4001020 |
460 | #define MEM_STTIME2 0xB4001024 | |
461 | #define MEM_STADDR2 0xB4001028 | |
1da177e4 | 462 | |
ff6814d5 SS |
463 | #define MEM_STCFG3 0xB4001030 |
464 | #define MEM_STTIME3 0xB4001034 | |
465 | #define MEM_STADDR3 0xB4001038 | |
1da177e4 LT |
466 | |
467 | #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) | |
ff6814d5 SS |
468 | #define MEM_STNDCTL 0xB4001100 |
469 | #define MEM_STSTAT 0xB4001104 | |
1da177e4 | 470 | |
ff6814d5 SS |
471 | #define MEM_STNAND_CMD 0x0 |
472 | #define MEM_STNAND_ADDR 0x4 | |
473 | #define MEM_STNAND_DATA 0x20 | |
1da177e4 LT |
474 | #endif |
475 | ||
476 | /* Interrupt Controller 0 */ | |
ff6814d5 SS |
477 | #define IC0_CFG0RD 0xB0400040 |
478 | #define IC0_CFG0SET 0xB0400040 | |
479 | #define IC0_CFG0CLR 0xB0400044 | |
1da177e4 | 480 | |
ff6814d5 SS |
481 | #define IC0_CFG1RD 0xB0400048 |
482 | #define IC0_CFG1SET 0xB0400048 | |
483 | #define IC0_CFG1CLR 0xB040004C | |
1da177e4 | 484 | |
ff6814d5 SS |
485 | #define IC0_CFG2RD 0xB0400050 |
486 | #define IC0_CFG2SET 0xB0400050 | |
487 | #define IC0_CFG2CLR 0xB0400054 | |
1da177e4 | 488 | |
ff6814d5 SS |
489 | #define IC0_REQ0INT 0xB0400054 |
490 | #define IC0_SRCRD 0xB0400058 | |
491 | #define IC0_SRCSET 0xB0400058 | |
492 | #define IC0_SRCCLR 0xB040005C | |
493 | #define IC0_REQ1INT 0xB040005C | |
1da177e4 | 494 | |
ff6814d5 SS |
495 | #define IC0_ASSIGNRD 0xB0400060 |
496 | #define IC0_ASSIGNSET 0xB0400060 | |
497 | #define IC0_ASSIGNCLR 0xB0400064 | |
1da177e4 | 498 | |
ff6814d5 SS |
499 | #define IC0_WAKERD 0xB0400068 |
500 | #define IC0_WAKESET 0xB0400068 | |
501 | #define IC0_WAKECLR 0xB040006C | |
1da177e4 | 502 | |
ff6814d5 SS |
503 | #define IC0_MASKRD 0xB0400070 |
504 | #define IC0_MASKSET 0xB0400070 | |
505 | #define IC0_MASKCLR 0xB0400074 | |
1da177e4 | 506 | |
ff6814d5 SS |
507 | #define IC0_RISINGRD 0xB0400078 |
508 | #define IC0_RISINGCLR 0xB0400078 | |
509 | #define IC0_FALLINGRD 0xB040007C | |
510 | #define IC0_FALLINGCLR 0xB040007C | |
1da177e4 | 511 | |
ff6814d5 | 512 | #define IC0_TESTBIT 0xB0400080 |
1da177e4 LT |
513 | |
514 | /* Interrupt Controller 1 */ | |
ff6814d5 SS |
515 | #define IC1_CFG0RD 0xB1800040 |
516 | #define IC1_CFG0SET 0xB1800040 | |
517 | #define IC1_CFG0CLR 0xB1800044 | |
1da177e4 | 518 | |
ff6814d5 SS |
519 | #define IC1_CFG1RD 0xB1800048 |
520 | #define IC1_CFG1SET 0xB1800048 | |
521 | #define IC1_CFG1CLR 0xB180004C | |
1da177e4 | 522 | |
ff6814d5 SS |
523 | #define IC1_CFG2RD 0xB1800050 |
524 | #define IC1_CFG2SET 0xB1800050 | |
525 | #define IC1_CFG2CLR 0xB1800054 | |
1da177e4 | 526 | |
ff6814d5 SS |
527 | #define IC1_REQ0INT 0xB1800054 |
528 | #define IC1_SRCRD 0xB1800058 | |
529 | #define IC1_SRCSET 0xB1800058 | |
530 | #define IC1_SRCCLR 0xB180005C | |
531 | #define IC1_REQ1INT 0xB180005C | |
1da177e4 | 532 | |
ff6814d5 SS |
533 | #define IC1_ASSIGNRD 0xB1800060 |
534 | #define IC1_ASSIGNSET 0xB1800060 | |
535 | #define IC1_ASSIGNCLR 0xB1800064 | |
1da177e4 | 536 | |
ff6814d5 SS |
537 | #define IC1_WAKERD 0xB1800068 |
538 | #define IC1_WAKESET 0xB1800068 | |
539 | #define IC1_WAKECLR 0xB180006C | |
1da177e4 | 540 | |
ff6814d5 SS |
541 | #define IC1_MASKRD 0xB1800070 |
542 | #define IC1_MASKSET 0xB1800070 | |
543 | #define IC1_MASKCLR 0xB1800074 | |
1da177e4 | 544 | |
ff6814d5 SS |
545 | #define IC1_RISINGRD 0xB1800078 |
546 | #define IC1_RISINGCLR 0xB1800078 | |
547 | #define IC1_FALLINGRD 0xB180007C | |
548 | #define IC1_FALLINGCLR 0xB180007C | |
1da177e4 | 549 | |
ff6814d5 | 550 | #define IC1_TESTBIT 0xB1800080 |
1da177e4 | 551 | |
1da177e4 LT |
552 | /* Interrupt Numbers */ |
553 | /* Au1000 */ | |
554 | #ifdef CONFIG_SOC_AU1000 | |
9d360ab4 | 555 | enum soc_au1000_ints { |
0e8120e0 | 556 | AU1000_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, |
9d360ab4 RB |
557 | AU1000_UART0_INT = AU1000_FIRST_INT, |
558 | AU1000_UART1_INT, /* au1000 */ | |
559 | AU1000_UART2_INT, /* au1000 */ | |
560 | AU1000_UART3_INT, | |
561 | AU1000_SSI0_INT, /* au1000 */ | |
562 | AU1000_SSI1_INT, /* au1000 */ | |
563 | AU1000_DMA_INT_BASE, | |
564 | ||
565 | AU1000_TOY_INT = AU1000_FIRST_INT + 14, | |
566 | AU1000_TOY_MATCH0_INT, | |
567 | AU1000_TOY_MATCH1_INT, | |
568 | AU1000_TOY_MATCH2_INT, | |
569 | AU1000_RTC_INT, | |
570 | AU1000_RTC_MATCH0_INT, | |
571 | AU1000_RTC_MATCH1_INT, | |
572 | AU1000_RTC_MATCH2_INT, | |
573 | AU1000_IRDA_TX_INT, /* au1000 */ | |
574 | AU1000_IRDA_RX_INT, /* au1000 */ | |
575 | AU1000_USB_DEV_REQ_INT, | |
576 | AU1000_USB_DEV_SUS_INT, | |
577 | AU1000_USB_HOST_INT, | |
578 | AU1000_ACSYNC_INT, | |
579 | AU1000_MAC0_DMA_INT, | |
580 | AU1000_MAC1_DMA_INT, | |
581 | AU1000_I2S_UO_INT, /* au1000 */ | |
582 | AU1000_AC97C_INT, | |
583 | AU1000_GPIO_0, | |
584 | AU1000_GPIO_1, | |
585 | AU1000_GPIO_2, | |
586 | AU1000_GPIO_3, | |
587 | AU1000_GPIO_4, | |
588 | AU1000_GPIO_5, | |
589 | AU1000_GPIO_6, | |
590 | AU1000_GPIO_7, | |
591 | AU1000_GPIO_8, | |
592 | AU1000_GPIO_9, | |
593 | AU1000_GPIO_10, | |
594 | AU1000_GPIO_11, | |
595 | AU1000_GPIO_12, | |
596 | AU1000_GPIO_13, | |
597 | AU1000_GPIO_14, | |
598 | AU1000_GPIO_15, | |
599 | AU1000_GPIO_16, | |
600 | AU1000_GPIO_17, | |
601 | AU1000_GPIO_18, | |
602 | AU1000_GPIO_19, | |
603 | AU1000_GPIO_20, | |
604 | AU1000_GPIO_21, | |
605 | AU1000_GPIO_22, | |
606 | AU1000_GPIO_23, | |
607 | AU1000_GPIO_24, | |
608 | AU1000_GPIO_25, | |
609 | AU1000_GPIO_26, | |
610 | AU1000_GPIO_27, | |
611 | AU1000_GPIO_28, | |
612 | AU1000_GPIO_29, | |
613 | AU1000_GPIO_30, | |
614 | AU1000_GPIO_31, | |
615 | }; | |
1da177e4 | 616 | |
ff6814d5 SS |
617 | #define UART0_ADDR 0xB1100000 |
618 | #define UART1_ADDR 0xB1200000 | |
619 | #define UART2_ADDR 0xB1300000 | |
620 | #define UART3_ADDR 0xB1400000 | |
1da177e4 | 621 | |
ff6814d5 SS |
622 | #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ |
623 | #define USB_HOST_CONFIG 0xB017FFFC | |
1da177e4 | 624 | |
ff6814d5 SS |
625 | #define AU1000_ETH0_BASE 0xB0500000 |
626 | #define AU1000_ETH1_BASE 0xB0510000 | |
627 | #define AU1000_MAC0_ENABLE 0xB0520000 | |
628 | #define AU1000_MAC1_ENABLE 0xB0520004 | |
1da177e4 | 629 | #define NUM_ETH_INTERFACES 2 |
e3ad1c23 | 630 | #endif /* CONFIG_SOC_AU1000 */ |
1da177e4 LT |
631 | |
632 | /* Au1500 */ | |
633 | #ifdef CONFIG_SOC_AU1500 | |
9d360ab4 | 634 | enum soc_au1500_ints { |
0e8120e0 | 635 | AU1500_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, |
9d360ab4 RB |
636 | AU1500_UART0_INT = AU1500_FIRST_INT, |
637 | AU1000_PCI_INTA, /* au1500 */ | |
638 | AU1000_PCI_INTB, /* au1500 */ | |
639 | AU1500_UART3_INT, | |
640 | AU1000_PCI_INTC, /* au1500 */ | |
641 | AU1000_PCI_INTD, /* au1500 */ | |
642 | AU1000_DMA_INT_BASE, | |
643 | ||
644 | AU1000_TOY_INT = AU1500_FIRST_INT + 14, | |
645 | AU1000_TOY_MATCH0_INT, | |
646 | AU1000_TOY_MATCH1_INT, | |
647 | AU1000_TOY_MATCH2_INT, | |
648 | AU1000_RTC_INT, | |
649 | AU1000_RTC_MATCH0_INT, | |
650 | AU1000_RTC_MATCH1_INT, | |
651 | AU1000_RTC_MATCH2_INT, | |
652 | AU1500_PCI_ERR_INT, | |
6b7d0b2f | 653 | AU1500_RESERVED_INT, |
9d360ab4 RB |
654 | AU1000_USB_DEV_REQ_INT, |
655 | AU1000_USB_DEV_SUS_INT, | |
656 | AU1000_USB_HOST_INT, | |
657 | AU1000_ACSYNC_INT, | |
658 | AU1500_MAC0_DMA_INT, | |
659 | AU1500_MAC1_DMA_INT, | |
660 | AU1000_AC97C_INT = AU1500_FIRST_INT + 31, | |
661 | AU1000_GPIO_0, | |
662 | AU1000_GPIO_1, | |
663 | AU1000_GPIO_2, | |
664 | AU1000_GPIO_3, | |
665 | AU1000_GPIO_4, | |
666 | AU1000_GPIO_5, | |
667 | AU1000_GPIO_6, | |
668 | AU1000_GPIO_7, | |
669 | AU1000_GPIO_8, | |
670 | AU1000_GPIO_9, | |
671 | AU1000_GPIO_10, | |
672 | AU1000_GPIO_11, | |
673 | AU1000_GPIO_12, | |
674 | AU1000_GPIO_13, | |
675 | AU1000_GPIO_14, | |
676 | AU1000_GPIO_15, | |
677 | AU1500_GPIO_200, | |
678 | AU1500_GPIO_201, | |
679 | AU1500_GPIO_202, | |
680 | AU1500_GPIO_203, | |
681 | AU1500_GPIO_20, | |
682 | AU1500_GPIO_204, | |
683 | AU1500_GPIO_205, | |
684 | AU1500_GPIO_23, | |
685 | AU1500_GPIO_24, | |
686 | AU1500_GPIO_25, | |
687 | AU1500_GPIO_26, | |
688 | AU1500_GPIO_27, | |
689 | AU1500_GPIO_28, | |
690 | AU1500_GPIO_206, | |
691 | AU1500_GPIO_207, | |
692 | AU1500_GPIO_208_215, | |
693 | }; | |
1da177e4 | 694 | |
2d32ffa4 PP |
695 | /* shortcuts */ |
696 | #define INTA AU1000_PCI_INTA | |
697 | #define INTB AU1000_PCI_INTB | |
698 | #define INTC AU1000_PCI_INTC | |
699 | #define INTD AU1000_PCI_INTD | |
700 | ||
ff6814d5 SS |
701 | #define UART0_ADDR 0xB1100000 |
702 | #define UART3_ADDR 0xB1400000 | |
1da177e4 | 703 | |
ff6814d5 SS |
704 | #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ |
705 | #define USB_HOST_CONFIG 0xB017fffc | |
1da177e4 | 706 | |
ff6814d5 SS |
707 | #define AU1500_ETH0_BASE 0xB1500000 |
708 | #define AU1500_ETH1_BASE 0xB1510000 | |
709 | #define AU1500_MAC0_ENABLE 0xB1520000 | |
710 | #define AU1500_MAC1_ENABLE 0xB1520004 | |
1da177e4 | 711 | #define NUM_ETH_INTERFACES 2 |
e3ad1c23 | 712 | #endif /* CONFIG_SOC_AU1500 */ |
1da177e4 LT |
713 | |
714 | /* Au1100 */ | |
715 | #ifdef CONFIG_SOC_AU1100 | |
9d360ab4 | 716 | enum soc_au1100_ints { |
0e8120e0 | 717 | AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, |
b7863ee1 | 718 | AU1100_UART0_INT = AU1100_FIRST_INT, |
9d360ab4 RB |
719 | AU1100_UART1_INT, |
720 | AU1100_SD_INT, | |
721 | AU1100_UART3_INT, | |
722 | AU1000_SSI0_INT, | |
723 | AU1000_SSI1_INT, | |
724 | AU1000_DMA_INT_BASE, | |
725 | ||
726 | AU1000_TOY_INT = AU1100_FIRST_INT + 14, | |
727 | AU1000_TOY_MATCH0_INT, | |
728 | AU1000_TOY_MATCH1_INT, | |
729 | AU1000_TOY_MATCH2_INT, | |
730 | AU1000_RTC_INT, | |
731 | AU1000_RTC_MATCH0_INT, | |
732 | AU1000_RTC_MATCH1_INT, | |
733 | AU1000_RTC_MATCH2_INT, | |
734 | AU1000_IRDA_TX_INT, | |
735 | AU1000_IRDA_RX_INT, | |
736 | AU1000_USB_DEV_REQ_INT, | |
737 | AU1000_USB_DEV_SUS_INT, | |
738 | AU1000_USB_HOST_INT, | |
739 | AU1000_ACSYNC_INT, | |
740 | AU1100_MAC0_DMA_INT, | |
741 | AU1100_GPIO_208_215, | |
742 | AU1100_LCD_INT, | |
743 | AU1000_AC97C_INT, | |
744 | AU1000_GPIO_0, | |
745 | AU1000_GPIO_1, | |
746 | AU1000_GPIO_2, | |
747 | AU1000_GPIO_3, | |
748 | AU1000_GPIO_4, | |
749 | AU1000_GPIO_5, | |
750 | AU1000_GPIO_6, | |
751 | AU1000_GPIO_7, | |
752 | AU1000_GPIO_8, | |
753 | AU1000_GPIO_9, | |
754 | AU1000_GPIO_10, | |
755 | AU1000_GPIO_11, | |
756 | AU1000_GPIO_12, | |
757 | AU1000_GPIO_13, | |
758 | AU1000_GPIO_14, | |
759 | AU1000_GPIO_15, | |
760 | AU1000_GPIO_16, | |
761 | AU1000_GPIO_17, | |
762 | AU1000_GPIO_18, | |
763 | AU1000_GPIO_19, | |
764 | AU1000_GPIO_20, | |
765 | AU1000_GPIO_21, | |
766 | AU1000_GPIO_22, | |
767 | AU1000_GPIO_23, | |
768 | AU1000_GPIO_24, | |
769 | AU1000_GPIO_25, | |
770 | AU1000_GPIO_26, | |
771 | AU1000_GPIO_27, | |
772 | AU1000_GPIO_28, | |
773 | AU1000_GPIO_29, | |
774 | AU1000_GPIO_30, | |
775 | AU1000_GPIO_31, | |
776 | }; | |
1da177e4 | 777 | |
ff6814d5 SS |
778 | #define UART0_ADDR 0xB1100000 |
779 | #define UART1_ADDR 0xB1200000 | |
780 | #define UART3_ADDR 0xB1400000 | |
1da177e4 | 781 | |
ff6814d5 SS |
782 | #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ |
783 | #define USB_HOST_CONFIG 0xB017FFFC | |
1da177e4 | 784 | |
ff6814d5 SS |
785 | #define AU1100_ETH0_BASE 0xB0500000 |
786 | #define AU1100_MAC0_ENABLE 0xB0520000 | |
1da177e4 | 787 | #define NUM_ETH_INTERFACES 1 |
e3ad1c23 | 788 | #endif /* CONFIG_SOC_AU1100 */ |
1da177e4 LT |
789 | |
790 | #ifdef CONFIG_SOC_AU1550 | |
9d360ab4 | 791 | enum soc_au1550_ints { |
0e8120e0 | 792 | AU1550_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, |
9d360ab4 RB |
793 | AU1550_UART0_INT = AU1550_FIRST_INT, |
794 | AU1550_PCI_INTA, | |
795 | AU1550_PCI_INTB, | |
796 | AU1550_DDMA_INT, | |
797 | AU1550_CRYPTO_INT, | |
798 | AU1550_PCI_INTC, | |
799 | AU1550_PCI_INTD, | |
800 | AU1550_PCI_RST_INT, | |
801 | AU1550_UART1_INT, | |
802 | AU1550_UART3_INT, | |
803 | AU1550_PSC0_INT, | |
804 | AU1550_PSC1_INT, | |
805 | AU1550_PSC2_INT, | |
806 | AU1550_PSC3_INT, | |
807 | AU1000_TOY_INT, | |
808 | AU1000_TOY_MATCH0_INT, | |
809 | AU1000_TOY_MATCH1_INT, | |
810 | AU1000_TOY_MATCH2_INT, | |
811 | AU1000_RTC_INT, | |
812 | AU1000_RTC_MATCH0_INT, | |
813 | AU1000_RTC_MATCH1_INT, | |
814 | AU1000_RTC_MATCH2_INT, | |
815 | ||
816 | AU1550_NAND_INT = AU1550_FIRST_INT + 23, | |
817 | AU1550_USB_DEV_REQ_INT, | |
818 | AU1000_USB_DEV_REQ_INT = AU1550_USB_DEV_REQ_INT, | |
819 | AU1550_USB_DEV_SUS_INT, | |
820 | AU1000_USB_DEV_SUS_INT = AU1550_USB_DEV_SUS_INT, | |
821 | AU1550_USB_HOST_INT, | |
822 | AU1000_USB_HOST_INT = AU1550_USB_HOST_INT, | |
823 | AU1550_MAC0_DMA_INT, | |
824 | AU1550_MAC1_DMA_INT, | |
825 | AU1000_GPIO_0 = AU1550_FIRST_INT + 32, | |
826 | AU1000_GPIO_1, | |
827 | AU1000_GPIO_2, | |
828 | AU1000_GPIO_3, | |
829 | AU1000_GPIO_4, | |
830 | AU1000_GPIO_5, | |
831 | AU1000_GPIO_6, | |
832 | AU1000_GPIO_7, | |
833 | AU1000_GPIO_8, | |
834 | AU1000_GPIO_9, | |
835 | AU1000_GPIO_10, | |
836 | AU1000_GPIO_11, | |
837 | AU1000_GPIO_12, | |
838 | AU1000_GPIO_13, | |
839 | AU1000_GPIO_14, | |
840 | AU1000_GPIO_15, | |
841 | AU1550_GPIO_200, | |
842 | AU1500_GPIO_201_205, /* Logical or of GPIO201:205 */ | |
843 | AU1500_GPIO_16, | |
844 | AU1500_GPIO_17, | |
845 | AU1500_GPIO_20, | |
846 | AU1500_GPIO_21, | |
847 | AU1500_GPIO_22, | |
848 | AU1500_GPIO_23, | |
849 | AU1500_GPIO_24, | |
850 | AU1500_GPIO_25, | |
851 | AU1500_GPIO_26, | |
852 | AU1500_GPIO_27, | |
853 | AU1500_GPIO_28, | |
854 | AU1500_GPIO_206, | |
855 | AU1500_GPIO_207, | |
856 | AU1500_GPIO_208_218, /* Logical or of GPIO208:218 */ | |
857 | }; | |
1da177e4 | 858 | |
2d32ffa4 PP |
859 | /* shortcuts */ |
860 | #define INTA AU1550_PCI_INTA | |
861 | #define INTB AU1550_PCI_INTB | |
862 | #define INTC AU1550_PCI_INTC | |
863 | #define INTD AU1550_PCI_INTD | |
864 | ||
ff6814d5 SS |
865 | #define UART0_ADDR 0xB1100000 |
866 | #define UART1_ADDR 0xB1200000 | |
867 | #define UART3_ADDR 0xB1400000 | |
1da177e4 | 868 | |
ff6814d5 SS |
869 | #define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */ |
870 | #define USB_OHCI_LEN 0x00060000 | |
871 | #define USB_HOST_CONFIG 0xB4027ffc | |
1da177e4 | 872 | |
ff6814d5 SS |
873 | #define AU1550_ETH0_BASE 0xB0500000 |
874 | #define AU1550_ETH1_BASE 0xB0510000 | |
875 | #define AU1550_MAC0_ENABLE 0xB0520000 | |
876 | #define AU1550_MAC1_ENABLE 0xB0520004 | |
1da177e4 | 877 | #define NUM_ETH_INTERFACES 2 |
e3ad1c23 | 878 | #endif /* CONFIG_SOC_AU1550 */ |
1da177e4 LT |
879 | |
880 | #ifdef CONFIG_SOC_AU1200 | |
9d360ab4 | 881 | enum soc_au1200_ints { |
0e8120e0 | 882 | AU1200_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, |
9d360ab4 RB |
883 | AU1200_UART0_INT = AU1200_FIRST_INT, |
884 | AU1200_SWT_INT, | |
885 | AU1200_SD_INT, | |
886 | AU1200_DDMA_INT, | |
887 | AU1200_MAE_BE_INT, | |
888 | AU1200_GPIO_200, | |
889 | AU1200_GPIO_201, | |
890 | AU1200_GPIO_202, | |
891 | AU1200_UART1_INT, | |
892 | AU1200_MAE_FE_INT, | |
893 | AU1200_PSC0_INT, | |
894 | AU1200_PSC1_INT, | |
895 | AU1200_AES_INT, | |
896 | AU1200_CAMERA_INT, | |
897 | AU1000_TOY_INT, | |
898 | AU1000_TOY_MATCH0_INT, | |
899 | AU1000_TOY_MATCH1_INT, | |
900 | AU1000_TOY_MATCH2_INT, | |
901 | AU1000_RTC_INT, | |
902 | AU1000_RTC_MATCH0_INT, | |
903 | AU1000_RTC_MATCH1_INT, | |
904 | AU1000_RTC_MATCH2_INT, | |
d16797b3 ML |
905 | AU1200_GPIO_203, |
906 | AU1200_NAND_INT, | |
9d360ab4 RB |
907 | AU1200_GPIO_204, |
908 | AU1200_GPIO_205, | |
909 | AU1200_GPIO_206, | |
910 | AU1200_GPIO_207, | |
911 | AU1200_GPIO_208_215, /* Logical OR of 208:215 */ | |
912 | AU1200_USB_INT, | |
913 | AU1000_USB_HOST_INT = AU1200_USB_INT, | |
914 | AU1200_LCD_INT, | |
915 | AU1200_MAE_BOTH_INT, | |
916 | AU1000_GPIO_0, | |
917 | AU1000_GPIO_1, | |
918 | AU1000_GPIO_2, | |
919 | AU1000_GPIO_3, | |
920 | AU1000_GPIO_4, | |
921 | AU1000_GPIO_5, | |
922 | AU1000_GPIO_6, | |
923 | AU1000_GPIO_7, | |
924 | AU1000_GPIO_8, | |
925 | AU1000_GPIO_9, | |
926 | AU1000_GPIO_10, | |
927 | AU1000_GPIO_11, | |
928 | AU1000_GPIO_12, | |
929 | AU1000_GPIO_13, | |
930 | AU1000_GPIO_14, | |
931 | AU1000_GPIO_15, | |
932 | AU1000_GPIO_16, | |
933 | AU1000_GPIO_17, | |
934 | AU1000_GPIO_18, | |
935 | AU1000_GPIO_19, | |
936 | AU1000_GPIO_20, | |
937 | AU1000_GPIO_21, | |
938 | AU1000_GPIO_22, | |
939 | AU1000_GPIO_23, | |
940 | AU1000_GPIO_24, | |
941 | AU1000_GPIO_25, | |
942 | AU1000_GPIO_26, | |
943 | AU1000_GPIO_27, | |
944 | AU1000_GPIO_28, | |
945 | AU1000_GPIO_29, | |
946 | AU1000_GPIO_30, | |
947 | AU1000_GPIO_31, | |
948 | }; | |
1da177e4 | 949 | |
ff6814d5 SS |
950 | #define UART0_ADDR 0xB1100000 |
951 | #define UART1_ADDR 0xB1200000 | |
952 | ||
953 | #define USB_UOC_BASE 0x14020020 | |
954 | #define USB_UOC_LEN 0x20 | |
955 | #define USB_OHCI_BASE 0x14020100 | |
956 | #define USB_OHCI_LEN 0x100 | |
957 | #define USB_EHCI_BASE 0x14020200 | |
958 | #define USB_EHCI_LEN 0x100 | |
959 | #define USB_UDC_BASE 0x14022000 | |
960 | #define USB_UDC_LEN 0x2000 | |
961 | #define USB_MSR_BASE 0xB4020000 | |
962 | #define USB_MSR_MCFG 4 | |
963 | #define USBMSRMCFG_OMEMEN 0 | |
964 | #define USBMSRMCFG_OBMEN 1 | |
965 | #define USBMSRMCFG_EMEMEN 2 | |
966 | #define USBMSRMCFG_EBMEN 3 | |
967 | #define USBMSRMCFG_DMEMEN 4 | |
968 | #define USBMSRMCFG_DBMEN 5 | |
969 | #define USBMSRMCFG_GMEMEN 6 | |
970 | #define USBMSRMCFG_OHCCLKEN 16 | |
971 | #define USBMSRMCFG_EHCCLKEN 17 | |
972 | #define USBMSRMCFG_UDCCLKEN 18 | |
973 | #define USBMSRMCFG_PHYPLLEN 19 | |
974 | #define USBMSRMCFG_RDCOMB 30 | |
975 | #define USBMSRMCFG_PFEN 31 | |
e3ad1c23 PP |
976 | |
977 | #endif /* CONFIG_SOC_AU1200 */ | |
1da177e4 | 978 | |
0e8120e0 SS |
979 | #define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) |
980 | #define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31) | |
981 | #define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_BASE + 32) | |
982 | #define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31) | |
983 | ||
984 | #define AU1000_MAX_INTR AU1000_INTC1_INT_LAST | |
f3e8d1da | 985 | #define INTX 0xFF /* not valid */ |
1da177e4 | 986 | |
1da177e4 | 987 | /* Programmable Counters 0 and 1 */ |
ff6814d5 SS |
988 | #define SYS_BASE 0xB1900000 |
989 | #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) | |
990 | # define SYS_CNTRL_E1S (1 << 23) | |
991 | # define SYS_CNTRL_T1S (1 << 20) | |
992 | # define SYS_CNTRL_M21 (1 << 19) | |
993 | # define SYS_CNTRL_M11 (1 << 18) | |
994 | # define SYS_CNTRL_M01 (1 << 17) | |
995 | # define SYS_CNTRL_C1S (1 << 16) | |
996 | # define SYS_CNTRL_BP (1 << 14) | |
997 | # define SYS_CNTRL_EN1 (1 << 13) | |
998 | # define SYS_CNTRL_BT1 (1 << 12) | |
999 | # define SYS_CNTRL_EN0 (1 << 11) | |
1000 | # define SYS_CNTRL_BT0 (1 << 10) | |
1001 | # define SYS_CNTRL_E0 (1 << 8) | |
1002 | # define SYS_CNTRL_E0S (1 << 7) | |
1003 | # define SYS_CNTRL_32S (1 << 5) | |
1004 | # define SYS_CNTRL_T0S (1 << 4) | |
1005 | # define SYS_CNTRL_M20 (1 << 3) | |
1006 | # define SYS_CNTRL_M10 (1 << 2) | |
1007 | # define SYS_CNTRL_M00 (1 << 1) | |
1008 | # define SYS_CNTRL_C0S (1 << 0) | |
1da177e4 LT |
1009 | |
1010 | /* Programmable Counter 0 Registers */ | |
ff6814d5 SS |
1011 | #define SYS_TOYTRIM (SYS_BASE + 0) |
1012 | #define SYS_TOYWRITE (SYS_BASE + 4) | |
1013 | #define SYS_TOYMATCH0 (SYS_BASE + 8) | |
1014 | #define SYS_TOYMATCH1 (SYS_BASE + 0xC) | |
1015 | #define SYS_TOYMATCH2 (SYS_BASE + 0x10) | |
1016 | #define SYS_TOYREAD (SYS_BASE + 0x40) | |
1da177e4 LT |
1017 | |
1018 | /* Programmable Counter 1 Registers */ | |
ff6814d5 SS |
1019 | #define SYS_RTCTRIM (SYS_BASE + 0x44) |
1020 | #define SYS_RTCWRITE (SYS_BASE + 0x48) | |
1021 | #define SYS_RTCMATCH0 (SYS_BASE + 0x4C) | |
1022 | #define SYS_RTCMATCH1 (SYS_BASE + 0x50) | |
1023 | #define SYS_RTCMATCH2 (SYS_BASE + 0x54) | |
1024 | #define SYS_RTCREAD (SYS_BASE + 0x58) | |
1da177e4 LT |
1025 | |
1026 | /* I2S Controller */ | |
ff6814d5 SS |
1027 | #define I2S_DATA 0xB1000000 |
1028 | # define I2S_DATA_MASK 0xffffff | |
1029 | #define I2S_CONFIG 0xB1000004 | |
1030 | # define I2S_CONFIG_XU (1 << 25) | |
1031 | # define I2S_CONFIG_XO (1 << 24) | |
1032 | # define I2S_CONFIG_RU (1 << 23) | |
1033 | # define I2S_CONFIG_RO (1 << 22) | |
1034 | # define I2S_CONFIG_TR (1 << 21) | |
1035 | # define I2S_CONFIG_TE (1 << 20) | |
1036 | # define I2S_CONFIG_TF (1 << 19) | |
1037 | # define I2S_CONFIG_RR (1 << 18) | |
1038 | # define I2S_CONFIG_RE (1 << 17) | |
1039 | # define I2S_CONFIG_RF (1 << 16) | |
1040 | # define I2S_CONFIG_PD (1 << 11) | |
1041 | # define I2S_CONFIG_LB (1 << 10) | |
1042 | # define I2S_CONFIG_IC (1 << 9) | |
1043 | # define I2S_CONFIG_FM_BIT 7 | |
1044 | # define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) | |
1045 | # define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) | |
1046 | # define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) | |
1047 | # define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) | |
1048 | # define I2S_CONFIG_TN (1 << 6) | |
1049 | # define I2S_CONFIG_RN (1 << 5) | |
1050 | # define I2S_CONFIG_SZ_BIT 0 | |
1051 | # define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) | |
1052 | ||
1053 | #define I2S_CONTROL 0xB1000008 | |
1054 | # define I2S_CONTROL_D (1 << 1) | |
1055 | # define I2S_CONTROL_CE (1 << 0) | |
1da177e4 LT |
1056 | |
1057 | /* USB Host Controller */ | |
c5c64e22 | 1058 | #ifndef USB_OHCI_LEN |
ff6814d5 | 1059 | #define USB_OHCI_LEN 0x00100000 |
c5c64e22 SS |
1060 | #endif |
1061 | ||
1062 | #ifndef CONFIG_SOC_AU1200 | |
1da177e4 LT |
1063 | |
1064 | /* USB Device Controller */ | |
ff6814d5 SS |
1065 | #define USBD_EP0RD 0xB0200000 |
1066 | #define USBD_EP0WR 0xB0200004 | |
1067 | #define USBD_EP2WR 0xB0200008 | |
1068 | #define USBD_EP3WR 0xB020000C | |
1069 | #define USBD_EP4RD 0xB0200010 | |
1070 | #define USBD_EP5RD 0xB0200014 | |
1071 | #define USBD_INTEN 0xB0200018 | |
1072 | #define USBD_INTSTAT 0xB020001C | |
1073 | # define USBDEV_INT_SOF (1 << 12) | |
1074 | # define USBDEV_INT_HF_BIT 6 | |
25829b0e | 1075 | # define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) |
ff6814d5 | 1076 | # define USBDEV_INT_CMPLT_BIT 0 |
49a89efb | 1077 | # define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) |
ff6814d5 SS |
1078 | #define USBD_CONFIG 0xB0200020 |
1079 | #define USBD_EP0CS 0xB0200024 | |
1080 | #define USBD_EP2CS 0xB0200028 | |
1081 | #define USBD_EP3CS 0xB020002C | |
1082 | #define USBD_EP4CS 0xB0200030 | |
1083 | #define USBD_EP5CS 0xB0200034 | |
1084 | # define USBDEV_CS_SU (1 << 14) | |
1085 | # define USBDEV_CS_NAK (1 << 13) | |
1086 | # define USBDEV_CS_ACK (1 << 12) | |
1087 | # define USBDEV_CS_BUSY (1 << 11) | |
1088 | # define USBDEV_CS_TSIZE_BIT 1 | |
1089 | # define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) | |
1090 | # define USBDEV_CS_STALL (1 << 0) | |
1091 | #define USBD_EP0RDSTAT 0xB0200040 | |
1092 | #define USBD_EP0WRSTAT 0xB0200044 | |
1093 | #define USBD_EP2WRSTAT 0xB0200048 | |
1094 | #define USBD_EP3WRSTAT 0xB020004C | |
1095 | #define USBD_EP4RDSTAT 0xB0200050 | |
1096 | #define USBD_EP5RDSTAT 0xB0200054 | |
1097 | # define USBDEV_FSTAT_FLUSH (1 << 6) | |
1098 | # define USBDEV_FSTAT_UF (1 << 5) | |
1099 | # define USBDEV_FSTAT_OF (1 << 4) | |
1100 | # define USBDEV_FSTAT_FCNT_BIT 0 | |
49a89efb | 1101 | # define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) |
ff6814d5 SS |
1102 | #define USBD_ENABLE 0xB0200058 |
1103 | # define USBDEV_ENABLE (1 << 1) | |
1104 | # define USBDEV_CE (1 << 0) | |
1da177e4 | 1105 | |
e3ad1c23 PP |
1106 | #endif /* !CONFIG_SOC_AU1200 */ |
1107 | ||
1da177e4 LT |
1108 | /* Ethernet Controllers */ |
1109 | ||
1110 | /* 4 byte offsets from AU1000_ETH_BASE */ | |
ff6814d5 SS |
1111 | #define MAC_CONTROL 0x0 |
1112 | # define MAC_RX_ENABLE (1 << 2) | |
1113 | # define MAC_TX_ENABLE (1 << 3) | |
1114 | # define MAC_DEF_CHECK (1 << 5) | |
1115 | # define MAC_SET_BL(X) (((X) & 0x3) << 6) | |
1116 | # define MAC_AUTO_PAD (1 << 8) | |
1117 | # define MAC_DISABLE_RETRY (1 << 10) | |
1118 | # define MAC_DISABLE_BCAST (1 << 11) | |
1119 | # define MAC_LATE_COL (1 << 12) | |
1120 | # define MAC_HASH_MODE (1 << 13) | |
1121 | # define MAC_HASH_ONLY (1 << 15) | |
1122 | # define MAC_PASS_ALL (1 << 16) | |
1123 | # define MAC_INVERSE_FILTER (1 << 17) | |
1124 | # define MAC_PROMISCUOUS (1 << 18) | |
1125 | # define MAC_PASS_ALL_MULTI (1 << 19) | |
1126 | # define MAC_FULL_DUPLEX (1 << 20) | |
1127 | # define MAC_NORMAL_MODE 0 | |
1128 | # define MAC_INT_LOOPBACK (1 << 21) | |
1129 | # define MAC_EXT_LOOPBACK (1 << 22) | |
1130 | # define MAC_DISABLE_RX_OWN (1 << 23) | |
1131 | # define MAC_BIG_ENDIAN (1 << 30) | |
1132 | # define MAC_RX_ALL (1 << 31) | |
1133 | #define MAC_ADDRESS_HIGH 0x4 | |
1134 | #define MAC_ADDRESS_LOW 0x8 | |
1135 | #define MAC_MCAST_HIGH 0xC | |
1136 | #define MAC_MCAST_LOW 0x10 | |
1137 | #define MAC_MII_CNTRL 0x14 | |
1138 | # define MAC_MII_BUSY (1 << 0) | |
1139 | # define MAC_MII_READ 0 | |
1140 | # define MAC_MII_WRITE (1 << 1) | |
1141 | # define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6) | |
1142 | # define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11) | |
1143 | #define MAC_MII_DATA 0x18 | |
1144 | #define MAC_FLOW_CNTRL 0x1C | |
1145 | # define MAC_FLOW_CNTRL_BUSY (1 << 0) | |
1146 | # define MAC_FLOW_CNTRL_ENABLE (1 << 1) | |
1147 | # define MAC_PASS_CONTROL (1 << 2) | |
1148 | # define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16) | |
1149 | #define MAC_VLAN1_TAG 0x20 | |
1150 | #define MAC_VLAN2_TAG 0x24 | |
1da177e4 LT |
1151 | |
1152 | /* Ethernet Controller Enable */ | |
1153 | ||
ff6814d5 SS |
1154 | # define MAC_EN_CLOCK_ENABLE (1 << 0) |
1155 | # define MAC_EN_RESET0 (1 << 1) | |
1156 | # define MAC_EN_TOSS (0 << 2) | |
1157 | # define MAC_EN_CACHEABLE (1 << 3) | |
1158 | # define MAC_EN_RESET1 (1 << 4) | |
1159 | # define MAC_EN_RESET2 (1 << 5) | |
1160 | # define MAC_DMA_RESET (1 << 6) | |
1da177e4 LT |
1161 | |
1162 | /* Ethernet Controller DMA Channels */ | |
1163 | ||
ff6814d5 SS |
1164 | #define MAC0_TX_DMA_ADDR 0xB4004000 |
1165 | #define MAC1_TX_DMA_ADDR 0xB4004200 | |
1da177e4 | 1166 | /* offsets from MAC_TX_RING_ADDR address */ |
ff6814d5 SS |
1167 | #define MAC_TX_BUFF0_STATUS 0x0 |
1168 | # define TX_FRAME_ABORTED (1 << 0) | |
1169 | # define TX_JAB_TIMEOUT (1 << 1) | |
1170 | # define TX_NO_CARRIER (1 << 2) | |
1171 | # define TX_LOSS_CARRIER (1 << 3) | |
1172 | # define TX_EXC_DEF (1 << 4) | |
1173 | # define TX_LATE_COLL_ABORT (1 << 5) | |
1174 | # define TX_EXC_COLL (1 << 6) | |
1175 | # define TX_UNDERRUN (1 << 7) | |
1176 | # define TX_DEFERRED (1 << 8) | |
1177 | # define TX_LATE_COLL (1 << 9) | |
1178 | # define TX_COLL_CNT_MASK (0xF << 10) | |
1179 | # define TX_PKT_RETRY (1 << 31) | |
1180 | #define MAC_TX_BUFF0_ADDR 0x4 | |
1181 | # define TX_DMA_ENABLE (1 << 0) | |
1182 | # define TX_T_DONE (1 << 1) | |
1183 | # define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) | |
1184 | #define MAC_TX_BUFF0_LEN 0x8 | |
1185 | #define MAC_TX_BUFF1_STATUS 0x10 | |
1186 | #define MAC_TX_BUFF1_ADDR 0x14 | |
1187 | #define MAC_TX_BUFF1_LEN 0x18 | |
1188 | #define MAC_TX_BUFF2_STATUS 0x20 | |
1189 | #define MAC_TX_BUFF2_ADDR 0x24 | |
1190 | #define MAC_TX_BUFF2_LEN 0x28 | |
1191 | #define MAC_TX_BUFF3_STATUS 0x30 | |
1192 | #define MAC_TX_BUFF3_ADDR 0x34 | |
1193 | #define MAC_TX_BUFF3_LEN 0x38 | |
1194 | ||
1195 | #define MAC0_RX_DMA_ADDR 0xB4004100 | |
1196 | #define MAC1_RX_DMA_ADDR 0xB4004300 | |
1da177e4 | 1197 | /* offsets from MAC_RX_RING_ADDR */ |
ff6814d5 SS |
1198 | #define MAC_RX_BUFF0_STATUS 0x0 |
1199 | # define RX_FRAME_LEN_MASK 0x3fff | |
1200 | # define RX_WDOG_TIMER (1 << 14) | |
1201 | # define RX_RUNT (1 << 15) | |
1202 | # define RX_OVERLEN (1 << 16) | |
1203 | # define RX_COLL (1 << 17) | |
1204 | # define RX_ETHER (1 << 18) | |
1205 | # define RX_MII_ERROR (1 << 19) | |
1206 | # define RX_DRIBBLING (1 << 20) | |
1207 | # define RX_CRC_ERROR (1 << 21) | |
1208 | # define RX_VLAN1 (1 << 22) | |
1209 | # define RX_VLAN2 (1 << 23) | |
1210 | # define RX_LEN_ERROR (1 << 24) | |
1211 | # define RX_CNTRL_FRAME (1 << 25) | |
1212 | # define RX_U_CNTRL_FRAME (1 << 26) | |
1213 | # define RX_MCAST_FRAME (1 << 27) | |
1214 | # define RX_BCAST_FRAME (1 << 28) | |
1215 | # define RX_FILTER_FAIL (1 << 29) | |
1216 | # define RX_PACKET_FILTER (1 << 30) | |
1217 | # define RX_MISSED_FRAME (1 << 31) | |
49a89efb RB |
1218 | |
1219 | # define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ | |
ff6814d5 SS |
1220 | RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ |
1221 | RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) | |
1222 | #define MAC_RX_BUFF0_ADDR 0x4 | |
1223 | # define RX_DMA_ENABLE (1 << 0) | |
1224 | # define RX_T_DONE (1 << 1) | |
1225 | # define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) | |
1226 | # define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0) | |
1227 | #define MAC_RX_BUFF1_STATUS 0x10 | |
1228 | #define MAC_RX_BUFF1_ADDR 0x14 | |
1229 | #define MAC_RX_BUFF2_STATUS 0x20 | |
1230 | #define MAC_RX_BUFF2_ADDR 0x24 | |
1231 | #define MAC_RX_BUFF3_STATUS 0x30 | |
1232 | #define MAC_RX_BUFF3_ADDR 0x34 | |
1da177e4 LT |
1233 | |
1234 | /* UARTS 0-3 */ | |
ff6814d5 | 1235 | #define UART_BASE UART0_ADDR |
492fd5f2 | 1236 | #ifdef CONFIG_SOC_AU1200 |
ff6814d5 | 1237 | #define UART_DEBUG_BASE UART1_ADDR |
492fd5f2 | 1238 | #else |
ff6814d5 | 1239 | #define UART_DEBUG_BASE UART3_ADDR |
492fd5f2 | 1240 | #endif |
1da177e4 LT |
1241 | |
1242 | #define UART_RX 0 /* Receive buffer */ | |
1243 | #define UART_TX 4 /* Transmit buffer */ | |
1244 | #define UART_IER 8 /* Interrupt Enable Register */ | |
1245 | #define UART_IIR 0xC /* Interrupt ID Register */ | |
1246 | #define UART_FCR 0x10 /* FIFO Control Register */ | |
1247 | #define UART_LCR 0x14 /* Line Control Register */ | |
1248 | #define UART_MCR 0x18 /* Modem Control Register */ | |
1249 | #define UART_LSR 0x1C /* Line Status Register */ | |
1250 | #define UART_MSR 0x20 /* Modem Status Register */ | |
1251 | #define UART_CLK 0x28 /* Baud Rate Clock Divider */ | |
1252 | #define UART_MOD_CNTRL 0x100 /* Module Control */ | |
1253 | ||
1254 | #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ | |
1255 | #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ | |
1256 | #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ | |
1257 | #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ | |
1258 | #define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */ | |
1259 | #define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */ | |
1260 | #define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */ | |
1261 | #define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */ | |
1262 | #define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */ | |
1263 | #define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */ | |
1264 | #define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */ | |
1265 | #define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */ | |
1266 | #define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */ | |
1267 | ||
1268 | /* | |
1269 | * These are the definitions for the Line Control Register | |
1270 | */ | |
1271 | #define UART_LCR_SBC 0x40 /* Set break control */ | |
1272 | #define UART_LCR_SPAR 0x20 /* Stick parity (?) */ | |
1273 | #define UART_LCR_EPAR 0x10 /* Even parity select */ | |
1274 | #define UART_LCR_PARITY 0x08 /* Parity Enable */ | |
1275 | #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */ | |
1276 | #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ | |
1277 | #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ | |
1278 | #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ | |
1279 | #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ | |
1280 | ||
1281 | /* | |
1282 | * These are the definitions for the Line Status Register | |
1283 | */ | |
1284 | #define UART_LSR_TEMT 0x40 /* Transmitter empty */ | |
1285 | #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ | |
1286 | #define UART_LSR_BI 0x10 /* Break interrupt indicator */ | |
1287 | #define UART_LSR_FE 0x08 /* Frame error indicator */ | |
1288 | #define UART_LSR_PE 0x04 /* Parity error indicator */ | |
1289 | #define UART_LSR_OE 0x02 /* Overrun error indicator */ | |
1290 | #define UART_LSR_DR 0x01 /* Receiver data ready */ | |
1291 | ||
1292 | /* | |
1293 | * These are the definitions for the Interrupt Identification Register | |
1294 | */ | |
1295 | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ | |
1296 | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ | |
1297 | #define UART_IIR_MSI 0x00 /* Modem status interrupt */ | |
1298 | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ | |
1299 | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ | |
1300 | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ | |
1301 | ||
1302 | /* | |
1303 | * These are the definitions for the Interrupt Enable Register | |
1304 | */ | |
1305 | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ | |
1306 | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ | |
1307 | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ | |
1308 | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ | |
1309 | ||
1310 | /* | |
1311 | * These are the definitions for the Modem Control Register | |
1312 | */ | |
1313 | #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ | |
1314 | #define UART_MCR_OUT2 0x08 /* Out2 complement */ | |
1315 | #define UART_MCR_OUT1 0x04 /* Out1 complement */ | |
1316 | #define UART_MCR_RTS 0x02 /* RTS complement */ | |
1317 | #define UART_MCR_DTR 0x01 /* DTR complement */ | |
1318 | ||
1319 | /* | |
1320 | * These are the definitions for the Modem Status Register | |
1321 | */ | |
1322 | #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ | |
1323 | #define UART_MSR_RI 0x40 /* Ring Indicator */ | |
1324 | #define UART_MSR_DSR 0x20 /* Data Set Ready */ | |
1325 | #define UART_MSR_CTS 0x10 /* Clear to Send */ | |
1326 | #define UART_MSR_DDCD 0x08 /* Delta DCD */ | |
1327 | #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ | |
1328 | #define UART_MSR_DDSR 0x02 /* Delta DSR */ | |
1329 | #define UART_MSR_DCTS 0x01 /* Delta CTS */ | |
1330 | #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ | |
1331 | ||
1da177e4 | 1332 | /* SSIO */ |
ff6814d5 SS |
1333 | #define SSI0_STATUS 0xB1600000 |
1334 | # define SSI_STATUS_BF (1 << 4) | |
1335 | # define SSI_STATUS_OF (1 << 3) | |
1336 | # define SSI_STATUS_UF (1 << 2) | |
1337 | # define SSI_STATUS_D (1 << 1) | |
1338 | # define SSI_STATUS_B (1 << 0) | |
1339 | #define SSI0_INT 0xB1600004 | |
1340 | # define SSI_INT_OI (1 << 3) | |
1341 | # define SSI_INT_UI (1 << 2) | |
1342 | # define SSI_INT_DI (1 << 1) | |
1343 | #define SSI0_INT_ENABLE 0xB1600008 | |
1344 | # define SSI_INTE_OIE (1 << 3) | |
1345 | # define SSI_INTE_UIE (1 << 2) | |
1346 | # define SSI_INTE_DIE (1 << 1) | |
1347 | #define SSI0_CONFIG 0xB1600020 | |
1348 | # define SSI_CONFIG_AO (1 << 24) | |
1349 | # define SSI_CONFIG_DO (1 << 23) | |
1350 | # define SSI_CONFIG_ALEN_BIT 20 | |
1351 | # define SSI_CONFIG_ALEN_MASK (0x7 << 20) | |
1352 | # define SSI_CONFIG_DLEN_BIT 16 | |
1353 | # define SSI_CONFIG_DLEN_MASK (0x7 << 16) | |
1354 | # define SSI_CONFIG_DD (1 << 11) | |
1355 | # define SSI_CONFIG_AD (1 << 10) | |
1356 | # define SSI_CONFIG_BM_BIT 8 | |
1357 | # define SSI_CONFIG_BM_MASK (0x3 << 8) | |
1358 | # define SSI_CONFIG_CE (1 << 7) | |
1359 | # define SSI_CONFIG_DP (1 << 6) | |
1360 | # define SSI_CONFIG_DL (1 << 5) | |
1361 | # define SSI_CONFIG_EP (1 << 4) | |
1362 | #define SSI0_ADATA 0xB1600024 | |
1363 | # define SSI_AD_D (1 << 24) | |
1364 | # define SSI_AD_ADDR_BIT 16 | |
1365 | # define SSI_AD_ADDR_MASK (0xff << 16) | |
1366 | # define SSI_AD_DATA_BIT 0 | |
1367 | # define SSI_AD_DATA_MASK (0xfff << 0) | |
1368 | #define SSI0_CLKDIV 0xB1600028 | |
1369 | #define SSI0_CONTROL 0xB1600100 | |
1370 | # define SSI_CONTROL_CD (1 << 1) | |
1371 | # define SSI_CONTROL_E (1 << 0) | |
1da177e4 LT |
1372 | |
1373 | /* SSI1 */ | |
ff6814d5 SS |
1374 | #define SSI1_STATUS 0xB1680000 |
1375 | #define SSI1_INT 0xB1680004 | |
1376 | #define SSI1_INT_ENABLE 0xB1680008 | |
1377 | #define SSI1_CONFIG 0xB1680020 | |
1378 | #define SSI1_ADATA 0xB1680024 | |
1379 | #define SSI1_CLKDIV 0xB1680028 | |
1380 | #define SSI1_ENABLE 0xB1680100 | |
1da177e4 LT |
1381 | |
1382 | /* | |
1383 | * Register content definitions | |
1384 | */ | |
ff6814d5 SS |
1385 | #define SSI_STATUS_BF (1 << 4) |
1386 | #define SSI_STATUS_OF (1 << 3) | |
1387 | #define SSI_STATUS_UF (1 << 2) | |
1388 | #define SSI_STATUS_D (1 << 1) | |
1389 | #define SSI_STATUS_B (1 << 0) | |
1da177e4 LT |
1390 | |
1391 | /* SSI_INT */ | |
ff6814d5 SS |
1392 | #define SSI_INT_OI (1 << 3) |
1393 | #define SSI_INT_UI (1 << 2) | |
1394 | #define SSI_INT_DI (1 << 1) | |
1da177e4 LT |
1395 | |
1396 | /* SSI_INTEN */ | |
ff6814d5 SS |
1397 | #define SSI_INTEN_OIE (1 << 3) |
1398 | #define SSI_INTEN_UIE (1 << 2) | |
1399 | #define SSI_INTEN_DIE (1 << 1) | |
1400 | ||
1401 | #define SSI_CONFIG_AO (1 << 24) | |
1402 | #define SSI_CONFIG_DO (1 << 23) | |
1403 | #define SSI_CONFIG_ALEN (7 << 20) | |
1404 | #define SSI_CONFIG_DLEN (15 << 16) | |
1405 | #define SSI_CONFIG_DD (1 << 11) | |
1406 | #define SSI_CONFIG_AD (1 << 10) | |
1407 | #define SSI_CONFIG_BM (3 << 8) | |
1408 | #define SSI_CONFIG_CE (1 << 7) | |
1409 | #define SSI_CONFIG_DP (1 << 6) | |
1410 | #define SSI_CONFIG_DL (1 << 5) | |
1411 | #define SSI_CONFIG_EP (1 << 4) | |
1412 | #define SSI_CONFIG_ALEN_N(N) ((N-1) << 20) | |
1413 | #define SSI_CONFIG_DLEN_N(N) ((N-1) << 16) | |
1414 | #define SSI_CONFIG_BM_HI (0 << 8) | |
1415 | #define SSI_CONFIG_BM_LO (1 << 8) | |
1416 | #define SSI_CONFIG_BM_CY (2 << 8) | |
1417 | ||
1418 | #define SSI_ADATA_D (1 << 24) | |
1419 | #define SSI_ADATA_ADDR (0xFF << 16) | |
1420 | #define SSI_ADATA_DATA 0x0FFF | |
1421 | #define SSI_ADATA_ADDR_N(N) (N << 16) | |
1422 | ||
1423 | #define SSI_ENABLE_CD (1 << 1) | |
1424 | #define SSI_ENABLE_E (1 << 0) | |
1da177e4 LT |
1425 | |
1426 | /* IrDA Controller */ | |
ff6814d5 SS |
1427 | #define IRDA_BASE 0xB0300000 |
1428 | #define IR_RING_PTR_STATUS (IRDA_BASE + 0x00) | |
1429 | #define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04) | |
1430 | #define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08) | |
1431 | #define IR_RING_SIZE (IRDA_BASE + 0x0C) | |
1432 | #define IR_RING_PROMPT (IRDA_BASE + 0x10) | |
1433 | #define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14) | |
1434 | #define IR_INT_CLEAR (IRDA_BASE + 0x18) | |
1435 | #define IR_CONFIG_1 (IRDA_BASE + 0x20) | |
1436 | # define IR_RX_INVERT_LED (1 << 0) | |
1437 | # define IR_TX_INVERT_LED (1 << 1) | |
1438 | # define IR_ST (1 << 2) | |
1439 | # define IR_SF (1 << 3) | |
1440 | # define IR_SIR (1 << 4) | |
1441 | # define IR_MIR (1 << 5) | |
1442 | # define IR_FIR (1 << 6) | |
1443 | # define IR_16CRC (1 << 7) | |
1444 | # define IR_TD (1 << 8) | |
1445 | # define IR_RX_ALL (1 << 9) | |
1446 | # define IR_DMA_ENABLE (1 << 10) | |
1447 | # define IR_RX_ENABLE (1 << 11) | |
1448 | # define IR_TX_ENABLE (1 << 12) | |
1449 | # define IR_LOOPBACK (1 << 14) | |
1450 | # define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ | |
1451 | IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) | |
1452 | #define IR_SIR_FLAGS (IRDA_BASE + 0x24) | |
1453 | #define IR_ENABLE (IRDA_BASE + 0x28) | |
1454 | # define IR_RX_STATUS (1 << 9) | |
1455 | # define IR_TX_STATUS (1 << 10) | |
1456 | #define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C) | |
1457 | #define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30) | |
1458 | #define IR_MAX_PKT_LEN (IRDA_BASE + 0x34) | |
1459 | #define IR_RX_BYTE_CNT (IRDA_BASE + 0x38) | |
1460 | #define IR_CONFIG_2 (IRDA_BASE + 0x3C) | |
1461 | # define IR_MODE_INV (1 << 0) | |
1462 | # define IR_ONE_PIN (1 << 1) | |
1463 | #define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40) | |
1da177e4 LT |
1464 | |
1465 | /* GPIO */ | |
ff6814d5 SS |
1466 | #define SYS_PINFUNC 0xB190002C |
1467 | # define SYS_PF_USB (1 << 15) /* 2nd USB device/host */ | |
1468 | # define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */ | |
1469 | # define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */ | |
1470 | # define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */ | |
1471 | # define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */ | |
1472 | # define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */ | |
1473 | # define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */ | |
1474 | # define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */ | |
1475 | # define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */ | |
1476 | # define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */ | |
1477 | # define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */ | |
1478 | # define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */ | |
1479 | # define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */ | |
1480 | # define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */ | |
1481 | # define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */ | |
1482 | # define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */ | |
1483 | ||
1484 | /* Au1100 only */ | |
1485 | # define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */ | |
1486 | # define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */ | |
1487 | # define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */ | |
1488 | # define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */ | |
1489 | ||
1490 | /* Au1550 only. Redefines lots of pins */ | |
1491 | # define SYS_PF_PSC2_MASK (7 << 17) | |
1492 | # define SYS_PF_PSC2_AC97 0 | |
1493 | # define SYS_PF_PSC2_SPI 0 | |
1494 | # define SYS_PF_PSC2_I2S (1 << 17) | |
1495 | # define SYS_PF_PSC2_SMBUS (3 << 17) | |
1496 | # define SYS_PF_PSC2_GPIO (7 << 17) | |
1497 | # define SYS_PF_PSC3_MASK (7 << 20) | |
1498 | # define SYS_PF_PSC3_AC97 0 | |
1499 | # define SYS_PF_PSC3_SPI 0 | |
1500 | # define SYS_PF_PSC3_I2S (1 << 20) | |
1501 | # define SYS_PF_PSC3_SMBUS (3 << 20) | |
1502 | # define SYS_PF_PSC3_GPIO (7 << 20) | |
1503 | # define SYS_PF_PSC1_S1 (1 << 1) | |
1504 | # define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) | |
1505 | ||
1506 | /* Au1200 only */ | |
e3ad1c23 | 1507 | #ifdef CONFIG_SOC_AU1200 |
ff6814d5 SS |
1508 | #define SYS_PINFUNC_DMA (1 << 31) |
1509 | #define SYS_PINFUNC_S0A (1 << 30) | |
1510 | #define SYS_PINFUNC_S1A (1 << 29) | |
1511 | #define SYS_PINFUNC_LP0 (1 << 28) | |
1512 | #define SYS_PINFUNC_LP1 (1 << 27) | |
1513 | #define SYS_PINFUNC_LD16 (1 << 26) | |
1514 | #define SYS_PINFUNC_LD8 (1 << 25) | |
1515 | #define SYS_PINFUNC_LD1 (1 << 24) | |
1516 | #define SYS_PINFUNC_LD0 (1 << 23) | |
1517 | #define SYS_PINFUNC_P1A (3 << 21) | |
1518 | #define SYS_PINFUNC_P1B (1 << 20) | |
1519 | #define SYS_PINFUNC_FS3 (1 << 19) | |
1520 | #define SYS_PINFUNC_P0A (3 << 17) | |
1521 | #define SYS_PINFUNC_CS (1 << 16) | |
1522 | #define SYS_PINFUNC_CIM (1 << 15) | |
1523 | #define SYS_PINFUNC_P1C (1 << 14) | |
1524 | #define SYS_PINFUNC_U1T (1 << 12) | |
1525 | #define SYS_PINFUNC_U1R (1 << 11) | |
1526 | #define SYS_PINFUNC_EX1 (1 << 10) | |
1527 | #define SYS_PINFUNC_EX0 (1 << 9) | |
1528 | #define SYS_PINFUNC_U0R (1 << 8) | |
1529 | #define SYS_PINFUNC_MC (1 << 7) | |
1530 | #define SYS_PINFUNC_S0B (1 << 6) | |
1531 | #define SYS_PINFUNC_S0C (1 << 5) | |
1532 | #define SYS_PINFUNC_P0B (1 << 4) | |
1533 | #define SYS_PINFUNC_U0T (1 << 3) | |
1534 | #define SYS_PINFUNC_S1B (1 << 2) | |
e3ad1c23 PP |
1535 | #endif |
1536 | ||
ff6814d5 SS |
1537 | #define SYS_TRIOUTRD 0xB1900100 |
1538 | #define SYS_TRIOUTCLR 0xB1900100 | |
1539 | #define SYS_OUTPUTRD 0xB1900108 | |
1540 | #define SYS_OUTPUTSET 0xB1900108 | |
1541 | #define SYS_OUTPUTCLR 0xB190010C | |
1542 | #define SYS_PINSTATERD 0xB1900110 | |
1543 | #define SYS_PININPUTEN 0xB1900110 | |
1da177e4 LT |
1544 | |
1545 | /* GPIO2, Au1500, Au1550 only */ | |
ff6814d5 SS |
1546 | #define GPIO2_BASE 0xB1700000 |
1547 | #define GPIO2_DIR (GPIO2_BASE + 0) | |
1548 | #define GPIO2_OUTPUT (GPIO2_BASE + 8) | |
1549 | #define GPIO2_PINSTATE (GPIO2_BASE + 0xC) | |
1550 | #define GPIO2_INTENABLE (GPIO2_BASE + 0x10) | |
1551 | #define GPIO2_ENABLE (GPIO2_BASE + 0x14) | |
1da177e4 LT |
1552 | |
1553 | /* Power Management */ | |
ff6814d5 SS |
1554 | #define SYS_SCRATCH0 0xB1900018 |
1555 | #define SYS_SCRATCH1 0xB190001C | |
1556 | #define SYS_WAKEMSK 0xB1900034 | |
1557 | #define SYS_ENDIAN 0xB1900038 | |
1558 | #define SYS_POWERCTRL 0xB190003C | |
1559 | #define SYS_WAKESRC 0xB190005C | |
1560 | #define SYS_SLPPWR 0xB1900078 | |
1561 | #define SYS_SLEEP 0xB190007C | |
1da177e4 | 1562 | |
61f9c58d ML |
1563 | #define SYS_WAKEMSK_D2 (1 << 9) |
1564 | #define SYS_WAKEMSK_M2 (1 << 8) | |
1565 | #define SYS_WAKEMSK_GPIO(x) (1 << (x)) | |
1566 | ||
1da177e4 | 1567 | /* Clock Controller */ |
ff6814d5 SS |
1568 | #define SYS_FREQCTRL0 0xB1900020 |
1569 | # define SYS_FC_FRDIV2_BIT 22 | |
1570 | # define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) | |
1571 | # define SYS_FC_FE2 (1 << 21) | |
1572 | # define SYS_FC_FS2 (1 << 20) | |
1573 | # define SYS_FC_FRDIV1_BIT 12 | |
1574 | # define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) | |
1575 | # define SYS_FC_FE1 (1 << 11) | |
1576 | # define SYS_FC_FS1 (1 << 10) | |
1577 | # define SYS_FC_FRDIV0_BIT 2 | |
1578 | # define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) | |
1579 | # define SYS_FC_FE0 (1 << 1) | |
1580 | # define SYS_FC_FS0 (1 << 0) | |
1581 | #define SYS_FREQCTRL1 0xB1900024 | |
1582 | # define SYS_FC_FRDIV5_BIT 22 | |
1583 | # define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) | |
1584 | # define SYS_FC_FE5 (1 << 21) | |
1585 | # define SYS_FC_FS5 (1 << 20) | |
1586 | # define SYS_FC_FRDIV4_BIT 12 | |
1587 | # define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) | |
1588 | # define SYS_FC_FE4 (1 << 11) | |
1589 | # define SYS_FC_FS4 (1 << 10) | |
1590 | # define SYS_FC_FRDIV3_BIT 2 | |
1591 | # define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) | |
1592 | # define SYS_FC_FE3 (1 << 1) | |
1593 | # define SYS_FC_FS3 (1 << 0) | |
1594 | #define SYS_CLKSRC 0xB1900028 | |
1595 | # define SYS_CS_ME1_BIT 27 | |
1596 | # define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT) | |
1597 | # define SYS_CS_DE1 (1 << 26) | |
1598 | # define SYS_CS_CE1 (1 << 25) | |
1599 | # define SYS_CS_ME0_BIT 22 | |
1600 | # define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT) | |
1601 | # define SYS_CS_DE0 (1 << 21) | |
1602 | # define SYS_CS_CE0 (1 << 20) | |
1603 | # define SYS_CS_MI2_BIT 17 | |
1604 | # define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT) | |
1605 | # define SYS_CS_DI2 (1 << 16) | |
1606 | # define SYS_CS_CI2 (1 << 15) | |
3b495f2b | 1607 | #ifdef CONFIG_SOC_AU1100 |
ff6814d5 SS |
1608 | # define SYS_CS_ML_BIT 7 |
1609 | # define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT) | |
1610 | # define SYS_CS_DL (1 << 6) | |
1611 | # define SYS_CS_CL (1 << 5) | |
3b495f2b | 1612 | #else |
ff6814d5 SS |
1613 | # define SYS_CS_MUH_BIT 12 |
1614 | # define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT) | |
1615 | # define SYS_CS_DUH (1 << 11) | |
1616 | # define SYS_CS_CUH (1 << 10) | |
1617 | # define SYS_CS_MUD_BIT 7 | |
1618 | # define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT) | |
1619 | # define SYS_CS_DUD (1 << 6) | |
1620 | # define SYS_CS_CUD (1 << 5) | |
3b495f2b | 1621 | #endif |
ff6814d5 SS |
1622 | # define SYS_CS_MIR_BIT 2 |
1623 | # define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT) | |
1624 | # define SYS_CS_DIR (1 << 1) | |
1625 | # define SYS_CS_CIR (1 << 0) | |
1626 | ||
1627 | # define SYS_CS_MUX_AUX 0x1 | |
1628 | # define SYS_CS_MUX_FQ0 0x2 | |
1629 | # define SYS_CS_MUX_FQ1 0x3 | |
1630 | # define SYS_CS_MUX_FQ2 0x4 | |
1631 | # define SYS_CS_MUX_FQ3 0x5 | |
1632 | # define SYS_CS_MUX_FQ4 0x6 | |
1633 | # define SYS_CS_MUX_FQ5 0x7 | |
1634 | #define SYS_CPUPLL 0xB1900060 | |
1635 | #define SYS_AUXPLL 0xB1900064 | |
1da177e4 LT |
1636 | |
1637 | /* AC97 Controller */ | |
ff6814d5 SS |
1638 | #define AC97C_CONFIG 0xB0000000 |
1639 | # define AC97C_RECV_SLOTS_BIT 13 | |
49a89efb | 1640 | # define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT) |
ff6814d5 | 1641 | # define AC97C_XMIT_SLOTS_BIT 3 |
49a89efb | 1642 | # define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT) |
ff6814d5 SS |
1643 | # define AC97C_SG (1 << 2) |
1644 | # define AC97C_SYNC (1 << 1) | |
1645 | # define AC97C_RESET (1 << 0) | |
1646 | #define AC97C_STATUS 0xB0000004 | |
1647 | # define AC97C_XU (1 << 11) | |
1648 | # define AC97C_XO (1 << 10) | |
1649 | # define AC97C_RU (1 << 9) | |
1650 | # define AC97C_RO (1 << 8) | |
1651 | # define AC97C_READY (1 << 7) | |
1652 | # define AC97C_CP (1 << 6) | |
1653 | # define AC97C_TR (1 << 5) | |
1654 | # define AC97C_TE (1 << 4) | |
1655 | # define AC97C_TF (1 << 3) | |
1656 | # define AC97C_RR (1 << 2) | |
1657 | # define AC97C_RE (1 << 1) | |
1658 | # define AC97C_RF (1 << 0) | |
1659 | #define AC97C_DATA 0xB0000008 | |
1660 | #define AC97C_CMD 0xB000000C | |
1661 | # define AC97C_WD_BIT 16 | |
1662 | # define AC97C_READ (1 << 7) | |
1663 | # define AC97C_INDEX_MASK 0x7f | |
1664 | #define AC97C_CNTRL 0xB0000010 | |
1665 | # define AC97C_RS (1 << 1) | |
1666 | # define AC97C_CE (1 << 0) | |
1da177e4 LT |
1667 | |
1668 | /* Secure Digital (SD) Controller */ | |
1669 | #define SD0_XMIT_FIFO 0xB0600000 | |
1670 | #define SD0_RECV_FIFO 0xB0600004 | |
1671 | #define SD1_XMIT_FIFO 0xB0680000 | |
1672 | #define SD1_RECV_FIFO 0xB0680004 | |
1673 | ||
49a89efb | 1674 | #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) |
1da177e4 | 1675 | /* Au1500 PCI Controller */ |
ff6814d5 SS |
1676 | #define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */ |
1677 | #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0) | |
1678 | #define Au1500_PCI_CFG (Au1500_CFG_BASE + 4) | |
1679 | # define PCI_ERROR ((1 << 22) | (1 << 23) | (1 << 24) | \ | |
1680 | (1 << 25) | (1 << 26) | (1 << 27)) | |
1681 | #define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8) | |
1682 | #define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC) | |
1683 | #define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10) | |
1684 | #define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14) | |
1da177e4 | 1685 | #define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18) |
ff6814d5 SS |
1686 | #define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C) |
1687 | #define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20) | |
1688 | #define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100) | |
1689 | #define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104) | |
1690 | #define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108) | |
1691 | #define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C) | |
1692 | #define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110) | |
1da177e4 | 1693 | |
ff6814d5 | 1694 | #define Au1500_PCI_HDR 0xB4005100 /* virtual, KSEG1 addr */ |
1da177e4 | 1695 | |
ff6814d5 SS |
1696 | /* |
1697 | * All of our structures, like PCI resource, have 32-bit members. | |
1da177e4 | 1698 | * Drivers are expected to do an ioremap on the PCI MEM resource, but it's |
ff6814d5 | 1699 | * hard to store 0x4 0000 0000 in a 32-bit type. We require a small patch |
1da177e4 | 1700 | * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and |
ff6814d5 SS |
1701 | * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM |
1702 | * addresses. For PCI I/O, it's simpler because we get to do the ioremap | |
1da177e4 LT |
1703 | * ourselves and then adjust the device's resources. |
1704 | */ | |
ff6814d5 SS |
1705 | #define Au1500_EXT_CFG 0x600000000ULL |
1706 | #define Au1500_EXT_CFG_TYPE1 0x680000000ULL | |
1707 | #define Au1500_PCI_IO_START 0x500000000ULL | |
1708 | #define Au1500_PCI_IO_END 0x5000FFFFFULL | |
1709 | #define Au1500_PCI_MEM_START 0x440000000ULL | |
1710 | #define Au1500_PCI_MEM_END 0x44FFFFFFFULL | |
1da177e4 | 1711 | |
dd99d966 SS |
1712 | #define PCI_IO_START 0x00001000 |
1713 | #define PCI_IO_END 0x000FFFFF | |
1714 | #define PCI_MEM_START 0x40000000 | |
1715 | #define PCI_MEM_END 0x4FFFFFFF | |
1716 | ||
ff6814d5 SS |
1717 | #define PCI_FIRST_DEVFN (0 << 3) |
1718 | #define PCI_LAST_DEVFN (19 << 3) | |
1da177e4 | 1719 | |
ff6814d5 SS |
1720 | #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */ |
1721 | #define IOPORT_RESOURCE_END 0xffffffff | |
1722 | #define IOMEM_RESOURCE_START 0x10000000 | |
1723 | #define IOMEM_RESOURCE_END 0xffffffff | |
1da177e4 | 1724 | |
e3ad1c23 | 1725 | #else /* Au1000 and Au1100 and Au1200 */ |
1da177e4 | 1726 | |
ff6814d5 SS |
1727 | /* Don't allow any legacy ports probing */ |
1728 | #define IOPORT_RESOURCE_START 0x10000000 | |
1729 | #define IOPORT_RESOURCE_END 0xffffffff | |
1730 | #define IOMEM_RESOURCE_START 0x10000000 | |
1731 | #define IOMEM_RESOURCE_END 0xffffffff | |
1da177e4 | 1732 | |
ff6814d5 SS |
1733 | #define PCI_IO_START 0 |
1734 | #define PCI_IO_END 0 | |
1735 | #define PCI_MEM_START 0 | |
1736 | #define PCI_MEM_END 0 | |
1da177e4 | 1737 | #define PCI_FIRST_DEVFN 0 |
ff6814d5 | 1738 | #define PCI_LAST_DEVFN 0 |
1da177e4 LT |
1739 | |
1740 | #endif | |
1741 | ||
e3ad1c23 | 1742 | #ifndef _LANGUAGE_ASSEMBLY |
ff6814d5 | 1743 | typedef volatile struct { |
e3ad1c23 PP |
1744 | /* 0x0000 */ u32 toytrim; |
1745 | /* 0x0004 */ u32 toywrite; | |
1746 | /* 0x0008 */ u32 toymatch0; | |
1747 | /* 0x000C */ u32 toymatch1; | |
1748 | /* 0x0010 */ u32 toymatch2; | |
1749 | /* 0x0014 */ u32 cntrctrl; | |
1750 | /* 0x0018 */ u32 scratch0; | |
1751 | /* 0x001C */ u32 scratch1; | |
1752 | /* 0x0020 */ u32 freqctrl0; | |
1753 | /* 0x0024 */ u32 freqctrl1; | |
1754 | /* 0x0028 */ u32 clksrc; | |
1755 | /* 0x002C */ u32 pinfunc; | |
1756 | /* 0x0030 */ u32 reserved0; | |
1757 | /* 0x0034 */ u32 wakemsk; | |
1758 | /* 0x0038 */ u32 endian; | |
1759 | /* 0x003C */ u32 powerctrl; | |
1760 | /* 0x0040 */ u32 toyread; | |
1761 | /* 0x0044 */ u32 rtctrim; | |
1762 | /* 0x0048 */ u32 rtcwrite; | |
1763 | /* 0x004C */ u32 rtcmatch0; | |
1764 | /* 0x0050 */ u32 rtcmatch1; | |
1765 | /* 0x0054 */ u32 rtcmatch2; | |
1766 | /* 0x0058 */ u32 rtcread; | |
1767 | /* 0x005C */ u32 wakesrc; | |
1768 | /* 0x0060 */ u32 cpupll; | |
1769 | /* 0x0064 */ u32 auxpll; | |
1770 | /* 0x0068 */ u32 reserved1; | |
1771 | /* 0x006C */ u32 reserved2; | |
1772 | /* 0x0070 */ u32 reserved3; | |
1773 | /* 0x0074 */ u32 reserved4; | |
1774 | /* 0x0078 */ u32 slppwr; | |
1775 | /* 0x007C */ u32 sleep; | |
1776 | /* 0x0080 */ u32 reserved5[32]; | |
1777 | /* 0x0100 */ u32 trioutrd; | |
1778 | #define trioutclr trioutrd | |
1779 | /* 0x0104 */ u32 reserved6; | |
1780 | /* 0x0108 */ u32 outputrd; | |
1781 | #define outputset outputrd | |
1782 | /* 0x010C */ u32 outputclr; | |
1783 | /* 0x0110 */ u32 pinstaterd; | |
1784 | #define pininputen pinstaterd | |
e3ad1c23 PP |
1785 | } AU1X00_SYS; |
1786 | ||
ff6814d5 | 1787 | static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE; |
e3ad1c23 PP |
1788 | |
1789 | #endif | |
ff6814d5 | 1790 | |
e3ad1c23 | 1791 | #endif |