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MIPS: Alchemy: Stop IRQ name sharing
[deliverable/linux.git] / arch / mips / include / asm / mach-au1x00 / au1000.h
CommitLineData
1da177e4
LT		 1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1k CPU.
5 *
01675095
SS		 6 * Copyright 2000-2001, 2006-2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30 /*
31 * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
32 */
33
34#ifndef _AU1000_H_
35#define _AU1000_H_
36
1da177e4
LT		 37
38#ifndef _LANGUAGE_ASSEMBLY
39
40#include <linux/delay.h>
786d7cdd 41#include <linux/types.h>
9d360ab4 42
ff6814d5
SS		 43#include <linux/io.h>
44#include <linux/irq.h>
1da177e4
LT		 45
46/* cpu pipeline flush */
47void static inline au_sync(void)
48{
49 __asm__ volatile ("sync");
50}
51
52void static inline au_sync_udelay(int us)
53{
54 __asm__ volatile ("sync");
55 udelay(us);
56}
57
58void static inline au_sync_delay(int ms)
59{
60 __asm__ volatile ("sync");
61 mdelay(ms);
62}
63
7de8d232 64void static inline au_writeb(u8 val, unsigned long reg)
1da177e4 65{
ff6814d5 66 *(volatile u8 *)reg = val;
1da177e4
LT		 67}
68
7de8d232 69void static inline au_writew(u16 val, unsigned long reg)
1da177e4 70{
ff6814d5 71 *(volatile u16 *)reg = val;
1da177e4
LT		 72}
73
7de8d232 74void static inline au_writel(u32 val, unsigned long reg)
1da177e4 75{
ff6814d5 76 *(volatile u32 *)reg = val;
1da177e4
LT		 77}
78
7de8d232 79static inline u8 au_readb(unsigned long reg)
1da177e4 80{
ff6814d5 81 return *(volatile u8 *)reg;
1da177e4
LT		 82}
83
7de8d232 84static inline u16 au_readw(unsigned long reg)
1da177e4 85{
ff6814d5 86 return *(volatile u16 *)reg;
1da177e4
LT		 87}
88
7de8d232 89static inline u32 au_readl(unsigned long reg)
1da177e4 90{
ff6814d5 91 return *(volatile u32 *)reg;
1da177e4
LT		 92}
93
074cf656
ML		 94/* Early Au1000 have a write-only SYS_CPUPLL register. */
95static inline int au1xxx_cpu_has_pll_wo(void)
96{
97 switch (read_c0_prid()) {
98 case 0x00030100: /* Au1000 DA */
99 case 0x00030201: /* Au1000 HA */
100 case 0x00030202: /* Au1000 HB */
101 return 1;
102 }
103 return 0;
104}
105
106/* does CPU need CONFIG[OD] set to fix tons of errata? */
107static inline int au1xxx_cpu_needs_config_od(void)
108{
109 /*
110 * c0_config.od (bit 19) was write only (and read as 0) on the
111 * early revisions of Alchemy SOCs. It disables the bus trans-
112 * action overlapping and needs to be set to fix various errata.
113 */
114 switch (read_c0_prid()) {
115 case 0x00030100: /* Au1000 DA */
116 case 0x00030201: /* Au1000 HA */
117 case 0x00030202: /* Au1000 HB */
118 case 0x01030200: /* Au1500 AB */
119 /*
120 * Au1100/Au1200 errata actually keep silence about this bit,
121 * so we set it just in case for those revisions that require
122 * it to be set according to the (now gone) cpu_table.
123 */
124 case 0x02030200: /* Au1100 AB */
125 case 0x02030201: /* Au1100 BA */
126 case 0x02030202: /* Au1100 BC */
127 case 0x04030201: /* Au1200 AC */
128 return 1;
129 }
130 return 0;
131}
1da177e4 132
93e9cd84
ML		 133#define ALCHEMY_CPU_UNKNOWN -1
134#define ALCHEMY_CPU_AU1000 0
135#define ALCHEMY_CPU_AU1500 1
136#define ALCHEMY_CPU_AU1100 2
137#define ALCHEMY_CPU_AU1550 3
138#define ALCHEMY_CPU_AU1200 4
139
140static inline int alchemy_get_cputype(void)
141{
142 switch (read_c0_prid() & 0xffff0000) {
143 case 0x00030000:
144 return ALCHEMY_CPU_AU1000;
145 break;
146 case 0x01030000:
147 return ALCHEMY_CPU_AU1500;
148 break;
149 case 0x02030000:
150 return ALCHEMY_CPU_AU1100;
151 break;
152 case 0x03030000:
153 return ALCHEMY_CPU_AU1550;
154 break;
155 case 0x04030000:
156 case 0x05030000:
157 return ALCHEMY_CPU_AU1200;
158 break;
159 }
160
161 return ALCHEMY_CPU_UNKNOWN;
162}
163
1da177e4
LT		 164/* arch/mips/au1000/common/clocks.c */
165extern void set_au1x00_speed(unsigned int new_freq);
166extern unsigned int get_au1x00_speed(void);
167extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
168extern unsigned long get_au1x00_uart_baud_base(void);
2699cdfb 169extern unsigned long au1xxx_calc_clock(void);
1da177e4 170
564365b0
ML		 171/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
172void au1xxx_save_and_sleep(void);
173void au_sleep(void);
174void save_au1xxx_intctl(void);
175void restore_au1xxx_intctl(void);
176
78814465
ML		 177
178/* SOC Interrupt numbers */
179
180#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
181#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
182#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1)
183#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
184#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
185
186enum soc_au1000_ints {
187 AU1000_FIRST_INT = AU1000_INTC0_INT_BASE,
188 AU1000_UART0_INT = AU1000_FIRST_INT,
189 AU1000_UART1_INT,
190 AU1000_UART2_INT,
191 AU1000_UART3_INT,
192 AU1000_SSI0_INT,
193 AU1000_SSI1_INT,
194 AU1000_DMA_INT_BASE,
195
196 AU1000_TOY_INT = AU1000_FIRST_INT + 14,
197 AU1000_TOY_MATCH0_INT,
198 AU1000_TOY_MATCH1_INT,
199 AU1000_TOY_MATCH2_INT,
200 AU1000_RTC_INT,
201 AU1000_RTC_MATCH0_INT,
202 AU1000_RTC_MATCH1_INT,
203 AU1000_RTC_MATCH2_INT,
204 AU1000_IRDA_TX_INT,
205 AU1000_IRDA_RX_INT,
206 AU1000_USB_DEV_REQ_INT,
207 AU1000_USB_DEV_SUS_INT,
208 AU1000_USB_HOST_INT,
209 AU1000_ACSYNC_INT,
210 AU1000_MAC0_DMA_INT,
211 AU1000_MAC1_DMA_INT,
212 AU1000_I2S_UO_INT,
213 AU1000_AC97C_INT,
214 AU1000_GPIO0_INT,
215 AU1000_GPIO1_INT,
216 AU1000_GPIO2_INT,
217 AU1000_GPIO3_INT,
218 AU1000_GPIO4_INT,
219 AU1000_GPIO5_INT,
220 AU1000_GPIO6_INT,
221 AU1000_GPIO7_INT,
222 AU1000_GPIO8_INT,
223 AU1000_GPIO9_INT,
224 AU1000_GPIO10_INT,
225 AU1000_GPIO11_INT,
226 AU1000_GPIO12_INT,
227 AU1000_GPIO13_INT,
228 AU1000_GPIO14_INT,
229 AU1000_GPIO15_INT,
230 AU1000_GPIO16_INT,
231 AU1000_GPIO17_INT,
232 AU1000_GPIO18_INT,
233 AU1000_GPIO19_INT,
234 AU1000_GPIO20_INT,
235 AU1000_GPIO21_INT,
236 AU1000_GPIO22_INT,
237 AU1000_GPIO23_INT,
238 AU1000_GPIO24_INT,
239 AU1000_GPIO25_INT,
240 AU1000_GPIO26_INT,
241 AU1000_GPIO27_INT,
242 AU1000_GPIO28_INT,
243 AU1000_GPIO29_INT,
244 AU1000_GPIO30_INT,
245 AU1000_GPIO31_INT,
246};
247
248enum soc_au1100_ints {
249 AU1100_FIRST_INT = AU1000_INTC0_INT_BASE,
250 AU1100_UART0_INT = AU1100_FIRST_INT,
251 AU1100_UART1_INT,
252 AU1100_SD_INT,
253 AU1100_UART3_INT,
254 AU1100_SSI0_INT,
255 AU1100_SSI1_INT,
256 AU1100_DMA_INT_BASE,
257
258 AU1100_TOY_INT = AU1100_FIRST_INT + 14,
259 AU1100_TOY_MATCH0_INT,
260 AU1100_TOY_MATCH1_INT,
261 AU1100_TOY_MATCH2_INT,
262 AU1100_RTC_INT,
263 AU1100_RTC_MATCH0_INT,
264 AU1100_RTC_MATCH1_INT,
265 AU1100_RTC_MATCH2_INT,
266 AU1100_IRDA_TX_INT,
267 AU1100_IRDA_RX_INT,
268 AU1100_USB_DEV_REQ_INT,
269 AU1100_USB_DEV_SUS_INT,
270 AU1100_USB_HOST_INT,
271 AU1100_ACSYNC_INT,
272 AU1100_MAC0_DMA_INT,
273 AU1100_GPIO208_215_INT,
274 AU1100_LCD_INT,
275 AU1100_AC97C_INT,
276 AU1100_GPIO0_INT,
277 AU1100_GPIO1_INT,
278 AU1100_GPIO2_INT,
279 AU1100_GPIO3_INT,
280 AU1100_GPIO4_INT,
281 AU1100_GPIO5_INT,
282 AU1100_GPIO6_INT,
283 AU1100_GPIO7_INT,
284 AU1100_GPIO8_INT,
285 AU1100_GPIO9_INT,
286 AU1100_GPIO10_INT,
287 AU1100_GPIO11_INT,
288 AU1100_GPIO12_INT,
289 AU1100_GPIO13_INT,
290 AU1100_GPIO14_INT,
291 AU1100_GPIO15_INT,
292 AU1100_GPIO16_INT,
293 AU1100_GPIO17_INT,
294 AU1100_GPIO18_INT,
295 AU1100_GPIO19_INT,
296 AU1100_GPIO20_INT,
297 AU1100_GPIO21_INT,
298 AU1100_GPIO22_INT,
299 AU1100_GPIO23_INT,
300 AU1100_GPIO24_INT,
301 AU1100_GPIO25_INT,
302 AU1100_GPIO26_INT,
303 AU1100_GPIO27_INT,
304 AU1100_GPIO28_INT,
305 AU1100_GPIO29_INT,
306 AU1100_GPIO30_INT,
307 AU1100_GPIO31_INT,
308};
309
310enum soc_au1500_ints {
311 AU1500_FIRST_INT = AU1000_INTC0_INT_BASE,
312 AU1500_UART0_INT = AU1500_FIRST_INT,
313 AU1500_PCI_INTA,
314 AU1500_PCI_INTB,
315 AU1500_UART3_INT,
316 AU1500_PCI_INTC,
317 AU1500_PCI_INTD,
318 AU1500_DMA_INT_BASE,
319
320 AU1500_TOY_INT = AU1500_FIRST_INT + 14,
321 AU1500_TOY_MATCH0_INT,
322 AU1500_TOY_MATCH1_INT,
323 AU1500_TOY_MATCH2_INT,
324 AU1500_RTC_INT,
325 AU1500_RTC_MATCH0_INT,
326 AU1500_RTC_MATCH1_INT,
327 AU1500_RTC_MATCH2_INT,
328 AU1500_PCI_ERR_INT,
329 AU1500_RESERVED_INT,
330 AU1500_USB_DEV_REQ_INT,
331 AU1500_USB_DEV_SUS_INT,
332 AU1500_USB_HOST_INT,
333 AU1500_ACSYNC_INT,
334 AU1500_MAC0_DMA_INT,
335 AU1500_MAC1_DMA_INT,
336 AU1500_AC97C_INT = AU1500_FIRST_INT + 31,
337 AU1500_GPIO0_INT,
338 AU1500_GPIO1_INT,
339 AU1500_GPIO2_INT,
340 AU1500_GPIO3_INT,
341 AU1500_GPIO4_INT,
342 AU1500_GPIO5_INT,
343 AU1500_GPIO6_INT,
344 AU1500_GPIO7_INT,
345 AU1500_GPIO8_INT,
346 AU1500_GPIO9_INT,
347 AU1500_GPIO10_INT,
348 AU1500_GPIO11_INT,
349 AU1500_GPIO12_INT,
350 AU1500_GPIO13_INT,
351 AU1500_GPIO14_INT,
352 AU1500_GPIO15_INT,
353 AU1500_GPIO200_INT,
354 AU1500_GPIO201_INT,
355 AU1500_GPIO202_INT,
356 AU1500_GPIO203_INT,
357 AU1500_GPIO20_INT,
358 AU1500_GPIO204_INT,
359 AU1500_GPIO205_INT,
360 AU1500_GPIO23_INT,
361 AU1500_GPIO24_INT,
362 AU1500_GPIO25_INT,
363 AU1500_GPIO26_INT,
364 AU1500_GPIO27_INT,
365 AU1500_GPIO28_INT,
366 AU1500_GPIO206_INT,
367 AU1500_GPIO207_INT,
368 AU1500_GPIO208_215_INT,
369};
370
371enum soc_au1550_ints {
372 AU1550_FIRST_INT = AU1000_INTC0_INT_BASE,
373 AU1550_UART0_INT = AU1550_FIRST_INT,
374 AU1550_PCI_INTA,
375 AU1550_PCI_INTB,
376 AU1550_DDMA_INT,
377 AU1550_CRYPTO_INT,
378 AU1550_PCI_INTC,
379 AU1550_PCI_INTD,
380 AU1550_PCI_RST_INT,
381 AU1550_UART1_INT,
382 AU1550_UART3_INT,
383 AU1550_PSC0_INT,
384 AU1550_PSC1_INT,
385 AU1550_PSC2_INT,
386 AU1550_PSC3_INT,
387 AU1550_TOY_INT,
388 AU1550_TOY_MATCH0_INT,
389 AU1550_TOY_MATCH1_INT,
390 AU1550_TOY_MATCH2_INT,
391 AU1550_RTC_INT,
392 AU1550_RTC_MATCH0_INT,
393 AU1550_RTC_MATCH1_INT,
394 AU1550_RTC_MATCH2_INT,
395
396 AU1550_NAND_INT = AU1550_FIRST_INT + 23,
397 AU1550_USB_DEV_REQ_INT,
398 AU1550_USB_DEV_SUS_INT,
399 AU1550_USB_HOST_INT,
400 AU1550_MAC0_DMA_INT,
401 AU1550_MAC1_DMA_INT,
402 AU1550_GPIO0_INT = AU1550_FIRST_INT + 32,
403 AU1550_GPIO1_INT,
404 AU1550_GPIO2_INT,
405 AU1550_GPIO3_INT,
406 AU1550_GPIO4_INT,
407 AU1550_GPIO5_INT,
408 AU1550_GPIO6_INT,
409 AU1550_GPIO7_INT,
410 AU1550_GPIO8_INT,
411 AU1550_GPIO9_INT,
412 AU1550_GPIO10_INT,
413 AU1550_GPIO11_INT,
414 AU1550_GPIO12_INT,
415 AU1550_GPIO13_INT,
416 AU1550_GPIO14_INT,
417 AU1550_GPIO15_INT,
418 AU1550_GPIO200_INT,
419 AU1550_GPIO201_205_INT, /* Logical or of GPIO201:205 */
420 AU1550_GPIO16_INT,
421 AU1550_GPIO17_INT,
422 AU1550_GPIO20_INT,
423 AU1550_GPIO21_INT,
424 AU1550_GPIO22_INT,
425 AU1550_GPIO23_INT,
426 AU1550_GPIO24_INT,
427 AU1550_GPIO25_INT,
428 AU1550_GPIO26_INT,
429 AU1550_GPIO27_INT,
430 AU1550_GPIO28_INT,
431 AU1550_GPIO206_INT,
432 AU1550_GPIO207_INT,
433 AU1550_GPIO208_215_INT, /* Logical or of GPIO208:215 */
434};
435
436enum soc_au1200_ints {
437 AU1200_FIRST_INT = AU1000_INTC0_INT_BASE,
438 AU1200_UART0_INT = AU1200_FIRST_INT,
439 AU1200_SWT_INT,
440 AU1200_SD_INT,
441 AU1200_DDMA_INT,
442 AU1200_MAE_BE_INT,
443 AU1200_GPIO200_INT,
444 AU1200_GPIO201_INT,
445 AU1200_GPIO202_INT,
446 AU1200_UART1_INT,
447 AU1200_MAE_FE_INT,
448 AU1200_PSC0_INT,
449 AU1200_PSC1_INT,
450 AU1200_AES_INT,
451 AU1200_CAMERA_INT,
452 AU1200_TOY_INT,
453 AU1200_TOY_MATCH0_INT,
454 AU1200_TOY_MATCH1_INT,
455 AU1200_TOY_MATCH2_INT,
456 AU1200_RTC_INT,
457 AU1200_RTC_MATCH0_INT,
458 AU1200_RTC_MATCH1_INT,
459 AU1200_RTC_MATCH2_INT,
460 AU1200_GPIO203_INT,
461 AU1200_NAND_INT,
462 AU1200_GPIO204_INT,
463 AU1200_GPIO205_INT,
464 AU1200_GPIO206_INT,
465 AU1200_GPIO207_INT,
466 AU1200_GPIO208_215_INT, /* Logical OR of 208:215 */
467 AU1200_USB_INT,
468 AU1200_LCD_INT,
469 AU1200_MAE_BOTH_INT,
470 AU1200_GPIO0_INT,
471 AU1200_GPIO1_INT,
472 AU1200_GPIO2_INT,
473 AU1200_GPIO3_INT,
474 AU1200_GPIO4_INT,
475 AU1200_GPIO5_INT,
476 AU1200_GPIO6_INT,
477 AU1200_GPIO7_INT,
478 AU1200_GPIO8_INT,
479 AU1200_GPIO9_INT,
480 AU1200_GPIO10_INT,
481 AU1200_GPIO11_INT,
482 AU1200_GPIO12_INT,
483 AU1200_GPIO13_INT,
484 AU1200_GPIO14_INT,
485 AU1200_GPIO15_INT,
486 AU1200_GPIO16_INT,
487 AU1200_GPIO17_INT,
488 AU1200_GPIO18_INT,
489 AU1200_GPIO19_INT,
490 AU1200_GPIO20_INT,
491 AU1200_GPIO21_INT,
492 AU1200_GPIO22_INT,
493 AU1200_GPIO23_INT,
494 AU1200_GPIO24_INT,
495 AU1200_GPIO25_INT,
496 AU1200_GPIO26_INT,
497 AU1200_GPIO27_INT,
498 AU1200_GPIO28_INT,
499 AU1200_GPIO29_INT,
500 AU1200_GPIO30_INT,
501 AU1200_GPIO31_INT,
502};
503
1da177e4
LT		 504#endif /* !defined (_LANGUAGE_ASSEMBLY) */
505
e3ad1c23 506/*
ff6814d5 507 * SDRAM register offsets
e3ad1c23 508 */
ff6814d5
SS		 509#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
510 defined(CONFIG_SOC_AU1100)
511#define MEM_SDMODE0 0x0000
512#define MEM_SDMODE1 0x0004
513#define MEM_SDMODE2 0x0008
514#define MEM_SDADDR0 0x000C
515#define MEM_SDADDR1 0x0010
516#define MEM_SDADDR2 0x0014
517#define MEM_SDREFCFG 0x0018
518#define MEM_SDPRECMD 0x001C
519#define MEM_SDAUTOREF 0x0020
520#define MEM_SDWRMD0 0x0024
521#define MEM_SDWRMD1 0x0028
522#define MEM_SDWRMD2 0x002C
523#define MEM_SDSLEEP 0x0030
524#define MEM_SDSMCKE 0x0034
e3ad1c23 525
e3ad1c23
PP		 526/*
527 * MEM_SDMODE register content definitions
528 */
ff6814d5
SS		 529#define MEM_SDMODE_F (1 << 22)
530#define MEM_SDMODE_SR (1 << 21)
531#define MEM_SDMODE_BS (1 << 20)
532#define MEM_SDMODE_RS (3 << 18)
533#define MEM_SDMODE_CS (7 << 15)
534#define MEM_SDMODE_TRAS (15 << 11)
535#define MEM_SDMODE_TMRD (3 << 9)
536#define MEM_SDMODE_TWR (3 << 7)
537#define MEM_SDMODE_TRP (3 << 5)
538#define MEM_SDMODE_TRCD (3 << 3)
539#define MEM_SDMODE_TCL (7 << 0)
540
541#define MEM_SDMODE_BS_2Bank (0 << 20)
542#define MEM_SDMODE_BS_4Bank (1 << 20)
543#define MEM_SDMODE_RS_11Row (0 << 18)
544#define MEM_SDMODE_RS_12Row (1 << 18)
545#define MEM_SDMODE_RS_13Row (2 << 18)
546#define MEM_SDMODE_RS_N(N) ((N) << 18)
547#define MEM_SDMODE_CS_7Col (0 << 15)
548#define MEM_SDMODE_CS_8Col (1 << 15)
549#define MEM_SDMODE_CS_9Col (2 << 15)
550#define MEM_SDMODE_CS_10Col (3 << 15)
551#define MEM_SDMODE_CS_11Col (4 << 15)
552#define MEM_SDMODE_CS_N(N) ((N) << 15)
553#define MEM_SDMODE_TRAS_N(N) ((N) << 11)
554#define MEM_SDMODE_TMRD_N(N) ((N) << 9)
555#define MEM_SDMODE_TWR_N(N) ((N) << 7)
556#define MEM_SDMODE_TRP_N(N) ((N) << 5)
557#define MEM_SDMODE_TRCD_N(N) ((N) << 3)
558#define MEM_SDMODE_TCL_N(N) ((N) << 0)
e3ad1c23
PP		 559
560/*
561 * MEM_SDADDR register contents definitions
562 */
ff6814d5
SS		 563#define MEM_SDADDR_E (1 << 20)
564#define MEM_SDADDR_CSBA (0x03FF << 10)
565#define MEM_SDADDR_CSMASK (0x03FF << 0)
566#define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
567#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
e3ad1c23
PP		 568
569/*
570 * MEM_SDREFCFG register content definitions
571 */
ff6814d5
SS		 572#define MEM_SDREFCFG_TRC (15 << 28)
573#define MEM_SDREFCFG_TRPM (3 << 26)
574#define MEM_SDREFCFG_E (1 << 25)
575#define MEM_SDREFCFG_RE (0x1ffffff << 0)
576#define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC)
577#define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM)
e3ad1c23
PP		 578#define MEM_SDREFCFG_REF_N(N) (N)
579#endif
1da177e4 580
e3ad1c23 581/***********************************************************************/
1da177e4 582
e3ad1c23
PP		 583/*
584 * Au1550 SDRAM Register Offsets
585 */
1da177e4 586
e3ad1c23 587/***********************************************************************/
1da177e4 588
e3ad1c23 589#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
ff6814d5
SS		 590#define MEM_SDMODE0 0x0800
591#define MEM_SDMODE1 0x0808
592#define MEM_SDMODE2 0x0810
593#define MEM_SDADDR0 0x0820
594#define MEM_SDADDR1 0x0828
595#define MEM_SDADDR2 0x0830
596#define MEM_SDCONFIGA 0x0840
597#define MEM_SDCONFIGB 0x0848
598#define MEM_SDSTAT 0x0850
599#define MEM_SDERRADDR 0x0858
600#define MEM_SDSTRIDE0 0x0860
601#define MEM_SDSTRIDE1 0x0868
602#define MEM_SDSTRIDE2 0x0870
603#define MEM_SDWRMD0 0x0880
604#define MEM_SDWRMD1 0x0888
605#define MEM_SDWRMD2 0x0890
606#define MEM_SDPRECMD 0x08C0
607#define MEM_SDAUTOREF 0x08C8
608#define MEM_SDSREF 0x08D0
e3ad1c23
PP		 609#define MEM_SDSLEEP MEM_SDSREF
610
e3ad1c23
PP		 611#endif
612
613/*
614 * Physical base addresses for integrated peripherals
615 */
616
617#ifdef CONFIG_SOC_AU1000
618#define MEM_PHYS_ADDR 0x14000000
619#define STATIC_MEM_PHYS_ADDR 0x14001000
620#define DMA0_PHYS_ADDR 0x14002000
621#define DMA1_PHYS_ADDR 0x14002100
622#define DMA2_PHYS_ADDR 0x14002200
623#define DMA3_PHYS_ADDR 0x14002300
624#define DMA4_PHYS_ADDR 0x14002400
625#define DMA5_PHYS_ADDR 0x14002500
626#define DMA6_PHYS_ADDR 0x14002600
627#define DMA7_PHYS_ADDR 0x14002700
628#define IC0_PHYS_ADDR 0x10400000
629#define IC1_PHYS_ADDR 0x11800000
630#define AC97_PHYS_ADDR 0x10000000
631#define USBH_PHYS_ADDR 0x10100000
632#define USBD_PHYS_ADDR 0x10200000
633#define IRDA_PHYS_ADDR 0x10300000
634#define MAC0_PHYS_ADDR 0x10500000
635#define MAC1_PHYS_ADDR 0x10510000
636#define MACEN_PHYS_ADDR 0x10520000
637#define MACDMA0_PHYS_ADDR 0x14004000
638#define MACDMA1_PHYS_ADDR 0x14004200
639#define I2S_PHYS_ADDR 0x11000000
640#define UART0_PHYS_ADDR 0x11100000
641#define UART1_PHYS_ADDR 0x11200000
642#define UART2_PHYS_ADDR 0x11300000
643#define UART3_PHYS_ADDR 0x11400000
644#define SSI0_PHYS_ADDR 0x11600000
645#define SSI1_PHYS_ADDR 0x11680000
646#define SYS_PHYS_ADDR 0x11900000
ff6814d5
SS		 647#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
648#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
649#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
e3ad1c23
PP		 650#endif
651
652/********************************************************************/
653
654#ifdef CONFIG_SOC_AU1500
655#define MEM_PHYS_ADDR 0x14000000
656#define STATIC_MEM_PHYS_ADDR 0x14001000
657#define DMA0_PHYS_ADDR 0x14002000
658#define DMA1_PHYS_ADDR 0x14002100
659#define DMA2_PHYS_ADDR 0x14002200
660#define DMA3_PHYS_ADDR 0x14002300
661#define DMA4_PHYS_ADDR 0x14002400
662#define DMA5_PHYS_ADDR 0x14002500
663#define DMA6_PHYS_ADDR 0x14002600
664#define DMA7_PHYS_ADDR 0x14002700
665#define IC0_PHYS_ADDR 0x10400000
666#define IC1_PHYS_ADDR 0x11800000
667#define AC97_PHYS_ADDR 0x10000000
668#define USBH_PHYS_ADDR 0x10100000
669#define USBD_PHYS_ADDR 0x10200000
670#define PCI_PHYS_ADDR 0x14005000
671#define MAC0_PHYS_ADDR 0x11500000
672#define MAC1_PHYS_ADDR 0x11510000
673#define MACEN_PHYS_ADDR 0x11520000
674#define MACDMA0_PHYS_ADDR 0x14004000
675#define MACDMA1_PHYS_ADDR 0x14004200
676#define I2S_PHYS_ADDR 0x11000000
677#define UART0_PHYS_ADDR 0x11100000
678#define UART3_PHYS_ADDR 0x11400000
679#define GPIO2_PHYS_ADDR 0x11700000
680#define SYS_PHYS_ADDR 0x11900000
ff6814d5
SS		 681#define PCI_MEM_PHYS_ADDR 0x400000000ULL
682#define PCI_IO_PHYS_ADDR 0x500000000ULL
683#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
684#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
685#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
686#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
687#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
e3ad1c23
PP		 688#endif
689
690/********************************************************************/
691
692#ifdef CONFIG_SOC_AU1100
693#define MEM_PHYS_ADDR 0x14000000
694#define STATIC_MEM_PHYS_ADDR 0x14001000
695#define DMA0_PHYS_ADDR 0x14002000
696#define DMA1_PHYS_ADDR 0x14002100
697#define DMA2_PHYS_ADDR 0x14002200
698#define DMA3_PHYS_ADDR 0x14002300
699#define DMA4_PHYS_ADDR 0x14002400
700#define DMA5_PHYS_ADDR 0x14002500
701#define DMA6_PHYS_ADDR 0x14002600
702#define DMA7_PHYS_ADDR 0x14002700
703#define IC0_PHYS_ADDR 0x10400000
704#define SD0_PHYS_ADDR 0x10600000
705#define SD1_PHYS_ADDR 0x10680000
706#define IC1_PHYS_ADDR 0x11800000
707#define AC97_PHYS_ADDR 0x10000000
708#define USBH_PHYS_ADDR 0x10100000
709#define USBD_PHYS_ADDR 0x10200000
710#define IRDA_PHYS_ADDR 0x10300000
711#define MAC0_PHYS_ADDR 0x10500000
712#define MACEN_PHYS_ADDR 0x10520000
713#define MACDMA0_PHYS_ADDR 0x14004000
714#define MACDMA1_PHYS_ADDR 0x14004200
715#define I2S_PHYS_ADDR 0x11000000
716#define UART0_PHYS_ADDR 0x11100000
717#define UART1_PHYS_ADDR 0x11200000
718#define UART3_PHYS_ADDR 0x11400000
719#define SSI0_PHYS_ADDR 0x11600000
720#define SSI1_PHYS_ADDR 0x11680000
721#define GPIO2_PHYS_ADDR 0x11700000
722#define SYS_PHYS_ADDR 0x11900000
723#define LCD_PHYS_ADDR 0x15000000
ff6814d5
SS		 724#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
725#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
726#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
e3ad1c23
PP		 727#endif
728
729/***********************************************************************/
730
731#ifdef CONFIG_SOC_AU1550
732#define MEM_PHYS_ADDR 0x14000000
733#define STATIC_MEM_PHYS_ADDR 0x14001000
734#define IC0_PHYS_ADDR 0x10400000
735#define IC1_PHYS_ADDR 0x11800000
736#define USBH_PHYS_ADDR 0x14020000
737#define USBD_PHYS_ADDR 0x10200000
738#define PCI_PHYS_ADDR 0x14005000
739#define MAC0_PHYS_ADDR 0x10500000
740#define MAC1_PHYS_ADDR 0x10510000
741#define MACEN_PHYS_ADDR 0x10520000
742#define MACDMA0_PHYS_ADDR 0x14004000
743#define MACDMA1_PHYS_ADDR 0x14004200
744#define UART0_PHYS_ADDR 0x11100000
745#define UART1_PHYS_ADDR 0x11200000
746#define UART3_PHYS_ADDR 0x11400000
747#define GPIO2_PHYS_ADDR 0x11700000
748#define SYS_PHYS_ADDR 0x11900000
749#define DDMA_PHYS_ADDR 0x14002000
750#define PE_PHYS_ADDR 0x14008000
ff6814d5
SS		 751#define PSC0_PHYS_ADDR 0x11A00000
752#define PSC1_PHYS_ADDR 0x11B00000
753#define PSC2_PHYS_ADDR 0x10A00000
754#define PSC3_PHYS_ADDR 0x10B00000
755#define PCI_MEM_PHYS_ADDR 0x400000000ULL
756#define PCI_IO_PHYS_ADDR 0x500000000ULL
757#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
758#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
759#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
760#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
761#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
e3ad1c23
PP		 762#endif
763
764/***********************************************************************/
765
766#ifdef CONFIG_SOC_AU1200
767#define MEM_PHYS_ADDR 0x14000000
768#define STATIC_MEM_PHYS_ADDR 0x14001000
769#define AES_PHYS_ADDR 0x10300000
770#define CIM_PHYS_ADDR 0x14004000
771#define IC0_PHYS_ADDR 0x10400000
772#define IC1_PHYS_ADDR 0x11800000
773#define USBM_PHYS_ADDR 0x14020000
774#define USBH_PHYS_ADDR 0x14020100
775#define UART0_PHYS_ADDR 0x11100000
776#define UART1_PHYS_ADDR 0x11200000
777#define GPIO2_PHYS_ADDR 0x11700000
778#define SYS_PHYS_ADDR 0x11900000
779#define DDMA_PHYS_ADDR 0x14002000
780#define PSC0_PHYS_ADDR 0x11A00000
781#define PSC1_PHYS_ADDR 0x11B00000
e3ad1c23
PP		 782#define SD0_PHYS_ADDR 0x10600000
783#define SD1_PHYS_ADDR 0x10680000
784#define LCD_PHYS_ADDR 0x15000000
785#define SWCNT_PHYS_ADDR 0x1110010C
786#define MAEFE_PHYS_ADDR 0x14012000
787#define MAEBE_PHYS_ADDR 0x14010000
ff6814d5
SS		 788#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
789#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
790#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
e3ad1c23
PP		 791#endif
792
1da177e4 793/* Static Bus Controller */
ff6814d5
SS		 794#define MEM_STCFG0 0xB4001000
795#define MEM_STTIME0 0xB4001004
796#define MEM_STADDR0 0xB4001008
1da177e4 797
ff6814d5
SS		 798#define MEM_STCFG1 0xB4001010
799#define MEM_STTIME1 0xB4001014
800#define MEM_STADDR1 0xB4001018
1da177e4 801
ff6814d5
SS		 802#define MEM_STCFG2 0xB4001020
803#define MEM_STTIME2 0xB4001024
804#define MEM_STADDR2 0xB4001028
1da177e4 805
ff6814d5
SS		 806#define MEM_STCFG3 0xB4001030
807#define MEM_STTIME3 0xB4001034
808#define MEM_STADDR3 0xB4001038
1da177e4
LT		 809
810#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
ff6814d5
SS		 811#define MEM_STNDCTL 0xB4001100
812#define MEM_STSTAT 0xB4001104
1da177e4 813
ff6814d5
SS		 814#define MEM_STNAND_CMD 0x0
815#define MEM_STNAND_ADDR 0x4
816#define MEM_STNAND_DATA 0x20
1da177e4
LT		 817#endif
818
819/* Interrupt Controller 0 */
ff6814d5
SS		 820#define IC0_CFG0RD 0xB0400040
821#define IC0_CFG0SET 0xB0400040
822#define IC0_CFG0CLR 0xB0400044
1da177e4 823
ff6814d5
SS		 824#define IC0_CFG1RD 0xB0400048
825#define IC0_CFG1SET 0xB0400048
826#define IC0_CFG1CLR 0xB040004C
1da177e4 827
ff6814d5
SS		 828#define IC0_CFG2RD 0xB0400050
829#define IC0_CFG2SET 0xB0400050
830#define IC0_CFG2CLR 0xB0400054
1da177e4 831
ff6814d5
SS		 832#define IC0_REQ0INT 0xB0400054
833#define IC0_SRCRD 0xB0400058
834#define IC0_SRCSET 0xB0400058
835#define IC0_SRCCLR 0xB040005C
836#define IC0_REQ1INT 0xB040005C
1da177e4 837
ff6814d5
SS		 838#define IC0_ASSIGNRD 0xB0400060
839#define IC0_ASSIGNSET 0xB0400060
840#define IC0_ASSIGNCLR 0xB0400064
1da177e4 841
ff6814d5
SS		 842#define IC0_WAKERD 0xB0400068
843#define IC0_WAKESET 0xB0400068
844#define IC0_WAKECLR 0xB040006C
1da177e4 845
ff6814d5
SS		 846#define IC0_MASKRD 0xB0400070
847#define IC0_MASKSET 0xB0400070
848#define IC0_MASKCLR 0xB0400074
1da177e4 849
ff6814d5
SS		 850#define IC0_RISINGRD 0xB0400078
851#define IC0_RISINGCLR 0xB0400078
852#define IC0_FALLINGRD 0xB040007C
853#define IC0_FALLINGCLR 0xB040007C
1da177e4 854
ff6814d5 855#define IC0_TESTBIT 0xB0400080
1da177e4
LT		 856
857/* Interrupt Controller 1 */
ff6814d5
SS		 858#define IC1_CFG0RD 0xB1800040
859#define IC1_CFG0SET 0xB1800040
860#define IC1_CFG0CLR 0xB1800044
1da177e4 861
ff6814d5
SS		 862#define IC1_CFG1RD 0xB1800048
863#define IC1_CFG1SET 0xB1800048
864#define IC1_CFG1CLR 0xB180004C
1da177e4 865
ff6814d5
SS		 866#define IC1_CFG2RD 0xB1800050
867#define IC1_CFG2SET 0xB1800050
868#define IC1_CFG2CLR 0xB1800054
1da177e4 869
ff6814d5
SS		 870#define IC1_REQ0INT 0xB1800054
871#define IC1_SRCRD 0xB1800058
872#define IC1_SRCSET 0xB1800058
873#define IC1_SRCCLR 0xB180005C
874#define IC1_REQ1INT 0xB180005C
1da177e4 875
ff6814d5
SS		 876#define IC1_ASSIGNRD 0xB1800060
877#define IC1_ASSIGNSET 0xB1800060
878#define IC1_ASSIGNCLR 0xB1800064
1da177e4 879
ff6814d5
SS		 880#define IC1_WAKERD 0xB1800068
881#define IC1_WAKESET 0xB1800068
882#define IC1_WAKECLR 0xB180006C
1da177e4 883
ff6814d5
SS		 884#define IC1_MASKRD 0xB1800070
885#define IC1_MASKSET 0xB1800070
886#define IC1_MASKCLR 0xB1800074
1da177e4 887
ff6814d5
SS		 888#define IC1_RISINGRD 0xB1800078
889#define IC1_RISINGCLR 0xB1800078
890#define IC1_FALLINGRD 0xB180007C
891#define IC1_FALLINGCLR 0xB180007C
1da177e4 892
ff6814d5 893#define IC1_TESTBIT 0xB1800080
1da177e4 894
78814465 895
1da177e4
LT		 896/* Au1000 */
897#ifdef CONFIG_SOC_AU1000
1da177e4 898
ff6814d5
SS		 899#define UART0_ADDR 0xB1100000
900#define UART1_ADDR 0xB1200000
901#define UART2_ADDR 0xB1300000
902#define UART3_ADDR 0xB1400000
1da177e4 903
ff6814d5
SS		 904#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
905#define USB_HOST_CONFIG 0xB017FFFC
78814465 906#define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT
1da177e4 907
ff6814d5
SS		 908#define AU1000_ETH0_BASE 0xB0500000
909#define AU1000_ETH1_BASE 0xB0510000
910#define AU1000_MAC0_ENABLE 0xB0520000
911#define AU1000_MAC1_ENABLE 0xB0520004
1da177e4 912#define NUM_ETH_INTERFACES 2
e3ad1c23 913#endif /* CONFIG_SOC_AU1000 */
1da177e4
LT		 914
915/* Au1500 */
916#ifdef CONFIG_SOC_AU1500
2d32ffa4 917
ff6814d5
SS		 918#define UART0_ADDR 0xB1100000
919#define UART3_ADDR 0xB1400000
1da177e4 920
ff6814d5
SS		 921#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
922#define USB_HOST_CONFIG 0xB017fffc
78814465 923#define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT
1da177e4 924
ff6814d5
SS		 925#define AU1500_ETH0_BASE 0xB1500000
926#define AU1500_ETH1_BASE 0xB1510000
927#define AU1500_MAC0_ENABLE 0xB1520000
928#define AU1500_MAC1_ENABLE 0xB1520004
1da177e4 929#define NUM_ETH_INTERFACES 2
e3ad1c23 930#endif /* CONFIG_SOC_AU1500 */
1da177e4
LT		 931
932/* Au1100 */
933#ifdef CONFIG_SOC_AU1100
1da177e4 934
ff6814d5
SS		 935#define UART0_ADDR 0xB1100000
936#define UART1_ADDR 0xB1200000
937#define UART3_ADDR 0xB1400000
1da177e4 938
ff6814d5
SS		 939#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
940#define USB_HOST_CONFIG 0xB017FFFC
78814465 941#define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT
1da177e4 942
ff6814d5
SS		 943#define AU1100_ETH0_BASE 0xB0500000
944#define AU1100_MAC0_ENABLE 0xB0520000
1da177e4 945#define NUM_ETH_INTERFACES 1
e3ad1c23 946#endif /* CONFIG_SOC_AU1100 */
1da177e4
LT		 947
948#ifdef CONFIG_SOC_AU1550
ff6814d5
SS		 949#define UART0_ADDR 0xB1100000
950#define UART1_ADDR 0xB1200000
951#define UART3_ADDR 0xB1400000
1da177e4 952
ff6814d5
SS		 953#define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */
954#define USB_OHCI_LEN 0x00060000
955#define USB_HOST_CONFIG 0xB4027ffc
78814465 956#define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT
1da177e4 957
ff6814d5
SS		 958#define AU1550_ETH0_BASE 0xB0500000
959#define AU1550_ETH1_BASE 0xB0510000
960#define AU1550_MAC0_ENABLE 0xB0520000
961#define AU1550_MAC1_ENABLE 0xB0520004
1da177e4 962#define NUM_ETH_INTERFACES 2
e3ad1c23 963#endif /* CONFIG_SOC_AU1550 */
1da177e4 964
78814465 965
1da177e4 966#ifdef CONFIG_SOC_AU1200
1da177e4 967
ff6814d5
SS		 968#define UART0_ADDR 0xB1100000
969#define UART1_ADDR 0xB1200000
970
971#define USB_UOC_BASE 0x14020020
972#define USB_UOC_LEN 0x20
973#define USB_OHCI_BASE 0x14020100
974#define USB_OHCI_LEN 0x100
975#define USB_EHCI_BASE 0x14020200
976#define USB_EHCI_LEN 0x100
977#define USB_UDC_BASE 0x14022000
978#define USB_UDC_LEN 0x2000
979#define USB_MSR_BASE 0xB4020000
980#define USB_MSR_MCFG 4
981#define USBMSRMCFG_OMEMEN 0
982#define USBMSRMCFG_OBMEN 1
983#define USBMSRMCFG_EMEMEN 2
984#define USBMSRMCFG_EBMEN 3
985#define USBMSRMCFG_DMEMEN 4
986#define USBMSRMCFG_DBMEN 5
987#define USBMSRMCFG_GMEMEN 6
988#define USBMSRMCFG_OHCCLKEN 16
989#define USBMSRMCFG_EHCCLKEN 17
990#define USBMSRMCFG_UDCCLKEN 18
991#define USBMSRMCFG_PHYPLLEN 19
992#define USBMSRMCFG_RDCOMB 30
993#define USBMSRMCFG_PFEN 31
e3ad1c23 994
78814465 995#define FOR_PLATFORM_C_USB_HOST_INT AU1200_USB_INT
1da177e4 996
78814465 997#endif /* CONFIG_SOC_AU1200 */
1da177e4 998
1da177e4 999/* Programmable Counters 0 and 1 */
ff6814d5
SS		 1000#define SYS_BASE 0xB1900000
1001#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
1002# define SYS_CNTRL_E1S (1 << 23)
1003# define SYS_CNTRL_T1S (1 << 20)
1004# define SYS_CNTRL_M21 (1 << 19)
1005# define SYS_CNTRL_M11 (1 << 18)
1006# define SYS_CNTRL_M01 (1 << 17)
1007# define SYS_CNTRL_C1S (1 << 16)
1008# define SYS_CNTRL_BP (1 << 14)
1009# define SYS_CNTRL_EN1 (1 << 13)
1010# define SYS_CNTRL_BT1 (1 << 12)
1011# define SYS_CNTRL_EN0 (1 << 11)
1012# define SYS_CNTRL_BT0 (1 << 10)
1013# define SYS_CNTRL_E0 (1 << 8)
1014# define SYS_CNTRL_E0S (1 << 7)
1015# define SYS_CNTRL_32S (1 << 5)
1016# define SYS_CNTRL_T0S (1 << 4)
1017# define SYS_CNTRL_M20 (1 << 3)
1018# define SYS_CNTRL_M10 (1 << 2)
1019# define SYS_CNTRL_M00 (1 << 1)
1020# define SYS_CNTRL_C0S (1 << 0)
1da177e4
LT		 1021
1022/* Programmable Counter 0 Registers */
ff6814d5
SS		 1023#define SYS_TOYTRIM (SYS_BASE + 0)
1024#define SYS_TOYWRITE (SYS_BASE + 4)
1025#define SYS_TOYMATCH0 (SYS_BASE + 8)
1026#define SYS_TOYMATCH1 (SYS_BASE + 0xC)
1027#define SYS_TOYMATCH2 (SYS_BASE + 0x10)
1028#define SYS_TOYREAD (SYS_BASE + 0x40)
1da177e4
LT		 1029
1030/* Programmable Counter 1 Registers */
ff6814d5
SS		 1031#define SYS_RTCTRIM (SYS_BASE + 0x44)
1032#define SYS_RTCWRITE (SYS_BASE + 0x48)
1033#define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
1034#define SYS_RTCMATCH1 (SYS_BASE + 0x50)
1035#define SYS_RTCMATCH2 (SYS_BASE + 0x54)
1036#define SYS_RTCREAD (SYS_BASE + 0x58)
1da177e4
LT		 1037
1038/* I2S Controller */
ff6814d5
SS		 1039#define I2S_DATA 0xB1000000
1040# define I2S_DATA_MASK 0xffffff
1041#define I2S_CONFIG 0xB1000004
1042# define I2S_CONFIG_XU (1 << 25)
1043# define I2S_CONFIG_XO (1 << 24)
1044# define I2S_CONFIG_RU (1 << 23)
1045# define I2S_CONFIG_RO (1 << 22)
1046# define I2S_CONFIG_TR (1 << 21)
1047# define I2S_CONFIG_TE (1 << 20)
1048# define I2S_CONFIG_TF (1 << 19)
1049# define I2S_CONFIG_RR (1 << 18)
1050# define I2S_CONFIG_RE (1 << 17)
1051# define I2S_CONFIG_RF (1 << 16)
1052# define I2S_CONFIG_PD (1 << 11)
1053# define I2S_CONFIG_LB (1 << 10)
1054# define I2S_CONFIG_IC (1 << 9)
1055# define I2S_CONFIG_FM_BIT 7
1056# define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
1057# define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
1058# define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
1059# define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
1060# define I2S_CONFIG_TN (1 << 6)
1061# define I2S_CONFIG_RN (1 << 5)
1062# define I2S_CONFIG_SZ_BIT 0
1063# define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
1064
1065#define I2S_CONTROL 0xB1000008
1066# define I2S_CONTROL_D (1 << 1)
1067# define I2S_CONTROL_CE (1 << 0)
1da177e4
LT		 1068
1069/* USB Host Controller */
c5c64e22 1070#ifndef USB_OHCI_LEN
ff6814d5 1071#define USB_OHCI_LEN 0x00100000
c5c64e22
SS		 1072#endif
1073
1074#ifndef CONFIG_SOC_AU1200
1da177e4
LT		 1075
1076/* USB Device Controller */
ff6814d5
SS		 1077#define USBD_EP0RD 0xB0200000
1078#define USBD_EP0WR 0xB0200004
1079#define USBD_EP2WR 0xB0200008
1080#define USBD_EP3WR 0xB020000C
1081#define USBD_EP4RD 0xB0200010
1082#define USBD_EP5RD 0xB0200014
1083#define USBD_INTEN 0xB0200018
1084#define USBD_INTSTAT 0xB020001C
1085# define USBDEV_INT_SOF (1 << 12)
1086# define USBDEV_INT_HF_BIT 6
25829b0e 1087# define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
ff6814d5 1088# define USBDEV_INT_CMPLT_BIT 0
49a89efb 1089# define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
ff6814d5
SS		 1090#define USBD_CONFIG 0xB0200020
1091#define USBD_EP0CS 0xB0200024
1092#define USBD_EP2CS 0xB0200028
1093#define USBD_EP3CS 0xB020002C
1094#define USBD_EP4CS 0xB0200030
1095#define USBD_EP5CS 0xB0200034
1096# define USBDEV_CS_SU (1 << 14)
1097# define USBDEV_CS_NAK (1 << 13)
1098# define USBDEV_CS_ACK (1 << 12)
1099# define USBDEV_CS_BUSY (1 << 11)
1100# define USBDEV_CS_TSIZE_BIT 1
1101# define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
1102# define USBDEV_CS_STALL (1 << 0)
1103#define USBD_EP0RDSTAT 0xB0200040
1104#define USBD_EP0WRSTAT 0xB0200044
1105#define USBD_EP2WRSTAT 0xB0200048
1106#define USBD_EP3WRSTAT 0xB020004C
1107#define USBD_EP4RDSTAT 0xB0200050
1108#define USBD_EP5RDSTAT 0xB0200054
1109# define USBDEV_FSTAT_FLUSH (1 << 6)
1110# define USBDEV_FSTAT_UF (1 << 5)
1111# define USBDEV_FSTAT_OF (1 << 4)
1112# define USBDEV_FSTAT_FCNT_BIT 0
49a89efb 1113# define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
ff6814d5
SS		 1114#define USBD_ENABLE 0xB0200058
1115# define USBDEV_ENABLE (1 << 1)
1116# define USBDEV_CE (1 << 0)
1da177e4 1117
e3ad1c23
PP		 1118#endif /* !CONFIG_SOC_AU1200 */
1119
1da177e4
LT		 1120/* Ethernet Controllers */
1121
1122/* 4 byte offsets from AU1000_ETH_BASE */
ff6814d5
SS		 1123#define MAC_CONTROL 0x0
1124# define MAC_RX_ENABLE (1 << 2)
1125# define MAC_TX_ENABLE (1 << 3)
1126# define MAC_DEF_CHECK (1 << 5)
1127# define MAC_SET_BL(X) (((X) & 0x3) << 6)
1128# define MAC_AUTO_PAD (1 << 8)
1129# define MAC_DISABLE_RETRY (1 << 10)
1130# define MAC_DISABLE_BCAST (1 << 11)
1131# define MAC_LATE_COL (1 << 12)
1132# define MAC_HASH_MODE (1 << 13)
1133# define MAC_HASH_ONLY (1 << 15)
1134# define MAC_PASS_ALL (1 << 16)
1135# define MAC_INVERSE_FILTER (1 << 17)
1136# define MAC_PROMISCUOUS (1 << 18)
1137# define MAC_PASS_ALL_MULTI (1 << 19)
1138# define MAC_FULL_DUPLEX (1 << 20)
1139# define MAC_NORMAL_MODE 0
1140# define MAC_INT_LOOPBACK (1 << 21)
1141# define MAC_EXT_LOOPBACK (1 << 22)
1142# define MAC_DISABLE_RX_OWN (1 << 23)
1143# define MAC_BIG_ENDIAN (1 << 30)
1144# define MAC_RX_ALL (1 << 31)
1145#define MAC_ADDRESS_HIGH 0x4
1146#define MAC_ADDRESS_LOW 0x8
1147#define MAC_MCAST_HIGH 0xC
1148#define MAC_MCAST_LOW 0x10
1149#define MAC_MII_CNTRL 0x14
1150# define MAC_MII_BUSY (1 << 0)
1151# define MAC_MII_READ 0
1152# define MAC_MII_WRITE (1 << 1)
1153# define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
1154# define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
1155#define MAC_MII_DATA 0x18
1156#define MAC_FLOW_CNTRL 0x1C
1157# define MAC_FLOW_CNTRL_BUSY (1 << 0)
1158# define MAC_FLOW_CNTRL_ENABLE (1 << 1)
1159# define MAC_PASS_CONTROL (1 << 2)
1160# define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16)
1161#define MAC_VLAN1_TAG 0x20
1162#define MAC_VLAN2_TAG 0x24
1da177e4
LT		 1163
1164/* Ethernet Controller Enable */
1165
ff6814d5
SS		 1166# define MAC_EN_CLOCK_ENABLE (1 << 0)
1167# define MAC_EN_RESET0 (1 << 1)
1168# define MAC_EN_TOSS (0 << 2)
1169# define MAC_EN_CACHEABLE (1 << 3)
1170# define MAC_EN_RESET1 (1 << 4)
1171# define MAC_EN_RESET2 (1 << 5)
1172# define MAC_DMA_RESET (1 << 6)
1da177e4
LT		 1173
1174/* Ethernet Controller DMA Channels */
1175
ff6814d5
SS		 1176#define MAC0_TX_DMA_ADDR 0xB4004000
1177#define MAC1_TX_DMA_ADDR 0xB4004200
1da177e4 1178/* offsets from MAC_TX_RING_ADDR address */
ff6814d5
SS		 1179#define MAC_TX_BUFF0_STATUS 0x0
1180# define TX_FRAME_ABORTED (1 << 0)
1181# define TX_JAB_TIMEOUT (1 << 1)
1182# define TX_NO_CARRIER (1 << 2)
1183# define TX_LOSS_CARRIER (1 << 3)
1184# define TX_EXC_DEF (1 << 4)
1185# define TX_LATE_COLL_ABORT (1 << 5)
1186# define TX_EXC_COLL (1 << 6)
1187# define TX_UNDERRUN (1 << 7)
1188# define TX_DEFERRED (1 << 8)
1189# define TX_LATE_COLL (1 << 9)
1190# define TX_COLL_CNT_MASK (0xF << 10)
1191# define TX_PKT_RETRY (1 << 31)
1192#define MAC_TX_BUFF0_ADDR 0x4
1193# define TX_DMA_ENABLE (1 << 0)
1194# define TX_T_DONE (1 << 1)
1195# define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1196#define MAC_TX_BUFF0_LEN 0x8
1197#define MAC_TX_BUFF1_STATUS 0x10
1198#define MAC_TX_BUFF1_ADDR 0x14
1199#define MAC_TX_BUFF1_LEN 0x18
1200#define MAC_TX_BUFF2_STATUS 0x20
1201#define MAC_TX_BUFF2_ADDR 0x24
1202#define MAC_TX_BUFF2_LEN 0x28
1203#define MAC_TX_BUFF3_STATUS 0x30
1204#define MAC_TX_BUFF3_ADDR 0x34
1205#define MAC_TX_BUFF3_LEN 0x38
1206
1207#define MAC0_RX_DMA_ADDR 0xB4004100
1208#define MAC1_RX_DMA_ADDR 0xB4004300
1da177e4 1209/* offsets from MAC_RX_RING_ADDR */
ff6814d5
SS		 1210#define MAC_RX_BUFF0_STATUS 0x0
1211# define RX_FRAME_LEN_MASK 0x3fff
1212# define RX_WDOG_TIMER (1 << 14)
1213# define RX_RUNT (1 << 15)
1214# define RX_OVERLEN (1 << 16)
1215# define RX_COLL (1 << 17)
1216# define RX_ETHER (1 << 18)
1217# define RX_MII_ERROR (1 << 19)
1218# define RX_DRIBBLING (1 << 20)
1219# define RX_CRC_ERROR (1 << 21)
1220# define RX_VLAN1 (1 << 22)
1221# define RX_VLAN2 (1 << 23)
1222# define RX_LEN_ERROR (1 << 24)
1223# define RX_CNTRL_FRAME (1 << 25)
1224# define RX_U_CNTRL_FRAME (1 << 26)
1225# define RX_MCAST_FRAME (1 << 27)
1226# define RX_BCAST_FRAME (1 << 28)
1227# define RX_FILTER_FAIL (1 << 29)
1228# define RX_PACKET_FILTER (1 << 30)
1229# define RX_MISSED_FRAME (1 << 31)
49a89efb
RB		 1230
1231# define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
ff6814d5
SS		 1232 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
1233 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
1234#define MAC_RX_BUFF0_ADDR 0x4
1235# define RX_DMA_ENABLE (1 << 0)
1236# define RX_T_DONE (1 << 1)
1237# define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1238# define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0)
1239#define MAC_RX_BUFF1_STATUS 0x10
1240#define MAC_RX_BUFF1_ADDR 0x14
1241#define MAC_RX_BUFF2_STATUS 0x20
1242#define MAC_RX_BUFF2_ADDR 0x24
1243#define MAC_RX_BUFF3_STATUS 0x30
1244#define MAC_RX_BUFF3_ADDR 0x34
1da177e4
LT		 1245
1246/* UARTS 0-3 */
ff6814d5 1247#define UART_BASE UART0_ADDR
492fd5f2 1248#ifdef CONFIG_SOC_AU1200
ff6814d5 1249#define UART_DEBUG_BASE UART1_ADDR
492fd5f2 1250#else
ff6814d5 1251#define UART_DEBUG_BASE UART3_ADDR
492fd5f2 1252#endif
1da177e4
LT		 1253
1254#define UART_RX 0 /* Receive buffer */
1255#define UART_TX 4 /* Transmit buffer */
1256#define UART_IER 8 /* Interrupt Enable Register */
1257#define UART_IIR 0xC /* Interrupt ID Register */
1258#define UART_FCR 0x10 /* FIFO Control Register */
1259#define UART_LCR 0x14 /* Line Control Register */
1260#define UART_MCR 0x18 /* Modem Control Register */
1261#define UART_LSR 0x1C /* Line Status Register */
1262#define UART_MSR 0x20 /* Modem Status Register */
1263#define UART_CLK 0x28 /* Baud Rate Clock Divider */
1264#define UART_MOD_CNTRL 0x100 /* Module Control */
1265
1266#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
1267#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
1268#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
1269#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
1270#define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */
1271#define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */
1272#define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */
1273#define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */
1274#define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */
1275#define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */
1276#define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */
1277#define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */
1278#define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */
1279
1280/*
1281 * These are the definitions for the Line Control Register
1282 */
1283#define UART_LCR_SBC 0x40 /* Set break control */
1284#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
1285#define UART_LCR_EPAR 0x10 /* Even parity select */
1286#define UART_LCR_PARITY 0x08 /* Parity Enable */
1287#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
1288#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
1289#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
1290#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
1291#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
1292
1293/*
1294 * These are the definitions for the Line Status Register
1295 */
1296#define UART_LSR_TEMT 0x40 /* Transmitter empty */
1297#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1298#define UART_LSR_BI 0x10 /* Break interrupt indicator */
1299#define UART_LSR_FE 0x08 /* Frame error indicator */
1300#define UART_LSR_PE 0x04 /* Parity error indicator */
1301#define UART_LSR_OE 0x02 /* Overrun error indicator */
1302#define UART_LSR_DR 0x01 /* Receiver data ready */
1303
1304/*
1305 * These are the definitions for the Interrupt Identification Register
1306 */
1307#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1308#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1309#define UART_IIR_MSI 0x00 /* Modem status interrupt */
1310#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1311#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1312#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1313
1314/*
1315 * These are the definitions for the Interrupt Enable Register
1316 */
1317#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1318#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1319#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1320#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1321
1322/*
1323 * These are the definitions for the Modem Control Register
1324 */
1325#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
1326#define UART_MCR_OUT2 0x08 /* Out2 complement */
1327#define UART_MCR_OUT1 0x04 /* Out1 complement */
1328#define UART_MCR_RTS 0x02 /* RTS complement */
1329#define UART_MCR_DTR 0x01 /* DTR complement */
1330
1331/*
1332 * These are the definitions for the Modem Status Register
1333 */
1334#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
1335#define UART_MSR_RI 0x40 /* Ring Indicator */
1336#define UART_MSR_DSR 0x20 /* Data Set Ready */
1337#define UART_MSR_CTS 0x10 /* Clear to Send */
1338#define UART_MSR_DDCD 0x08 /* Delta DCD */
1339#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
1340#define UART_MSR_DDSR 0x02 /* Delta DSR */
1341#define UART_MSR_DCTS 0x01 /* Delta CTS */
1342#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
1343
1da177e4 1344/* SSIO */
ff6814d5
SS		 1345#define SSI0_STATUS 0xB1600000
1346# define SSI_STATUS_BF (1 << 4)
1347# define SSI_STATUS_OF (1 << 3)
1348# define SSI_STATUS_UF (1 << 2)
1349# define SSI_STATUS_D (1 << 1)
1350# define SSI_STATUS_B (1 << 0)
1351#define SSI0_INT 0xB1600004
1352# define SSI_INT_OI (1 << 3)
1353# define SSI_INT_UI (1 << 2)
1354# define SSI_INT_DI (1 << 1)
1355#define SSI0_INT_ENABLE 0xB1600008
1356# define SSI_INTE_OIE (1 << 3)
1357# define SSI_INTE_UIE (1 << 2)
1358# define SSI_INTE_DIE (1 << 1)
1359#define SSI0_CONFIG 0xB1600020
1360# define SSI_CONFIG_AO (1 << 24)
1361# define SSI_CONFIG_DO (1 << 23)
1362# define SSI_CONFIG_ALEN_BIT 20
1363# define SSI_CONFIG_ALEN_MASK (0x7 << 20)
1364# define SSI_CONFIG_DLEN_BIT 16
1365# define SSI_CONFIG_DLEN_MASK (0x7 << 16)
1366# define SSI_CONFIG_DD (1 << 11)
1367# define SSI_CONFIG_AD (1 << 10)
1368# define SSI_CONFIG_BM_BIT 8
1369# define SSI_CONFIG_BM_MASK (0x3 << 8)
1370# define SSI_CONFIG_CE (1 << 7)
1371# define SSI_CONFIG_DP (1 << 6)
1372# define SSI_CONFIG_DL (1 << 5)
1373# define SSI_CONFIG_EP (1 << 4)
1374#define SSI0_ADATA 0xB1600024
1375# define SSI_AD_D (1 << 24)
1376# define SSI_AD_ADDR_BIT 16
1377# define SSI_AD_ADDR_MASK (0xff << 16)
1378# define SSI_AD_DATA_BIT 0
1379# define SSI_AD_DATA_MASK (0xfff << 0)
1380#define SSI0_CLKDIV 0xB1600028
1381#define SSI0_CONTROL 0xB1600100
1382# define SSI_CONTROL_CD (1 << 1)
1383# define SSI_CONTROL_E (1 << 0)
1da177e4
LT		 1384
1385/* SSI1 */
ff6814d5
SS		 1386#define SSI1_STATUS 0xB1680000
1387#define SSI1_INT 0xB1680004
1388#define SSI1_INT_ENABLE 0xB1680008
1389#define SSI1_CONFIG 0xB1680020
1390#define SSI1_ADATA 0xB1680024
1391#define SSI1_CLKDIV 0xB1680028
1392#define SSI1_ENABLE 0xB1680100
1da177e4
LT		 1393
1394/*
1395 * Register content definitions
1396 */
ff6814d5
SS		 1397#define SSI_STATUS_BF (1 << 4)
1398#define SSI_STATUS_OF (1 << 3)
1399#define SSI_STATUS_UF (1 << 2)
1400#define SSI_STATUS_D (1 << 1)
1401#define SSI_STATUS_B (1 << 0)
1da177e4
LT		 1402
1403/* SSI_INT */
ff6814d5
SS		 1404#define SSI_INT_OI (1 << 3)
1405#define SSI_INT_UI (1 << 2)
1406#define SSI_INT_DI (1 << 1)
1da177e4
LT		 1407
1408/* SSI_INTEN */
ff6814d5
SS		 1409#define SSI_INTEN_OIE (1 << 3)
1410#define SSI_INTEN_UIE (1 << 2)
1411#define SSI_INTEN_DIE (1 << 1)
1412
1413#define SSI_CONFIG_AO (1 << 24)
1414#define SSI_CONFIG_DO (1 << 23)
1415#define SSI_CONFIG_ALEN (7 << 20)
1416#define SSI_CONFIG_DLEN (15 << 16)
1417#define SSI_CONFIG_DD (1 << 11)
1418#define SSI_CONFIG_AD (1 << 10)
1419#define SSI_CONFIG_BM (3 << 8)
1420#define SSI_CONFIG_CE (1 << 7)
1421#define SSI_CONFIG_DP (1 << 6)
1422#define SSI_CONFIG_DL (1 << 5)
1423#define SSI_CONFIG_EP (1 << 4)
1424#define SSI_CONFIG_ALEN_N(N) ((N-1) << 20)
1425#define SSI_CONFIG_DLEN_N(N) ((N-1) << 16)
1426#define SSI_CONFIG_BM_HI (0 << 8)
1427#define SSI_CONFIG_BM_LO (1 << 8)
1428#define SSI_CONFIG_BM_CY (2 << 8)
1429
1430#define SSI_ADATA_D (1 << 24)
1431#define SSI_ADATA_ADDR (0xFF << 16)
1432#define SSI_ADATA_DATA 0x0FFF
1433#define SSI_ADATA_ADDR_N(N) (N << 16)
1434
1435#define SSI_ENABLE_CD (1 << 1)
1436#define SSI_ENABLE_E (1 << 0)
1da177e4
LT		 1437
1438/* IrDA Controller */
ff6814d5
SS		 1439#define IRDA_BASE 0xB0300000
1440#define IR_RING_PTR_STATUS (IRDA_BASE + 0x00)
1441#define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04)
1442#define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08)
1443#define IR_RING_SIZE (IRDA_BASE + 0x0C)
1444#define IR_RING_PROMPT (IRDA_BASE + 0x10)
1445#define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14)
1446#define IR_INT_CLEAR (IRDA_BASE + 0x18)
1447#define IR_CONFIG_1 (IRDA_BASE + 0x20)
1448# define IR_RX_INVERT_LED (1 << 0)
1449# define IR_TX_INVERT_LED (1 << 1)
1450# define IR_ST (1 << 2)
1451# define IR_SF (1 << 3)
1452# define IR_SIR (1 << 4)
1453# define IR_MIR (1 << 5)
1454# define IR_FIR (1 << 6)
1455# define IR_16CRC (1 << 7)
1456# define IR_TD (1 << 8)
1457# define IR_RX_ALL (1 << 9)
1458# define IR_DMA_ENABLE (1 << 10)
1459# define IR_RX_ENABLE (1 << 11)
1460# define IR_TX_ENABLE (1 << 12)
1461# define IR_LOOPBACK (1 << 14)
1462# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
1463 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
1464#define IR_SIR_FLAGS (IRDA_BASE + 0x24)
1465#define IR_ENABLE (IRDA_BASE + 0x28)
1466# define IR_RX_STATUS (1 << 9)
1467# define IR_TX_STATUS (1 << 10)
1468#define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C)
1469#define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30)
1470#define IR_MAX_PKT_LEN (IRDA_BASE + 0x34)
1471#define IR_RX_BYTE_CNT (IRDA_BASE + 0x38)
1472#define IR_CONFIG_2 (IRDA_BASE + 0x3C)
1473# define IR_MODE_INV (1 << 0)
1474# define IR_ONE_PIN (1 << 1)
1475#define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40)
1da177e4
LT		 1476
1477/* GPIO */
ff6814d5
SS		 1478#define SYS_PINFUNC 0xB190002C
1479# define SYS_PF_USB (1 << 15) /* 2nd USB device/host */
1480# define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */
1481# define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */
1482# define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */
1483# define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */
1484# define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */
1485# define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */
1486# define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */
1487# define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */
1488# define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */
1489# define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */
1490# define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */
1491# define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */
1492# define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */
1493# define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */
1494# define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */
1495
1496/* Au1100 only */
1497# define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */
1498# define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */
1499# define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */
1500# define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */
1501
1502/* Au1550 only. Redefines lots of pins */
1503# define SYS_PF_PSC2_MASK (7 << 17)
1504# define SYS_PF_PSC2_AC97 0
1505# define SYS_PF_PSC2_SPI 0
1506# define SYS_PF_PSC2_I2S (1 << 17)
1507# define SYS_PF_PSC2_SMBUS (3 << 17)
1508# define SYS_PF_PSC2_GPIO (7 << 17)
1509# define SYS_PF_PSC3_MASK (7 << 20)
1510# define SYS_PF_PSC3_AC97 0
1511# define SYS_PF_PSC3_SPI 0
1512# define SYS_PF_PSC3_I2S (1 << 20)
1513# define SYS_PF_PSC3_SMBUS (3 << 20)
1514# define SYS_PF_PSC3_GPIO (7 << 20)
1515# define SYS_PF_PSC1_S1 (1 << 1)
1516# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1517
1518/* Au1200 only */
e3ad1c23 1519#ifdef CONFIG_SOC_AU1200
ff6814d5
SS		 1520#define SYS_PINFUNC_DMA (1 << 31)
1521#define SYS_PINFUNC_S0A (1 << 30)
1522#define SYS_PINFUNC_S1A (1 << 29)
1523#define SYS_PINFUNC_LP0 (1 << 28)
1524#define SYS_PINFUNC_LP1 (1 << 27)
1525#define SYS_PINFUNC_LD16 (1 << 26)
1526#define SYS_PINFUNC_LD8 (1 << 25)
1527#define SYS_PINFUNC_LD1 (1 << 24)
1528#define SYS_PINFUNC_LD0 (1 << 23)
1529#define SYS_PINFUNC_P1A (3 << 21)
1530#define SYS_PINFUNC_P1B (1 << 20)
1531#define SYS_PINFUNC_FS3 (1 << 19)
1532#define SYS_PINFUNC_P0A (3 << 17)
1533#define SYS_PINFUNC_CS (1 << 16)
1534#define SYS_PINFUNC_CIM (1 << 15)
1535#define SYS_PINFUNC_P1C (1 << 14)
1536#define SYS_PINFUNC_U1T (1 << 12)
1537#define SYS_PINFUNC_U1R (1 << 11)
1538#define SYS_PINFUNC_EX1 (1 << 10)
1539#define SYS_PINFUNC_EX0 (1 << 9)
1540#define SYS_PINFUNC_U0R (1 << 8)
1541#define SYS_PINFUNC_MC (1 << 7)
1542#define SYS_PINFUNC_S0B (1 << 6)
1543#define SYS_PINFUNC_S0C (1 << 5)
1544#define SYS_PINFUNC_P0B (1 << 4)
1545#define SYS_PINFUNC_U0T (1 << 3)
1546#define SYS_PINFUNC_S1B (1 << 2)
e3ad1c23
PP		 1547#endif
1548
ff6814d5
SS		 1549#define SYS_TRIOUTRD 0xB1900100
1550#define SYS_TRIOUTCLR 0xB1900100
1551#define SYS_OUTPUTRD 0xB1900108
1552#define SYS_OUTPUTSET 0xB1900108
1553#define SYS_OUTPUTCLR 0xB190010C
1554#define SYS_PINSTATERD 0xB1900110
1555#define SYS_PININPUTEN 0xB1900110
1da177e4
LT		 1556
1557/* GPIO2, Au1500, Au1550 only */
ff6814d5
SS		 1558#define GPIO2_BASE 0xB1700000
1559#define GPIO2_DIR (GPIO2_BASE + 0)
1560#define GPIO2_OUTPUT (GPIO2_BASE + 8)
1561#define GPIO2_PINSTATE (GPIO2_BASE + 0xC)
1562#define GPIO2_INTENABLE (GPIO2_BASE + 0x10)
1563#define GPIO2_ENABLE (GPIO2_BASE + 0x14)
1da177e4
LT		 1564
1565/* Power Management */
ff6814d5
SS		 1566#define SYS_SCRATCH0 0xB1900018
1567#define SYS_SCRATCH1 0xB190001C
1568#define SYS_WAKEMSK 0xB1900034
1569#define SYS_ENDIAN 0xB1900038
1570#define SYS_POWERCTRL 0xB190003C
1571#define SYS_WAKESRC 0xB190005C
1572#define SYS_SLPPWR 0xB1900078
1573#define SYS_SLEEP 0xB190007C
1da177e4 1574
61f9c58d
ML		 1575#define SYS_WAKEMSK_D2 (1 << 9)
1576#define SYS_WAKEMSK_M2 (1 << 8)
1577#define SYS_WAKEMSK_GPIO(x) (1 << (x))
1578
1da177e4 1579/* Clock Controller */
ff6814d5
SS		 1580#define SYS_FREQCTRL0 0xB1900020
1581# define SYS_FC_FRDIV2_BIT 22
1582# define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
1583# define SYS_FC_FE2 (1 << 21)
1584# define SYS_FC_FS2 (1 << 20)
1585# define SYS_FC_FRDIV1_BIT 12
1586# define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
1587# define SYS_FC_FE1 (1 << 11)
1588# define SYS_FC_FS1 (1 << 10)
1589# define SYS_FC_FRDIV0_BIT 2
1590# define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
1591# define SYS_FC_FE0 (1 << 1)
1592# define SYS_FC_FS0 (1 << 0)
1593#define SYS_FREQCTRL1 0xB1900024
1594# define SYS_FC_FRDIV5_BIT 22
1595# define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
1596# define SYS_FC_FE5 (1 << 21)
1597# define SYS_FC_FS5 (1 << 20)
1598# define SYS_FC_FRDIV4_BIT 12
1599# define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
1600# define SYS_FC_FE4 (1 << 11)
1601# define SYS_FC_FS4 (1 << 10)
1602# define SYS_FC_FRDIV3_BIT 2
1603# define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
1604# define SYS_FC_FE3 (1 << 1)
1605# define SYS_FC_FS3 (1 << 0)
1606#define SYS_CLKSRC 0xB1900028
1607# define SYS_CS_ME1_BIT 27
1608# define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
1609# define SYS_CS_DE1 (1 << 26)
1610# define SYS_CS_CE1 (1 << 25)
1611# define SYS_CS_ME0_BIT 22
1612# define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
1613# define SYS_CS_DE0 (1 << 21)
1614# define SYS_CS_CE0 (1 << 20)
1615# define SYS_CS_MI2_BIT 17
1616# define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
1617# define SYS_CS_DI2 (1 << 16)
1618# define SYS_CS_CI2 (1 << 15)
3b495f2b 1619#ifdef CONFIG_SOC_AU1100
ff6814d5
SS		 1620# define SYS_CS_ML_BIT 7
1621# define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT)
1622# define SYS_CS_DL (1 << 6)
1623# define SYS_CS_CL (1 << 5)
3b495f2b 1624#else
ff6814d5
SS		 1625# define SYS_CS_MUH_BIT 12
1626# define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
1627# define SYS_CS_DUH (1 << 11)
1628# define SYS_CS_CUH (1 << 10)
1629# define SYS_CS_MUD_BIT 7
1630# define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
1631# define SYS_CS_DUD (1 << 6)
1632# define SYS_CS_CUD (1 << 5)
3b495f2b 1633#endif
ff6814d5
SS		 1634# define SYS_CS_MIR_BIT 2
1635# define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
1636# define SYS_CS_DIR (1 << 1)
1637# define SYS_CS_CIR (1 << 0)
1638
1639# define SYS_CS_MUX_AUX 0x1
1640# define SYS_CS_MUX_FQ0 0x2
1641# define SYS_CS_MUX_FQ1 0x3
1642# define SYS_CS_MUX_FQ2 0x4
1643# define SYS_CS_MUX_FQ3 0x5
1644# define SYS_CS_MUX_FQ4 0x6
1645# define SYS_CS_MUX_FQ5 0x7
1646#define SYS_CPUPLL 0xB1900060
1647#define SYS_AUXPLL 0xB1900064
1da177e4
LT		 1648
1649/* AC97 Controller */
ff6814d5
SS		 1650#define AC97C_CONFIG 0xB0000000
1651# define AC97C_RECV_SLOTS_BIT 13
49a89efb 1652# define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
ff6814d5 1653# define AC97C_XMIT_SLOTS_BIT 3
49a89efb 1654# define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
ff6814d5
SS		 1655# define AC97C_SG (1 << 2)
1656# define AC97C_SYNC (1 << 1)
1657# define AC97C_RESET (1 << 0)
1658#define AC97C_STATUS 0xB0000004
1659# define AC97C_XU (1 << 11)
1660# define AC97C_XO (1 << 10)
1661# define AC97C_RU (1 << 9)
1662# define AC97C_RO (1 << 8)
1663# define AC97C_READY (1 << 7)
1664# define AC97C_CP (1 << 6)
1665# define AC97C_TR (1 << 5)
1666# define AC97C_TE (1 << 4)
1667# define AC97C_TF (1 << 3)
1668# define AC97C_RR (1 << 2)
1669# define AC97C_RE (1 << 1)
1670# define AC97C_RF (1 << 0)
1671#define AC97C_DATA 0xB0000008
1672#define AC97C_CMD 0xB000000C
1673# define AC97C_WD_BIT 16
1674# define AC97C_READ (1 << 7)
1675# define AC97C_INDEX_MASK 0x7f
1676#define AC97C_CNTRL 0xB0000010
1677# define AC97C_RS (1 << 1)
1678# define AC97C_CE (1 << 0)
1da177e4
LT		 1679
1680/* Secure Digital (SD) Controller */
1681#define SD0_XMIT_FIFO 0xB0600000
1682#define SD0_RECV_FIFO 0xB0600004
1683#define SD1_XMIT_FIFO 0xB0680000
1684#define SD1_RECV_FIFO 0xB0680004
1685
49a89efb 1686#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1da177e4 1687/* Au1500 PCI Controller */
ff6814d5
SS		 1688#define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */
1689#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
1690#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
1691# define PCI_ERROR ((1 << 22) | (1 << 23) | (1 << 24) | \
1692 (1 << 25) | (1 << 26) | (1 << 27))
1693#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
1694#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
1695#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
1696#define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
1da177e4 1697#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
ff6814d5
SS		 1698#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
1699#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
1700#define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
1701#define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
1702#define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
1703#define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
1704#define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
1da177e4 1705
ff6814d5 1706#define Au1500_PCI_HDR 0xB4005100 /* virtual, KSEG1 addr */
1da177e4 1707
ff6814d5
SS		 1708/*
1709 * All of our structures, like PCI resource, have 32-bit members.
1da177e4 1710 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
ff6814d5 1711 * hard to store 0x4 0000 0000 in a 32-bit type. We require a small patch
1da177e4 1712 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
ff6814d5
SS		 1713 * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM
1714 * addresses. For PCI I/O, it's simpler because we get to do the ioremap
1da177e4
LT		 1715 * ourselves and then adjust the device's resources.
1716 */
ff6814d5
SS		 1717#define Au1500_EXT_CFG 0x600000000ULL
1718#define Au1500_EXT_CFG_TYPE1 0x680000000ULL
1719#define Au1500_PCI_IO_START 0x500000000ULL
1720#define Au1500_PCI_IO_END 0x5000FFFFFULL
1721#define Au1500_PCI_MEM_START 0x440000000ULL
1722#define Au1500_PCI_MEM_END 0x44FFFFFFFULL
1da177e4 1723
dd99d966
SS		 1724#define PCI_IO_START 0x00001000
1725#define PCI_IO_END 0x000FFFFF
1726#define PCI_MEM_START 0x40000000
1727#define PCI_MEM_END 0x4FFFFFFF
1728
ff6814d5
SS		 1729#define PCI_FIRST_DEVFN (0 << 3)
1730#define PCI_LAST_DEVFN (19 << 3)
1da177e4 1731
ff6814d5
SS		 1732#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
1733#define IOPORT_RESOURCE_END 0xffffffff
1734#define IOMEM_RESOURCE_START 0x10000000
1735#define IOMEM_RESOURCE_END 0xffffffff
1da177e4 1736
e3ad1c23 1737#else /* Au1000 and Au1100 and Au1200 */
1da177e4 1738
ff6814d5
SS		 1739/* Don't allow any legacy ports probing */
1740#define IOPORT_RESOURCE_START 0x10000000
1741#define IOPORT_RESOURCE_END 0xffffffff
1742#define IOMEM_RESOURCE_START 0x10000000
1743#define IOMEM_RESOURCE_END 0xffffffff
1da177e4 1744
ff6814d5
SS		 1745#define PCI_IO_START 0
1746#define PCI_IO_END 0
1747#define PCI_MEM_START 0
1748#define PCI_MEM_END 0
1da177e4 1749#define PCI_FIRST_DEVFN 0
ff6814d5 1750#define PCI_LAST_DEVFN 0
1da177e4
LT		 1751
1752#endif
1753
66213b3c
ML		 1754/*
1755 * All Au1xx0 SOCs have a PCMCIA controller.
1756 * We setup our 32-bit pseudo addresses to be equal to the
1757 * 36-bit addr >> 4, to make it easier to check the address
1758 * and fix it.
1759 * The PCMCIA socket 0 physical attribute address is 0xF 4000 0000.
1760 * The pseudo address we use is 0xF400 0000. Any address over
1761 * 0xF400 0000 is a PCMCIA pseudo address.
1762 */
1763#define PCMCIA_IO_PSEUDO_PHYS (PCMCIA_IO_PHYS_ADDR >> 4)
1764#define PCMCIA_ATTR_PSEUDO_PHYS (PCMCIA_ATTR_PHYS_ADDR >> 4)
1765#define PCMCIA_MEM_PSEUDO_PHYS (PCMCIA_MEM_PHYS_ADDR >> 4)
1766#define PCMCIA_PSEUDO_END (0xffffffff)
1767
e3ad1c23 1768#ifndef _LANGUAGE_ASSEMBLY
ff6814d5 1769typedef volatile struct {
e3ad1c23
PP		 1770 /* 0x0000 */ u32 toytrim;
1771 /* 0x0004 */ u32 toywrite;
1772 /* 0x0008 */ u32 toymatch0;
1773 /* 0x000C */ u32 toymatch1;
1774 /* 0x0010 */ u32 toymatch2;
1775 /* 0x0014 */ u32 cntrctrl;
1776 /* 0x0018 */ u32 scratch0;
1777 /* 0x001C */ u32 scratch1;
1778 /* 0x0020 */ u32 freqctrl0;
1779 /* 0x0024 */ u32 freqctrl1;
1780 /* 0x0028 */ u32 clksrc;
1781 /* 0x002C */ u32 pinfunc;
1782 /* 0x0030 */ u32 reserved0;
1783 /* 0x0034 */ u32 wakemsk;
1784 /* 0x0038 */ u32 endian;
1785 /* 0x003C */ u32 powerctrl;
1786 /* 0x0040 */ u32 toyread;
1787 /* 0x0044 */ u32 rtctrim;
1788 /* 0x0048 */ u32 rtcwrite;
1789 /* 0x004C */ u32 rtcmatch0;
1790 /* 0x0050 */ u32 rtcmatch1;
1791 /* 0x0054 */ u32 rtcmatch2;
1792 /* 0x0058 */ u32 rtcread;
1793 /* 0x005C */ u32 wakesrc;
1794 /* 0x0060 */ u32 cpupll;
1795 /* 0x0064 */ u32 auxpll;
1796 /* 0x0068 */ u32 reserved1;
1797 /* 0x006C */ u32 reserved2;
1798 /* 0x0070 */ u32 reserved3;
1799 /* 0x0074 */ u32 reserved4;
1800 /* 0x0078 */ u32 slppwr;
1801 /* 0x007C */ u32 sleep;
1802 /* 0x0080 */ u32 reserved5[32];
1803 /* 0x0100 */ u32 trioutrd;
1804#define trioutclr trioutrd
1805 /* 0x0104 */ u32 reserved6;
1806 /* 0x0108 */ u32 outputrd;
1807#define outputset outputrd
1808 /* 0x010C */ u32 outputclr;
1809 /* 0x0110 */ u32 pinstaterd;
1810#define pininputen pinstaterd
e3ad1c23
PP		 1811} AU1X00_SYS;
1812
ff6814d5 1813static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE;
e3ad1c23
PP		 1814
1815#endif
ff6814d5 1816
e3ad1c23 1817#endif
Linux kernel - Deliverables
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