projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| e7300d04 MB |
1 | #ifndef BCM63XX_REGS_H_ |
| 2 | #define BCM63XX_REGS_H_ | |
| 3 | ||
| 4 | /************************************************************************* | |
| 5 | * _REG relative to RSET_PERF | |
| 6 | *************************************************************************/ | |
| 7 | ||
| 8 | /* Chip Identifier / Revision register */ | |
| 9 | #define PERF_REV_REG 0x0 | |
| 10 | #define REV_CHIPID_SHIFT 16 | |
| 11 | #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) | |
| 12 | #define REV_REVID_SHIFT 0 | |
| 6605428c | 13 | #define REV_REVID_MASK (0xff << REV_REVID_SHIFT) |
| e7300d04 MB |
14 | |
| 15 | /* Clock Control register */ | |
| 16 | #define PERF_CKCTL_REG 0x4 | |
| 17 | ||
| e5766aea JG |
18 | #define CKCTL_6328_PHYMIPS_EN (1 << 0) |
| 19 | #define CKCTL_6328_ADSL_QPROC_EN (1 << 1) | |
| 20 | #define CKCTL_6328_ADSL_AFE_EN (1 << 2) | |
| 21 | #define CKCTL_6328_ADSL_EN (1 << 3) | |
| 22 | #define CKCTL_6328_MIPS_EN (1 << 4) | |
| 23 | #define CKCTL_6328_SAR_EN (1 << 5) | |
| 24 | #define CKCTL_6328_PCM_EN (1 << 6) | |
| 25 | #define CKCTL_6328_USBD_EN (1 << 7) | |
| 26 | #define CKCTL_6328_USBH_EN (1 << 8) | |
| 27 | #define CKCTL_6328_HSSPI_EN (1 << 9) | |
| 28 | #define CKCTL_6328_PCIE_EN (1 << 10) | |
| 29 | #define CKCTL_6328_ROBOSW_EN (1 << 11) | |
| 30 | ||
| 31 | #define CKCTL_6328_ALL_SAFE_EN (CKCTL_6328_PHYMIPS_EN | \ | |
| 32 | CKCTL_6328_ADSL_QPROC_EN | \ | |
| 33 | CKCTL_6328_ADSL_AFE_EN | \ | |
| 34 | CKCTL_6328_ADSL_EN | \ | |
| 35 | CKCTL_6328_SAR_EN | \ | |
| 36 | CKCTL_6328_PCM_EN | \ | |
| 37 | CKCTL_6328_USBD_EN | \ | |
| 38 | CKCTL_6328_USBH_EN | \ | |
| 39 | CKCTL_6328_ROBOSW_EN | \ | |
| 40 | CKCTL_6328_PCIE_EN) | |
| 41 | ||
| e7300d04 MB |
42 | #define CKCTL_6338_ADSLPHY_EN (1 << 0) |
| 43 | #define CKCTL_6338_MPI_EN (1 << 1) | |
| 44 | #define CKCTL_6338_DRAM_EN (1 << 2) | |
| 45 | #define CKCTL_6338_ENET_EN (1 << 4) | |
| 46 | #define CKCTL_6338_USBS_EN (1 << 4) | |
| 47 | #define CKCTL_6338_SAR_EN (1 << 5) | |
| 48 | #define CKCTL_6338_SPI_EN (1 << 9) | |
| 49 | ||
| 50 | #define CKCTL_6338_ALL_SAFE_EN (CKCTL_6338_ADSLPHY_EN | \ | |
| 51 | CKCTL_6338_MPI_EN | \ | |
| 52 | CKCTL_6338_ENET_EN | \ | |
| 53 | CKCTL_6338_SAR_EN | \ | |
| 54 | CKCTL_6338_SPI_EN) | |
| 55 | ||
| e59b008e FF |
56 | /* BCM6345 clock bits are shifted by 16 on the left, because of the test |
| 57 | * control register which is 16-bits wide. That way we do not have any | |
| 58 | * specific BCM6345 code for handling clocks, and writing 0 to the test | |
| 59 | * control register is fine. | |
| 60 | */ | |
| 61 | #define CKCTL_6345_CPU_EN (1 << 16) | |
| 62 | #define CKCTL_6345_BUS_EN (1 << 17) | |
| 63 | #define CKCTL_6345_EBI_EN (1 << 18) | |
| 64 | #define CKCTL_6345_UART_EN (1 << 19) | |
| 65 | #define CKCTL_6345_ADSLPHY_EN (1 << 20) | |
| 66 | #define CKCTL_6345_ENET_EN (1 << 23) | |
| 67 | #define CKCTL_6345_USBH_EN (1 << 24) | |
| e7300d04 MB |
68 | |
| 69 | #define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \ | |
| 70 | CKCTL_6345_USBH_EN | \ | |
| 71 | CKCTL_6345_ADSLPHY_EN) | |
| 72 | ||
| 73 | #define CKCTL_6348_ADSLPHY_EN (1 << 0) | |
| 74 | #define CKCTL_6348_MPI_EN (1 << 1) | |
| 75 | #define CKCTL_6348_SDRAM_EN (1 << 2) | |
| 76 | #define CKCTL_6348_M2M_EN (1 << 3) | |
| 77 | #define CKCTL_6348_ENET_EN (1 << 4) | |
| 78 | #define CKCTL_6348_SAR_EN (1 << 5) | |
| 79 | #define CKCTL_6348_USBS_EN (1 << 6) | |
| 80 | #define CKCTL_6348_USBH_EN (1 << 8) | |
| 81 | #define CKCTL_6348_SPI_EN (1 << 9) | |
| 82 | ||
| 83 | #define CKCTL_6348_ALL_SAFE_EN (CKCTL_6348_ADSLPHY_EN | \ | |
| 84 | CKCTL_6348_M2M_EN | \ | |
| 85 | CKCTL_6348_ENET_EN | \ | |
| 86 | CKCTL_6348_SAR_EN | \ | |
| 87 | CKCTL_6348_USBS_EN | \ | |
| 88 | CKCTL_6348_USBH_EN | \ | |
| 89 | CKCTL_6348_SPI_EN) | |
| 90 | ||
| 91 | #define CKCTL_6358_ENET_EN (1 << 4) | |
| 92 | #define CKCTL_6358_ADSLPHY_EN (1 << 5) | |
| 93 | #define CKCTL_6358_PCM_EN (1 << 8) | |
| 94 | #define CKCTL_6358_SPI_EN (1 << 9) | |
| 95 | #define CKCTL_6358_USBS_EN (1 << 10) | |
| 96 | #define CKCTL_6358_SAR_EN (1 << 11) | |
| 97 | #define CKCTL_6358_EMUSB_EN (1 << 17) | |
| 98 | #define CKCTL_6358_ENET0_EN (1 << 18) | |
| 99 | #define CKCTL_6358_ENET1_EN (1 << 19) | |
| 100 | #define CKCTL_6358_USBSU_EN (1 << 20) | |
| 101 | #define CKCTL_6358_EPHY_EN (1 << 21) | |
| 102 | ||
| 103 | #define CKCTL_6358_ALL_SAFE_EN (CKCTL_6358_ENET_EN | \ | |
| 104 | CKCTL_6358_ADSLPHY_EN | \ | |
| 105 | CKCTL_6358_PCM_EN | \ | |
| 106 | CKCTL_6358_SPI_EN | \ | |
| 107 | CKCTL_6358_USBS_EN | \ | |
| 108 | CKCTL_6358_SAR_EN | \ | |
| 109 | CKCTL_6358_EMUSB_EN | \ | |
| 110 | CKCTL_6358_ENET0_EN | \ | |
| 111 | CKCTL_6358_ENET1_EN | \ | |
| 112 | CKCTL_6358_USBSU_EN | \ | |
| 113 | CKCTL_6358_EPHY_EN) | |
| 114 | ||
| 2c8aaf71 JG |
115 | #define CKCTL_6362_ADSL_QPROC_EN (1 << 1) |
| 116 | #define CKCTL_6362_ADSL_AFE_EN (1 << 2) | |
| 117 | #define CKCTL_6362_ADSL_EN (1 << 3) | |
| 118 | #define CKCTL_6362_MIPS_EN (1 << 4) | |
| 119 | #define CKCTL_6362_WLAN_OCP_EN (1 << 5) | |
| 120 | #define CKCTL_6362_SWPKT_USB_EN (1 << 7) | |
| 121 | #define CKCTL_6362_SWPKT_SAR_EN (1 << 8) | |
| 122 | #define CKCTL_6362_SAR_EN (1 << 9) | |
| 123 | #define CKCTL_6362_ROBOSW_EN (1 << 10) | |
| 124 | #define CKCTL_6362_PCM_EN (1 << 11) | |
| 125 | #define CKCTL_6362_USBD_EN (1 << 12) | |
| 126 | #define CKCTL_6362_USBH_EN (1 << 13) | |
| 127 | #define CKCTL_6362_IPSEC_EN (1 << 14) | |
| 128 | #define CKCTL_6362_SPI_EN (1 << 15) | |
| 129 | #define CKCTL_6362_HSSPI_EN (1 << 16) | |
| 130 | #define CKCTL_6362_PCIE_EN (1 << 17) | |
| 131 | #define CKCTL_6362_FAP_EN (1 << 18) | |
| 132 | #define CKCTL_6362_PHYMIPS_EN (1 << 19) | |
| 133 | #define CKCTL_6362_NAND_EN (1 << 20) | |
| 134 | ||
| 135 | #define CKCTL_6362_ALL_SAFE_EN (CKCTL_6362_PHYMIPS_EN | \ | |
| 136 | CKCTL_6362_ADSL_QPROC_EN | \ | |
| 137 | CKCTL_6362_ADSL_AFE_EN | \ | |
| 138 | CKCTL_6362_ADSL_EN | \ | |
| 139 | CKCTL_6362_SAR_EN | \ | |
| 140 | CKCTL_6362_PCM_EN | \ | |
| 141 | CKCTL_6362_IPSEC_EN | \ | |
| 142 | CKCTL_6362_USBD_EN | \ | |
| 143 | CKCTL_6362_USBH_EN | \ | |
| 144 | CKCTL_6362_ROBOSW_EN | \ | |
| 145 | CKCTL_6362_PCIE_EN) | |
| 146 | ||
| 147 | ||
| 04712f3f MB |
148 | #define CKCTL_6368_VDSL_QPROC_EN (1 << 2) |
| 149 | #define CKCTL_6368_VDSL_AFE_EN (1 << 3) | |
| 150 | #define CKCTL_6368_VDSL_BONDING_EN (1 << 4) | |
| 151 | #define CKCTL_6368_VDSL_EN (1 << 5) | |
| 152 | #define CKCTL_6368_PHYMIPS_EN (1 << 6) | |
| 153 | #define CKCTL_6368_SWPKT_USB_EN (1 << 7) | |
| 154 | #define CKCTL_6368_SWPKT_SAR_EN (1 << 8) | |
| d9831a41 FF |
155 | #define CKCTL_6368_SPI_EN (1 << 9) |
| 156 | #define CKCTL_6368_USBD_EN (1 << 10) | |
| 157 | #define CKCTL_6368_SAR_EN (1 << 11) | |
| 158 | #define CKCTL_6368_ROBOSW_EN (1 << 12) | |
| 159 | #define CKCTL_6368_UTOPIA_EN (1 << 13) | |
| 160 | #define CKCTL_6368_PCM_EN (1 << 14) | |
| 161 | #define CKCTL_6368_USBH_EN (1 << 15) | |
| 04712f3f | 162 | #define CKCTL_6368_DISABLE_GLESS_EN (1 << 16) |
| d9831a41 FF |
163 | #define CKCTL_6368_NAND_EN (1 << 17) |
| 164 | #define CKCTL_6368_IPSEC_EN (1 << 18) | |
| 04712f3f MB |
165 | |
| 166 | #define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \ | |
| 167 | CKCTL_6368_SWPKT_SAR_EN | \ | |
| d9831a41 FF |
168 | CKCTL_6368_SPI_EN | \ |
| 169 | CKCTL_6368_USBD_EN | \ | |
| 170 | CKCTL_6368_SAR_EN | \ | |
| 171 | CKCTL_6368_ROBOSW_EN | \ | |
| 172 | CKCTL_6368_UTOPIA_EN | \ | |
| 173 | CKCTL_6368_PCM_EN | \ | |
| 174 | CKCTL_6368_USBH_EN | \ | |
| 04712f3f | 175 | CKCTL_6368_DISABLE_GLESS_EN | \ |
| d9831a41 FF |
176 | CKCTL_6368_NAND_EN | \ |
| 177 | CKCTL_6368_IPSEC_EN) | |
| 04712f3f | 178 | |
| 70342287 | 179 | /* System PLL Control register */ |
| e7300d04 MB |
180 | #define PERF_SYS_PLL_CTL_REG 0x8 |
| 181 | #define SYS_PLL_SOFT_RESET 0x1 | |
| 182 | ||
| 183 | /* Interrupt Mask register */ | |
| e5766aea | 184 | #define PERF_IRQMASK_6328_REG 0x20 |
| f61cced9 MB |
185 | #define PERF_IRQMASK_6338_REG 0xc |
| 186 | #define PERF_IRQMASK_6345_REG 0xc | |
| 187 | #define PERF_IRQMASK_6348_REG 0xc | |
| 188 | #define PERF_IRQMASK_6358_REG 0xc | |
| 2c8aaf71 | 189 | #define PERF_IRQMASK_6362_REG 0x20 |
| 04712f3f | 190 | #define PERF_IRQMASK_6368_REG 0x20 |
| e7300d04 MB |
191 | |
| 192 | /* Interrupt Status register */ | |
| e5766aea | 193 | #define PERF_IRQSTAT_6328_REG 0x28 |
| f61cced9 MB |
194 | #define PERF_IRQSTAT_6338_REG 0x10 |
| 195 | #define PERF_IRQSTAT_6345_REG 0x10 | |
| 196 | #define PERF_IRQSTAT_6348_REG 0x10 | |
| 197 | #define PERF_IRQSTAT_6358_REG 0x10 | |
| 2c8aaf71 | 198 | #define PERF_IRQSTAT_6362_REG 0x28 |
| 04712f3f | 199 | #define PERF_IRQSTAT_6368_REG 0x28 |
| e7300d04 MB |
200 | |
| 201 | /* External Interrupt Configuration register */ | |
| e5766aea | 202 | #define PERF_EXTIRQ_CFG_REG_6328 0x18 |
| 6224892c | 203 | #define PERF_EXTIRQ_CFG_REG_6338 0x14 |
| 64eaea4a | 204 | #define PERF_EXTIRQ_CFG_REG_6345 0x14 |
| 6224892c MB |
205 | #define PERF_EXTIRQ_CFG_REG_6348 0x14 |
| 206 | #define PERF_EXTIRQ_CFG_REG_6358 0x14 | |
| 2c8aaf71 | 207 | #define PERF_EXTIRQ_CFG_REG_6362 0x18 |
| 04712f3f MB |
208 | #define PERF_EXTIRQ_CFG_REG_6368 0x18 |
| 209 | ||
| 210 | #define PERF_EXTIRQ_CFG_REG2_6368 0x1c | |
| 6224892c MB |
211 | |
| 212 | /* for 6348 only */ | |
| 213 | #define EXTIRQ_CFG_SENSE_6348(x) (1 << (x)) | |
| 214 | #define EXTIRQ_CFG_STAT_6348(x) (1 << (x + 5)) | |
| 215 | #define EXTIRQ_CFG_CLEAR_6348(x) (1 << (x + 10)) | |
| 216 | #define EXTIRQ_CFG_MASK_6348(x) (1 << (x + 15)) | |
| 217 | #define EXTIRQ_CFG_BOTHEDGE_6348(x) (1 << (x + 20)) | |
| 218 | #define EXTIRQ_CFG_LEVELSENSE_6348(x) (1 << (x + 25)) | |
| 219 | #define EXTIRQ_CFG_CLEAR_ALL_6348 (0xf << 10) | |
| 220 | #define EXTIRQ_CFG_MASK_ALL_6348 (0xf << 15) | |
| 221 | ||
| 222 | /* for all others */ | |
| e7300d04 | 223 | #define EXTIRQ_CFG_SENSE(x) (1 << (x)) |
| 6224892c MB |
224 | #define EXTIRQ_CFG_STAT(x) (1 << (x + 4)) |
| 225 | #define EXTIRQ_CFG_CLEAR(x) (1 << (x + 8)) | |
| 226 | #define EXTIRQ_CFG_MASK(x) (1 << (x + 12)) | |
| 227 | #define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 16)) | |
| 228 | #define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 20)) | |
| 229 | #define EXTIRQ_CFG_CLEAR_ALL (0xf << 8) | |
| 230 | #define EXTIRQ_CFG_MASK_ALL (0xf << 12) | |
| e7300d04 MB |
231 | |
| 232 | /* Soft Reset register */ | |
| 233 | #define PERF_SOFTRESET_REG 0x28 | |
| e5766aea | 234 | #define PERF_SOFTRESET_6328_REG 0x10 |
| e7e9937f | 235 | #define PERF_SOFTRESET_6358_REG 0x34 |
| 2c8aaf71 | 236 | #define PERF_SOFTRESET_6362_REG 0x10 |
| 04712f3f | 237 | #define PERF_SOFTRESET_6368_REG 0x10 |
| e7300d04 | 238 | |
| e5766aea JG |
239 | #define SOFTRESET_6328_SPI_MASK (1 << 0) |
| 240 | #define SOFTRESET_6328_EPHY_MASK (1 << 1) | |
| 241 | #define SOFTRESET_6328_SAR_MASK (1 << 2) | |
| 242 | #define SOFTRESET_6328_ENETSW_MASK (1 << 3) | |
| 243 | #define SOFTRESET_6328_USBS_MASK (1 << 4) | |
| 244 | #define SOFTRESET_6328_USBH_MASK (1 << 5) | |
| 245 | #define SOFTRESET_6328_PCM_MASK (1 << 6) | |
| 246 | #define SOFTRESET_6328_PCIE_CORE_MASK (1 << 7) | |
| 247 | #define SOFTRESET_6328_PCIE_MASK (1 << 8) | |
| 248 | #define SOFTRESET_6328_PCIE_EXT_MASK (1 << 9) | |
| 249 | #define SOFTRESET_6328_PCIE_HARD_MASK (1 << 10) | |
| 250 | ||
| e7300d04 MB |
251 | #define SOFTRESET_6338_SPI_MASK (1 << 0) |
| 252 | #define SOFTRESET_6338_ENET_MASK (1 << 2) | |
| 253 | #define SOFTRESET_6338_USBH_MASK (1 << 3) | |
| 254 | #define SOFTRESET_6338_USBS_MASK (1 << 4) | |
| 255 | #define SOFTRESET_6338_ADSL_MASK (1 << 5) | |
| 256 | #define SOFTRESET_6338_DMAMEM_MASK (1 << 6) | |
| 257 | #define SOFTRESET_6338_SAR_MASK (1 << 7) | |
| 258 | #define SOFTRESET_6338_ACLC_MASK (1 << 8) | |
| 70342287 | 259 | #define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10) |
| e7300d04 MB |
260 | #define SOFTRESET_6338_ALL (SOFTRESET_6338_SPI_MASK | \ |
| 261 | SOFTRESET_6338_ENET_MASK | \ | |
| 262 | SOFTRESET_6338_USBH_MASK | \ | |
| 263 | SOFTRESET_6338_USBS_MASK | \ | |
| 264 | SOFTRESET_6338_ADSL_MASK | \ | |
| 265 | SOFTRESET_6338_DMAMEM_MASK | \ | |
| 266 | SOFTRESET_6338_SAR_MASK | \ | |
| 267 | SOFTRESET_6338_ACLC_MASK | \ | |
| 268 | SOFTRESET_6338_ADSLMIPSPLL_MASK) | |
| 269 | ||
| 270 | #define SOFTRESET_6348_SPI_MASK (1 << 0) | |
| 271 | #define SOFTRESET_6348_ENET_MASK (1 << 2) | |
| 272 | #define SOFTRESET_6348_USBH_MASK (1 << 3) | |
| 273 | #define SOFTRESET_6348_USBS_MASK (1 << 4) | |
| 274 | #define SOFTRESET_6348_ADSL_MASK (1 << 5) | |
| 275 | #define SOFTRESET_6348_DMAMEM_MASK (1 << 6) | |
| 276 | #define SOFTRESET_6348_SAR_MASK (1 << 7) | |
| 277 | #define SOFTRESET_6348_ACLC_MASK (1 << 8) | |
| 70342287 | 278 | #define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10) |
| e7300d04 MB |
279 | |
| 280 | #define SOFTRESET_6348_ALL (SOFTRESET_6348_SPI_MASK | \ | |
| 281 | SOFTRESET_6348_ENET_MASK | \ | |
| 282 | SOFTRESET_6348_USBH_MASK | \ | |
| 283 | SOFTRESET_6348_USBS_MASK | \ | |
| 284 | SOFTRESET_6348_ADSL_MASK | \ | |
| 285 | SOFTRESET_6348_DMAMEM_MASK | \ | |
| 286 | SOFTRESET_6348_SAR_MASK | \ | |
| 287 | SOFTRESET_6348_ACLC_MASK | \ | |
| 288 | SOFTRESET_6348_ADSLMIPSPLL_MASK) | |
| 289 | ||
| e7e9937f JG |
290 | #define SOFTRESET_6358_SPI_MASK (1 << 0) |
| 291 | #define SOFTRESET_6358_ENET_MASK (1 << 2) | |
| 292 | #define SOFTRESET_6358_MPI_MASK (1 << 3) | |
| 293 | #define SOFTRESET_6358_EPHY_MASK (1 << 6) | |
| 294 | #define SOFTRESET_6358_SAR_MASK (1 << 7) | |
| 295 | #define SOFTRESET_6358_USBH_MASK (1 << 12) | |
| 296 | #define SOFTRESET_6358_PCM_MASK (1 << 13) | |
| 297 | #define SOFTRESET_6358_ADSL_MASK (1 << 14) | |
| 298 | ||
| 2c8aaf71 JG |
299 | #define SOFTRESET_6362_SPI_MASK (1 << 0) |
| 300 | #define SOFTRESET_6362_IPSEC_MASK (1 << 1) | |
| 301 | #define SOFTRESET_6362_EPHY_MASK (1 << 2) | |
| 302 | #define SOFTRESET_6362_SAR_MASK (1 << 3) | |
| 303 | #define SOFTRESET_6362_ENETSW_MASK (1 << 4) | |
| 304 | #define SOFTRESET_6362_USBS_MASK (1 << 5) | |
| 305 | #define SOFTRESET_6362_USBH_MASK (1 << 6) | |
| 306 | #define SOFTRESET_6362_PCM_MASK (1 << 7) | |
| 307 | #define SOFTRESET_6362_PCIE_CORE_MASK (1 << 8) | |
| 308 | #define SOFTRESET_6362_PCIE_MASK (1 << 9) | |
| 309 | #define SOFTRESET_6362_PCIE_EXT_MASK (1 << 10) | |
| 310 | #define SOFTRESET_6362_WLAN_SHIM_MASK (1 << 11) | |
| 311 | #define SOFTRESET_6362_DDR_PHY_MASK (1 << 12) | |
| 312 | #define SOFTRESET_6362_FAP_MASK (1 << 13) | |
| 313 | #define SOFTRESET_6362_WLAN_UBUS_MASK (1 << 14) | |
| 314 | ||
| 04712f3f MB |
315 | #define SOFTRESET_6368_SPI_MASK (1 << 0) |
| 316 | #define SOFTRESET_6368_MPI_MASK (1 << 3) | |
| 317 | #define SOFTRESET_6368_EPHY_MASK (1 << 6) | |
| 318 | #define SOFTRESET_6368_SAR_MASK (1 << 7) | |
| 319 | #define SOFTRESET_6368_ENETSW_MASK (1 << 10) | |
| 320 | #define SOFTRESET_6368_USBS_MASK (1 << 11) | |
| 321 | #define SOFTRESET_6368_USBH_MASK (1 << 12) | |
| 322 | #define SOFTRESET_6368_PCM_MASK (1 << 13) | |
| 323 | ||
| e7300d04 MB |
324 | /* MIPS PLL control register */ |
| 325 | #define PERF_MIPSPLLCTL_REG 0x34 | |
| 326 | #define MIPSPLLCTL_N1_SHIFT 20 | |
| 327 | #define MIPSPLLCTL_N1_MASK (0x7 << MIPSPLLCTL_N1_SHIFT) | |
| 328 | #define MIPSPLLCTL_N2_SHIFT 15 | |
| 329 | #define MIPSPLLCTL_N2_MASK (0x1f << MIPSPLLCTL_N2_SHIFT) | |
| 330 | #define MIPSPLLCTL_M1REF_SHIFT 12 | |
| 331 | #define MIPSPLLCTL_M1REF_MASK (0x7 << MIPSPLLCTL_M1REF_SHIFT) | |
| 332 | #define MIPSPLLCTL_M2REF_SHIFT 9 | |
| 333 | #define MIPSPLLCTL_M2REF_MASK (0x7 << MIPSPLLCTL_M2REF_SHIFT) | |
| 334 | #define MIPSPLLCTL_M1CPU_SHIFT 6 | |
| 335 | #define MIPSPLLCTL_M1CPU_MASK (0x7 << MIPSPLLCTL_M1CPU_SHIFT) | |
| 336 | #define MIPSPLLCTL_M1BUS_SHIFT 3 | |
| 337 | #define MIPSPLLCTL_M1BUS_MASK (0x7 << MIPSPLLCTL_M1BUS_SHIFT) | |
| 338 | #define MIPSPLLCTL_M2BUS_SHIFT 0 | |
| 339 | #define MIPSPLLCTL_M2BUS_MASK (0x7 << MIPSPLLCTL_M2BUS_SHIFT) | |
| 340 | ||
| 341 | /* ADSL PHY PLL Control register */ | |
| 342 | #define PERF_ADSLPLLCTL_REG 0x38 | |
| 343 | #define ADSLPLLCTL_N1_SHIFT 20 | |
| 344 | #define ADSLPLLCTL_N1_MASK (0x7 << ADSLPLLCTL_N1_SHIFT) | |
| 345 | #define ADSLPLLCTL_N2_SHIFT 15 | |
| 346 | #define ADSLPLLCTL_N2_MASK (0x1f << ADSLPLLCTL_N2_SHIFT) | |
| 347 | #define ADSLPLLCTL_M1REF_SHIFT 12 | |
| 348 | #define ADSLPLLCTL_M1REF_MASK (0x7 << ADSLPLLCTL_M1REF_SHIFT) | |
| 349 | #define ADSLPLLCTL_M2REF_SHIFT 9 | |
| 350 | #define ADSLPLLCTL_M2REF_MASK (0x7 << ADSLPLLCTL_M2REF_SHIFT) | |
| 351 | #define ADSLPLLCTL_M1CPU_SHIFT 6 | |
| 352 | #define ADSLPLLCTL_M1CPU_MASK (0x7 << ADSLPLLCTL_M1CPU_SHIFT) | |
| 353 | #define ADSLPLLCTL_M1BUS_SHIFT 3 | |
| 354 | #define ADSLPLLCTL_M1BUS_MASK (0x7 << ADSLPLLCTL_M1BUS_SHIFT) | |
| 355 | #define ADSLPLLCTL_M2BUS_SHIFT 0 | |
| 356 | #define ADSLPLLCTL_M2BUS_MASK (0x7 << ADSLPLLCTL_M2BUS_SHIFT) | |
| 357 | ||
| 358 | #define ADSLPLLCTL_VAL(n1, n2, m1ref, m2ref, m1cpu, m1bus, m2bus) \ | |
| 359 | (((n1) << ADSLPLLCTL_N1_SHIFT) | \ | |
| 360 | ((n2) << ADSLPLLCTL_N2_SHIFT) | \ | |
| 361 | ((m1ref) << ADSLPLLCTL_M1REF_SHIFT) | \ | |
| 362 | ((m2ref) << ADSLPLLCTL_M2REF_SHIFT) | \ | |
| 363 | ((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) | \ | |
| 364 | ((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) | \ | |
| 365 | ((m2bus) << ADSLPLLCTL_M2BUS_SHIFT)) | |
| 366 | ||
| 367 | ||
| 368 | /************************************************************************* | |
| 369 | * _REG relative to RSET_TIMER | |
| 370 | *************************************************************************/ | |
| 371 | ||
| 372 | #define BCM63XX_TIMER_COUNT 4 | |
| 373 | #define TIMER_T0_ID 0 | |
| 374 | #define TIMER_T1_ID 1 | |
| 375 | #define TIMER_T2_ID 2 | |
| 376 | #define TIMER_WDT_ID 3 | |
| 377 | ||
| 378 | /* Timer irqstat register */ | |
| 379 | #define TIMER_IRQSTAT_REG 0 | |
| 380 | #define TIMER_IRQSTAT_TIMER_CAUSE(x) (1 << (x)) | |
| 381 | #define TIMER_IRQSTAT_TIMER0_CAUSE (1 << 0) | |
| 382 | #define TIMER_IRQSTAT_TIMER1_CAUSE (1 << 1) | |
| 383 | #define TIMER_IRQSTAT_TIMER2_CAUSE (1 << 2) | |
| 384 | #define TIMER_IRQSTAT_WDT_CAUSE (1 << 3) | |
| 385 | #define TIMER_IRQSTAT_TIMER_IR_EN(x) (1 << ((x) + 8)) | |
| 386 | #define TIMER_IRQSTAT_TIMER0_IR_EN (1 << 8) | |
| 387 | #define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9) | |
| 388 | #define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10) | |
| 389 | ||
| 390 | /* Timer control register */ | |
| 391 | #define TIMER_CTLx_REG(x) (0x4 + (x * 4)) | |
| 392 | #define TIMER_CTL0_REG 0x4 | |
| 393 | #define TIMER_CTL1_REG 0x8 | |
| 394 | #define TIMER_CTL2_REG 0xC | |
| 395 | #define TIMER_CTL_COUNTDOWN_MASK (0x3fffffff) | |
| 396 | #define TIMER_CTL_MONOTONIC_MASK (1 << 30) | |
| 397 | #define TIMER_CTL_ENABLE_MASK (1 << 31) | |
| 398 | ||
| 399 | ||
| 400 | /************************************************************************* | |
| 401 | * _REG relative to RSET_WDT | |
| 402 | *************************************************************************/ | |
| 403 | ||
| 404 | /* Watchdog default count register */ | |
| 405 | #define WDT_DEFVAL_REG 0x0 | |
| 406 | ||
| 407 | /* Watchdog control register */ | |
| 408 | #define WDT_CTL_REG 0x4 | |
| 409 | ||
| 410 | /* Watchdog control register constants */ | |
| 411 | #define WDT_START_1 (0xff00) | |
| 412 | #define WDT_START_2 (0x00ff) | |
| 413 | #define WDT_STOP_1 (0xee00) | |
| 414 | #define WDT_STOP_2 (0x00ee) | |
| 415 | ||
| 416 | /* Watchdog reset length register */ | |
| 417 | #define WDT_RSTLEN_REG 0x8 | |
| 418 | ||
| e5766aea JG |
419 | /* Watchdog soft reset register (BCM6328 only) */ |
| 420 | #define WDT_SOFTRESET_REG 0xc | |
| e7300d04 MB |
421 | |
| 422 | /************************************************************************* | |
| 423 | * _REG relative to RSET_UARTx | |
| 424 | *************************************************************************/ | |
| 425 | ||
| 426 | /* UART Control Register */ | |
| 427 | #define UART_CTL_REG 0x0 | |
| 428 | #define UART_CTL_RXTMOUTCNT_SHIFT 0 | |
| 429 | #define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT) | |
| 430 | #define UART_CTL_RSTTXDN_SHIFT 5 | |
| 431 | #define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT) | |
| 432 | #define UART_CTL_RSTRXFIFO_SHIFT 6 | |
| 433 | #define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT) | |
| 434 | #define UART_CTL_RSTTXFIFO_SHIFT 7 | |
| 435 | #define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT) | |
| 436 | #define UART_CTL_STOPBITS_SHIFT 8 | |
| 437 | #define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT) | |
| 438 | #define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT) | |
| 439 | #define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT) | |
| 440 | #define UART_CTL_BITSPERSYM_SHIFT 12 | |
| 441 | #define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT) | |
| 442 | #define UART_CTL_XMITBRK_SHIFT 14 | |
| 443 | #define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT) | |
| 444 | #define UART_CTL_RSVD_SHIFT 15 | |
| 445 | #define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT) | |
| 446 | #define UART_CTL_RXPAREVEN_SHIFT 16 | |
| 447 | #define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT) | |
| 448 | #define UART_CTL_RXPAREN_SHIFT 17 | |
| 449 | #define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT) | |
| 450 | #define UART_CTL_TXPAREVEN_SHIFT 18 | |
| 451 | #define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT) | |
| 452 | #define UART_CTL_TXPAREN_SHIFT 18 | |
| 453 | #define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT) | |
| 454 | #define UART_CTL_LOOPBACK_SHIFT 20 | |
| 455 | #define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT) | |
| 456 | #define UART_CTL_RXEN_SHIFT 21 | |
| 457 | #define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT) | |
| 458 | #define UART_CTL_TXEN_SHIFT 22 | |
| 459 | #define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT) | |
| 460 | #define UART_CTL_BRGEN_SHIFT 23 | |
| 461 | #define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT) | |
| 462 | ||
| 463 | /* UART Baudword register */ | |
| 464 | #define UART_BAUD_REG 0x4 | |
| 465 | ||
| 466 | /* UART Misc Control register */ | |
| 467 | #define UART_MCTL_REG 0x8 | |
| 468 | #define UART_MCTL_DTR_SHIFT 0 | |
| 469 | #define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT) | |
| 470 | #define UART_MCTL_RTS_SHIFT 1 | |
| 471 | #define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT) | |
| 472 | #define UART_MCTL_RXFIFOTHRESH_SHIFT 8 | |
| 473 | #define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT) | |
| 474 | #define UART_MCTL_TXFIFOTHRESH_SHIFT 12 | |
| 475 | #define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT) | |
| 476 | #define UART_MCTL_RXFIFOFILL_SHIFT 16 | |
| 477 | #define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT) | |
| 478 | #define UART_MCTL_TXFIFOFILL_SHIFT 24 | |
| 479 | #define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT) | |
| 480 | ||
| 481 | /* UART External Input Configuration register */ | |
| 482 | #define UART_EXTINP_REG 0xc | |
| 483 | #define UART_EXTINP_RI_SHIFT 0 | |
| 484 | #define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT) | |
| 485 | #define UART_EXTINP_CTS_SHIFT 1 | |
| 486 | #define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT) | |
| 487 | #define UART_EXTINP_DCD_SHIFT 2 | |
| 488 | #define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT) | |
| 489 | #define UART_EXTINP_DSR_SHIFT 3 | |
| 490 | #define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT) | |
| 491 | #define UART_EXTINP_IRSTAT(x) (1 << (x + 4)) | |
| 492 | #define UART_EXTINP_IRMASK(x) (1 << (x + 8)) | |
| 493 | #define UART_EXTINP_IR_RI 0 | |
| 494 | #define UART_EXTINP_IR_CTS 1 | |
| 495 | #define UART_EXTINP_IR_DCD 2 | |
| 496 | #define UART_EXTINP_IR_DSR 3 | |
| 497 | #define UART_EXTINP_RI_NOSENSE_SHIFT 16 | |
| 498 | #define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT) | |
| 499 | #define UART_EXTINP_CTS_NOSENSE_SHIFT 17 | |
| 500 | #define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT) | |
| 501 | #define UART_EXTINP_DCD_NOSENSE_SHIFT 18 | |
| 502 | #define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT) | |
| 503 | #define UART_EXTINP_DSR_NOSENSE_SHIFT 19 | |
| 504 | #define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT) | |
| 505 | ||
| 506 | /* UART Interrupt register */ | |
| 507 | #define UART_IR_REG 0x10 | |
| 508 | #define UART_IR_MASK(x) (1 << (x + 16)) | |
| 509 | #define UART_IR_STAT(x) (1 << (x)) | |
| 510 | #define UART_IR_EXTIP 0 | |
| 511 | #define UART_IR_TXUNDER 1 | |
| 512 | #define UART_IR_TXOVER 2 | |
| 513 | #define UART_IR_TXTRESH 3 | |
| 514 | #define UART_IR_TXRDLATCH 4 | |
| 515 | #define UART_IR_TXEMPTY 5 | |
| 516 | #define UART_IR_RXUNDER 6 | |
| 517 | #define UART_IR_RXOVER 7 | |
| 518 | #define UART_IR_RXTIMEOUT 8 | |
| 519 | #define UART_IR_RXFULL 9 | |
| 520 | #define UART_IR_RXTHRESH 10 | |
| 521 | #define UART_IR_RXNOTEMPTY 11 | |
| 522 | #define UART_IR_RXFRAMEERR 12 | |
| 523 | #define UART_IR_RXPARERR 13 | |
| 524 | #define UART_IR_RXBRK 14 | |
| 525 | #define UART_IR_TXDONE 15 | |
| 526 | ||
| 527 | /* UART Fifo register */ | |
| 528 | #define UART_FIFO_REG 0x14 | |
| 529 | #define UART_FIFO_VALID_SHIFT 0 | |
| 530 | #define UART_FIFO_VALID_MASK 0xff | |
| 531 | #define UART_FIFO_FRAMEERR_SHIFT 8 | |
| 532 | #define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT) | |
| 533 | #define UART_FIFO_PARERR_SHIFT 9 | |
| 534 | #define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT) | |
| 535 | #define UART_FIFO_BRKDET_SHIFT 10 | |
| 536 | #define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT) | |
| 537 | #define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \ | |
| 538 | UART_FIFO_PARERR_MASK | \ | |
| 539 | UART_FIFO_BRKDET_MASK) | |
| 540 | ||
| 541 | ||
| 542 | /************************************************************************* | |
| 543 | * _REG relative to RSET_GPIO | |
| 544 | *************************************************************************/ | |
| 545 | ||
| 546 | /* GPIO registers */ | |
| 547 | #define GPIO_CTL_HI_REG 0x0 | |
| 548 | #define GPIO_CTL_LO_REG 0x4 | |
| 549 | #define GPIO_DATA_HI_REG 0x8 | |
| 550 | #define GPIO_DATA_LO_REG 0xC | |
| 92d9ae20 | 551 | #define GPIO_DATA_LO_REG_6345 0x8 |
| e7300d04 MB |
552 | |
| 553 | /* GPIO mux registers and constants */ | |
| 554 | #define GPIO_MODE_REG 0x18 | |
| 555 | ||
| 556 | #define GPIO_MODE_6348_G4_DIAG 0x00090000 | |
| 557 | #define GPIO_MODE_6348_G4_UTOPIA 0x00080000 | |
| 558 | #define GPIO_MODE_6348_G4_LEGACY_LED 0x00030000 | |
| 559 | #define GPIO_MODE_6348_G4_MII_SNOOP 0x00020000 | |
| 560 | #define GPIO_MODE_6348_G4_EXT_EPHY 0x00010000 | |
| 561 | #define GPIO_MODE_6348_G3_DIAG 0x00009000 | |
| 562 | #define GPIO_MODE_6348_G3_UTOPIA 0x00008000 | |
| 563 | #define GPIO_MODE_6348_G3_EXT_MII 0x00007000 | |
| 564 | #define GPIO_MODE_6348_G2_DIAG 0x00000900 | |
| 565 | #define GPIO_MODE_6348_G2_PCI 0x00000500 | |
| 566 | #define GPIO_MODE_6348_G1_DIAG 0x00000090 | |
| 567 | #define GPIO_MODE_6348_G1_UTOPIA 0x00000080 | |
| 568 | #define GPIO_MODE_6348_G1_SPI_UART 0x00000060 | |
| 569 | #define GPIO_MODE_6348_G1_SPI_MASTER 0x00000060 | |
| 570 | #define GPIO_MODE_6348_G1_MII_PCCARD 0x00000040 | |
| 571 | #define GPIO_MODE_6348_G1_MII_SNOOP 0x00000020 | |
| 572 | #define GPIO_MODE_6348_G1_EXT_EPHY 0x00000010 | |
| 573 | #define GPIO_MODE_6348_G0_DIAG 0x00000009 | |
| 574 | #define GPIO_MODE_6348_G0_EXT_MII 0x00000007 | |
| 575 | ||
| 576 | #define GPIO_MODE_6358_EXTRACS (1 << 5) | |
| 577 | #define GPIO_MODE_6358_UART1 (1 << 6) | |
| 578 | #define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7) | |
| 579 | #define GPIO_MODE_6358_SERIAL_LED (1 << 10) | |
| 580 | #define GPIO_MODE_6358_UTOPIA (1 << 12) | |
| 581 | ||
| 04712f3f MB |
582 | #define GPIO_MODE_6368_ANALOG_AFE_0 (1 << 0) |
| 583 | #define GPIO_MODE_6368_ANALOG_AFE_1 (1 << 1) | |
| 584 | #define GPIO_MODE_6368_SYS_IRQ (1 << 2) | |
| 585 | #define GPIO_MODE_6368_SERIAL_LED_DATA (1 << 3) | |
| 586 | #define GPIO_MODE_6368_SERIAL_LED_CLK (1 << 4) | |
| 587 | #define GPIO_MODE_6368_INET_LED (1 << 5) | |
| 588 | #define GPIO_MODE_6368_EPHY0_LED (1 << 6) | |
| 589 | #define GPIO_MODE_6368_EPHY1_LED (1 << 7) | |
| 590 | #define GPIO_MODE_6368_EPHY2_LED (1 << 8) | |
| 591 | #define GPIO_MODE_6368_EPHY3_LED (1 << 9) | |
| 592 | #define GPIO_MODE_6368_ROBOSW_LED_DAT (1 << 10) | |
| 593 | #define GPIO_MODE_6368_ROBOSW_LED_CLK (1 << 11) | |
| 594 | #define GPIO_MODE_6368_ROBOSW_LED0 (1 << 12) | |
| 595 | #define GPIO_MODE_6368_ROBOSW_LED1 (1 << 13) | |
| 596 | #define GPIO_MODE_6368_USBD_LED (1 << 14) | |
| 597 | #define GPIO_MODE_6368_NTR_PULSE (1 << 15) | |
| 598 | #define GPIO_MODE_6368_PCI_REQ1 (1 << 16) | |
| 599 | #define GPIO_MODE_6368_PCI_GNT1 (1 << 17) | |
| 600 | #define GPIO_MODE_6368_PCI_INTB (1 << 18) | |
| 601 | #define GPIO_MODE_6368_PCI_REQ0 (1 << 19) | |
| 602 | #define GPIO_MODE_6368_PCI_GNT0 (1 << 20) | |
| 603 | #define GPIO_MODE_6368_PCMCIA_CD1 (1 << 22) | |
| 604 | #define GPIO_MODE_6368_PCMCIA_CD2 (1 << 23) | |
| 605 | #define GPIO_MODE_6368_PCMCIA_VS1 (1 << 24) | |
| 606 | #define GPIO_MODE_6368_PCMCIA_VS2 (1 << 25) | |
| 607 | #define GPIO_MODE_6368_EBI_CS2 (1 << 26) | |
| 608 | #define GPIO_MODE_6368_EBI_CS3 (1 << 27) | |
| 609 | #define GPIO_MODE_6368_SPI_SSN2 (1 << 28) | |
| 610 | #define GPIO_MODE_6368_SPI_SSN3 (1 << 29) | |
| 611 | #define GPIO_MODE_6368_SPI_SSN4 (1 << 30) | |
| 612 | #define GPIO_MODE_6368_SPI_SSN5 (1 << 31) | |
| 613 | ||
| 614 | ||
| 18ec0e70 | 615 | #define GPIO_PINMUX_OTHR_REG 0x24 |
| 70342287 | 616 | #define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12 |
| 18ec0e70 KC |
617 | #define GPIO_PINMUX_OTHR_6328_USB_MASK (3 << GPIO_PINMUX_OTHR_6328_USB_SHIFT) |
| 618 | #define GPIO_PINMUX_OTHR_6328_USB_HOST (1 << GPIO_PINMUX_OTHR_6328_USB_SHIFT) | |
| 619 | #define GPIO_PINMUX_OTHR_6328_USB_DEV (2 << GPIO_PINMUX_OTHR_6328_USB_SHIFT) | |
| 620 | ||
| 04712f3f MB |
621 | #define GPIO_BASEMODE_6368_REG 0x38 |
| 622 | #define GPIO_BASEMODE_6368_UART2 0x1 | |
| 623 | #define GPIO_BASEMODE_6368_GPIO 0x0 | |
| 624 | #define GPIO_BASEMODE_6368_MASK 0x7 | |
| 625 | /* those bits must be kept as read in gpio basemode register*/ | |
| e7300d04 | 626 | |
| aaf3fedb | 627 | #define GPIO_STRAPBUS_REG 0x40 |
| 70342287 | 628 | #define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1) |
| aaf3fedb JG |
629 | #define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1) |
| 630 | #define STRAPBUS_6368_BOOT_SEL_MASK 0x3 | |
| 631 | #define STRAPBUS_6368_BOOT_SEL_NAND 0 | |
| 632 | #define STRAPBUS_6368_BOOT_SEL_SERIAL 1 | |
| 70342287 | 633 | #define STRAPBUS_6368_BOOT_SEL_PARALLEL 3 |
| aaf3fedb JG |
634 | |
| 635 | ||
| e7300d04 MB |
636 | /************************************************************************* |
| 637 | * _REG relative to RSET_ENET | |
| 638 | *************************************************************************/ | |
| 639 | ||
| 640 | /* Receiver Configuration register */ | |
| 641 | #define ENET_RXCFG_REG 0x0 | |
| 642 | #define ENET_RXCFG_ALLMCAST_SHIFT 1 | |
| 643 | #define ENET_RXCFG_ALLMCAST_MASK (1 << ENET_RXCFG_ALLMCAST_SHIFT) | |
| 644 | #define ENET_RXCFG_PROMISC_SHIFT 3 | |
| 645 | #define ENET_RXCFG_PROMISC_MASK (1 << ENET_RXCFG_PROMISC_SHIFT) | |
| 646 | #define ENET_RXCFG_LOOPBACK_SHIFT 4 | |
| 647 | #define ENET_RXCFG_LOOPBACK_MASK (1 << ENET_RXCFG_LOOPBACK_SHIFT) | |
| 648 | #define ENET_RXCFG_ENFLOW_SHIFT 5 | |
| 649 | #define ENET_RXCFG_ENFLOW_MASK (1 << ENET_RXCFG_ENFLOW_SHIFT) | |
| 650 | ||
| 651 | /* Receive Maximum Length register */ | |
| 652 | #define ENET_RXMAXLEN_REG 0x4 | |
| 653 | #define ENET_RXMAXLEN_SHIFT 0 | |
| 654 | #define ENET_RXMAXLEN_MASK (0x7ff << ENET_RXMAXLEN_SHIFT) | |
| 655 | ||
| 656 | /* Transmit Maximum Length register */ | |
| 657 | #define ENET_TXMAXLEN_REG 0x8 | |
| 658 | #define ENET_TXMAXLEN_SHIFT 0 | |
| 659 | #define ENET_TXMAXLEN_MASK (0x7ff << ENET_TXMAXLEN_SHIFT) | |
| 660 | ||
| 661 | /* MII Status/Control register */ | |
| 662 | #define ENET_MIISC_REG 0x10 | |
| 663 | #define ENET_MIISC_MDCFREQDIV_SHIFT 0 | |
| 664 | #define ENET_MIISC_MDCFREQDIV_MASK (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT) | |
| 665 | #define ENET_MIISC_PREAMBLEEN_SHIFT 7 | |
| 666 | #define ENET_MIISC_PREAMBLEEN_MASK (1 << ENET_MIISC_PREAMBLEEN_SHIFT) | |
| 667 | ||
| 668 | /* MII Data register */ | |
| 669 | #define ENET_MIIDATA_REG 0x14 | |
| 670 | #define ENET_MIIDATA_DATA_SHIFT 0 | |
| 671 | #define ENET_MIIDATA_DATA_MASK (0xffff << ENET_MIIDATA_DATA_SHIFT) | |
| 672 | #define ENET_MIIDATA_TA_SHIFT 16 | |
| 673 | #define ENET_MIIDATA_TA_MASK (0x3 << ENET_MIIDATA_TA_SHIFT) | |
| 674 | #define ENET_MIIDATA_REG_SHIFT 18 | |
| 675 | #define ENET_MIIDATA_REG_MASK (0x1f << ENET_MIIDATA_REG_SHIFT) | |
| 676 | #define ENET_MIIDATA_PHYID_SHIFT 23 | |
| 677 | #define ENET_MIIDATA_PHYID_MASK (0x1f << ENET_MIIDATA_PHYID_SHIFT) | |
| 678 | #define ENET_MIIDATA_OP_READ_MASK (0x6 << 28) | |
| 679 | #define ENET_MIIDATA_OP_WRITE_MASK (0x5 << 28) | |
| 680 | ||
| 681 | /* Ethernet Interrupt Mask register */ | |
| 682 | #define ENET_IRMASK_REG 0x18 | |
| 683 | ||
| 684 | /* Ethernet Interrupt register */ | |
| 685 | #define ENET_IR_REG 0x1c | |
| 686 | #define ENET_IR_MII (1 << 0) | |
| 687 | #define ENET_IR_MIB (1 << 1) | |
| 688 | #define ENET_IR_FLOWC (1 << 2) | |
| 689 | ||
| 690 | /* Ethernet Control register */ | |
| 691 | #define ENET_CTL_REG 0x2c | |
| 692 | #define ENET_CTL_ENABLE_SHIFT 0 | |
| 693 | #define ENET_CTL_ENABLE_MASK (1 << ENET_CTL_ENABLE_SHIFT) | |
| 694 | #define ENET_CTL_DISABLE_SHIFT 1 | |
| 695 | #define ENET_CTL_DISABLE_MASK (1 << ENET_CTL_DISABLE_SHIFT) | |
| 696 | #define ENET_CTL_SRESET_SHIFT 2 | |
| 697 | #define ENET_CTL_SRESET_MASK (1 << ENET_CTL_SRESET_SHIFT) | |
| 698 | #define ENET_CTL_EPHYSEL_SHIFT 3 | |
| 699 | #define ENET_CTL_EPHYSEL_MASK (1 << ENET_CTL_EPHYSEL_SHIFT) | |
| 700 | ||
| 701 | /* Transmit Control register */ | |
| 702 | #define ENET_TXCTL_REG 0x30 | |
| 703 | #define ENET_TXCTL_FD_SHIFT 0 | |
| 704 | #define ENET_TXCTL_FD_MASK (1 << ENET_TXCTL_FD_SHIFT) | |
| 705 | ||
| 706 | /* Transmit Watermask register */ | |
| 707 | #define ENET_TXWMARK_REG 0x34 | |
| 708 | #define ENET_TXWMARK_WM_SHIFT 0 | |
| 709 | #define ENET_TXWMARK_WM_MASK (0x3f << ENET_TXWMARK_WM_SHIFT) | |
| 710 | ||
| 711 | /* MIB Control register */ | |
| 712 | #define ENET_MIBCTL_REG 0x38 | |
| 713 | #define ENET_MIBCTL_RDCLEAR_SHIFT 0 | |
| 714 | #define ENET_MIBCTL_RDCLEAR_MASK (1 << ENET_MIBCTL_RDCLEAR_SHIFT) | |
| 715 | ||
| 716 | /* Perfect Match Data Low register */ | |
| 717 | #define ENET_PML_REG(x) (0x58 + (x) * 8) | |
| 718 | #define ENET_PMH_REG(x) (0x5c + (x) * 8) | |
| 719 | #define ENET_PMH_DATAVALID_SHIFT 16 | |
| 720 | #define ENET_PMH_DATAVALID_MASK (1 << ENET_PMH_DATAVALID_SHIFT) | |
| 721 | ||
| 722 | /* MIB register */ | |
| 723 | #define ENET_MIB_REG(x) (0x200 + (x) * 4) | |
| 724 | #define ENET_MIB_REG_COUNT 55 | |
| 725 | ||
| 726 | ||
| 727 | /************************************************************************* | |
| 728 | * _REG relative to RSET_ENETDMA | |
| 729 | *************************************************************************/ | |
| 730 | ||
| 731 | /* Controller Configuration Register */ | |
| 732 | #define ENETDMA_CFG_REG (0x0) | |
| 733 | #define ENETDMA_CFG_EN_SHIFT 0 | |
| 734 | #define ENETDMA_CFG_EN_MASK (1 << ENETDMA_CFG_EN_SHIFT) | |
| 735 | #define ENETDMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1)) | |
| 736 | ||
| 737 | /* Flow Control Descriptor Low Threshold register */ | |
| 738 | #define ENETDMA_FLOWCL_REG(x) (0x4 + (x) * 6) | |
| 739 | ||
| 740 | /* Flow Control Descriptor High Threshold register */ | |
| 741 | #define ENETDMA_FLOWCH_REG(x) (0x8 + (x) * 6) | |
| 742 | ||
| 743 | /* Flow Control Descriptor Buffer Alloca Threshold register */ | |
| 744 | #define ENETDMA_BUFALLOC_REG(x) (0xc + (x) * 6) | |
| 745 | #define ENETDMA_BUFALLOC_FORCE_SHIFT 31 | |
| 746 | #define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT) | |
| 747 | ||
| 6f942345 KC |
748 | /* Global interrupt status */ |
| 749 | #define ENETDMA_GLB_IRQSTAT_REG (0x40) | |
| 750 | ||
| 751 | /* Global interrupt mask */ | |
| 752 | #define ENETDMA_GLB_IRQMASK_REG (0x44) | |
| 753 | ||
| e7300d04 MB |
754 | /* Channel Configuration register */ |
| 755 | #define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10) | |
| 756 | #define ENETDMA_CHANCFG_EN_SHIFT 0 | |
| 757 | #define ENETDMA_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT) | |
| 758 | #define ENETDMA_CHANCFG_PKTHALT_SHIFT 1 | |
| 759 | #define ENETDMA_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT) | |
| 760 | ||
| 761 | /* Interrupt Control/Status register */ | |
| 762 | #define ENETDMA_IR_REG(x) (0x104 + (x) * 0x10) | |
| 763 | #define ENETDMA_IR_BUFDONE_MASK (1 << 0) | |
| 764 | #define ENETDMA_IR_PKTDONE_MASK (1 << 1) | |
| 765 | #define ENETDMA_IR_NOTOWNER_MASK (1 << 2) | |
| 766 | ||
| 767 | /* Interrupt Mask register */ | |
| 768 | #define ENETDMA_IRMASK_REG(x) (0x108 + (x) * 0x10) | |
| 769 | ||
| 770 | /* Maximum Burst Length */ | |
| 771 | #define ENETDMA_MAXBURST_REG(x) (0x10C + (x) * 0x10) | |
| 772 | ||
| 773 | /* Ring Start Address register */ | |
| 774 | #define ENETDMA_RSTART_REG(x) (0x200 + (x) * 0x10) | |
| 775 | ||
| 776 | /* State Ram Word 2 */ | |
| 777 | #define ENETDMA_SRAM2_REG(x) (0x204 + (x) * 0x10) | |
| 778 | ||
| 779 | /* State Ram Word 3 */ | |
| 780 | #define ENETDMA_SRAM3_REG(x) (0x208 + (x) * 0x10) | |
| 781 | ||
| 782 | /* State Ram Word 4 */ | |
| 783 | #define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10) | |
| 784 | ||
| 785 | ||
| d430b6c5 MB |
786 | /************************************************************************* |
| 787 | * _REG relative to RSET_ENETDMAC | |
| 788 | *************************************************************************/ | |
| 789 | ||
| 790 | /* Channel Configuration register */ | |
| 791 | #define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10) | |
| 792 | #define ENETDMAC_CHANCFG_EN_SHIFT 0 | |
| 6f942345 | 793 | #define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMAC_CHANCFG_EN_SHIFT) |
| d430b6c5 | 794 | #define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1 |
| 6f942345 KC |
795 | #define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT) |
| 796 | #define ENETDMAC_CHANCFG_BUFHALT_SHIFT 2 | |
| 797 | #define ENETDMAC_CHANCFG_BUFHALT_MASK (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT) | |
| d430b6c5 MB |
798 | |
| 799 | /* Interrupt Control/Status register */ | |
| 800 | #define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10) | |
| 801 | #define ENETDMAC_IR_BUFDONE_MASK (1 << 0) | |
| 802 | #define ENETDMAC_IR_PKTDONE_MASK (1 << 1) | |
| 803 | #define ENETDMAC_IR_NOTOWNER_MASK (1 << 2) | |
| 804 | ||
| 805 | /* Interrupt Mask register */ | |
| 806 | #define ENETDMAC_IRMASK_REG(x) (0x8 + (x) * 0x10) | |
| 807 | ||
| 808 | /* Maximum Burst Length */ | |
| 809 | #define ENETDMAC_MAXBURST_REG(x) (0xc + (x) * 0x10) | |
| 810 | ||
| 811 | ||
| 812 | /************************************************************************* | |
| 813 | * _REG relative to RSET_ENETDMAS | |
| 814 | *************************************************************************/ | |
| 815 | ||
| 816 | /* Ring Start Address register */ | |
| 817 | #define ENETDMAS_RSTART_REG(x) ((x) * 0x10) | |
| 818 | ||
| 819 | /* State Ram Word 2 */ | |
| 820 | #define ENETDMAS_SRAM2_REG(x) (0x4 + (x) * 0x10) | |
| 821 | ||
| 822 | /* State Ram Word 3 */ | |
| 823 | #define ENETDMAS_SRAM3_REG(x) (0x8 + (x) * 0x10) | |
| 824 | ||
| 825 | /* State Ram Word 4 */ | |
| 826 | #define ENETDMAS_SRAM4_REG(x) (0xc + (x) * 0x10) | |
| 827 | ||
| 828 | ||
| 829 | /************************************************************************* | |
| 830 | * _REG relative to RSET_ENETSW | |
| 831 | *************************************************************************/ | |
| 832 | ||
| 833 | /* MIB register */ | |
| 834 | #define ENETSW_MIB_REG(x) (0x2800 + (x) * 4) | |
| 835 | #define ENETSW_MIB_REG_COUNT 47 | |
| 836 | ||
| 837 | ||
| e7300d04 MB |
838 | /************************************************************************* |
| 839 | * _REG relative to RSET_OHCI_PRIV | |
| 840 | *************************************************************************/ | |
| 841 | ||
| 842 | #define OHCI_PRIV_REG 0x0 | |
| 843 | #define OHCI_PRIV_PORT1_HOST_SHIFT 0 | |
| 844 | #define OHCI_PRIV_PORT1_HOST_MASK (1 << OHCI_PRIV_PORT1_HOST_SHIFT) | |
| 845 | #define OHCI_PRIV_REG_SWAP_SHIFT 3 | |
| 846 | #define OHCI_PRIV_REG_SWAP_MASK (1 << OHCI_PRIV_REG_SWAP_SHIFT) | |
| 847 | ||
| 848 | ||
| 849 | /************************************************************************* | |
| 850 | * _REG relative to RSET_USBH_PRIV | |
| 851 | *************************************************************************/ | |
| 852 | ||
| 04712f3f MB |
853 | #define USBH_PRIV_SWAP_6358_REG 0x0 |
| 854 | #define USBH_PRIV_SWAP_6368_REG 0x1c | |
| 855 | ||
| 18ec0e70 KC |
856 | #define USBH_PRIV_SWAP_USBD_SHIFT 6 |
| 857 | #define USBH_PRIV_SWAP_USBD_MASK (1 << USBH_PRIV_SWAP_USBD_SHIFT) | |
| e7300d04 MB |
858 | #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4 |
| 859 | #define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT) | |
| 860 | #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3 | |
| 861 | #define USBH_PRIV_SWAP_EHCI_DATA_MASK (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT) | |
| 862 | #define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT 1 | |
| 863 | #define USBH_PRIV_SWAP_OHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT) | |
| 864 | #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0 | |
| 865 | #define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT) | |
| 866 | ||
| 5fd66c2b | 867 | #define USBH_PRIV_UTMI_CTL_6368_REG 0x10 |
| 70342287 | 868 | #define USBH_PRIV_UTMI_CTL_NODRIV_SHIFT 12 |
| 5fd66c2b KC |
869 | #define USBH_PRIV_UTMI_CTL_NODRIV_MASK (0xf << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT) |
| 870 | #define USBH_PRIV_UTMI_CTL_HOSTB_SHIFT 0 | |
| 871 | #define USBH_PRIV_UTMI_CTL_HOSTB_MASK (0xf << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT) | |
| 872 | ||
| 04712f3f MB |
873 | #define USBH_PRIV_TEST_6358_REG 0x24 |
| 874 | #define USBH_PRIV_TEST_6368_REG 0x14 | |
| 875 | ||
| 876 | #define USBH_PRIV_SETUP_6368_REG 0x28 | |
| 877 | #define USBH_PRIV_SETUP_IOC_SHIFT 4 | |
| 878 | #define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT) | |
| 879 | ||
| e7300d04 | 880 | |
| 5fd66c2b KC |
881 | /************************************************************************* |
| 882 | * _REG relative to RSET_USBD | |
| 883 | *************************************************************************/ | |
| 884 | ||
| 885 | /* General control */ | |
| 886 | #define USBD_CONTROL_REG 0x00 | |
| 887 | #define USBD_CONTROL_TXZLENINS_SHIFT 14 | |
| 888 | #define USBD_CONTROL_TXZLENINS_MASK (1 << USBD_CONTROL_TXZLENINS_SHIFT) | |
| 889 | #define USBD_CONTROL_AUTO_CSRS_SHIFT 13 | |
| 890 | #define USBD_CONTROL_AUTO_CSRS_MASK (1 << USBD_CONTROL_AUTO_CSRS_SHIFT) | |
| 891 | #define USBD_CONTROL_RXZSCFG_SHIFT 12 | |
| 892 | #define USBD_CONTROL_RXZSCFG_MASK (1 << USBD_CONTROL_RXZSCFG_SHIFT) | |
| 893 | #define USBD_CONTROL_INIT_SEL_SHIFT 8 | |
| 894 | #define USBD_CONTROL_INIT_SEL_MASK (0xf << USBD_CONTROL_INIT_SEL_SHIFT) | |
| 895 | #define USBD_CONTROL_FIFO_RESET_SHIFT 6 | |
| 896 | #define USBD_CONTROL_FIFO_RESET_MASK (3 << USBD_CONTROL_FIFO_RESET_SHIFT) | |
| 70342287 | 897 | #define USBD_CONTROL_SETUPERRLOCK_SHIFT 5 |
| 5fd66c2b KC |
898 | #define USBD_CONTROL_SETUPERRLOCK_MASK (1 << USBD_CONTROL_SETUPERRLOCK_SHIFT) |
| 899 | #define USBD_CONTROL_DONE_CSRS_SHIFT 0 | |
| 900 | #define USBD_CONTROL_DONE_CSRS_MASK (1 << USBD_CONTROL_DONE_CSRS_SHIFT) | |
| 901 | ||
| 902 | /* Strap options */ | |
| 903 | #define USBD_STRAPS_REG 0x04 | |
| 904 | #define USBD_STRAPS_APP_SELF_PWR_SHIFT 10 | |
| 905 | #define USBD_STRAPS_APP_SELF_PWR_MASK (1 << USBD_STRAPS_APP_SELF_PWR_SHIFT) | |
| 906 | #define USBD_STRAPS_APP_DISCON_SHIFT 9 | |
| 907 | #define USBD_STRAPS_APP_DISCON_MASK (1 << USBD_STRAPS_APP_DISCON_SHIFT) | |
| 70342287 | 908 | #define USBD_STRAPS_APP_CSRPRGSUP_SHIFT 8 |
| 5fd66c2b KC |
909 | #define USBD_STRAPS_APP_CSRPRGSUP_MASK (1 << USBD_STRAPS_APP_CSRPRGSUP_SHIFT) |
| 910 | #define USBD_STRAPS_APP_RMTWKUP_SHIFT 6 | |
| 911 | #define USBD_STRAPS_APP_RMTWKUP_MASK (1 << USBD_STRAPS_APP_RMTWKUP_SHIFT) | |
| 912 | #define USBD_STRAPS_APP_RAM_IF_SHIFT 7 | |
| 913 | #define USBD_STRAPS_APP_RAM_IF_MASK (1 << USBD_STRAPS_APP_RAM_IF_SHIFT) | |
| 914 | #define USBD_STRAPS_APP_8BITPHY_SHIFT 2 | |
| 915 | #define USBD_STRAPS_APP_8BITPHY_MASK (1 << USBD_STRAPS_APP_8BITPHY_SHIFT) | |
| 916 | #define USBD_STRAPS_SPEED_SHIFT 0 | |
| 917 | #define USBD_STRAPS_SPEED_MASK (3 << USBD_STRAPS_SPEED_SHIFT) | |
| 918 | ||
| 919 | /* Stall control */ | |
| 920 | #define USBD_STALL_REG 0x08 | |
| 921 | #define USBD_STALL_UPDATE_SHIFT 7 | |
| 922 | #define USBD_STALL_UPDATE_MASK (1 << USBD_STALL_UPDATE_SHIFT) | |
| 923 | #define USBD_STALL_ENABLE_SHIFT 6 | |
| 924 | #define USBD_STALL_ENABLE_MASK (1 << USBD_STALL_ENABLE_SHIFT) | |
| 925 | #define USBD_STALL_EPNUM_SHIFT 0 | |
| 926 | #define USBD_STALL_EPNUM_MASK (0xf << USBD_STALL_EPNUM_SHIFT) | |
| 927 | ||
| 928 | /* General status */ | |
| 929 | #define USBD_STATUS_REG 0x0c | |
| 930 | #define USBD_STATUS_SOF_SHIFT 16 | |
| 931 | #define USBD_STATUS_SOF_MASK (0x7ff << USBD_STATUS_SOF_SHIFT) | |
| 932 | #define USBD_STATUS_SPD_SHIFT 12 | |
| 933 | #define USBD_STATUS_SPD_MASK (3 << USBD_STATUS_SPD_SHIFT) | |
| 934 | #define USBD_STATUS_ALTINTF_SHIFT 8 | |
| 935 | #define USBD_STATUS_ALTINTF_MASK (0xf << USBD_STATUS_ALTINTF_SHIFT) | |
| 936 | #define USBD_STATUS_INTF_SHIFT 4 | |
| 937 | #define USBD_STATUS_INTF_MASK (0xf << USBD_STATUS_INTF_SHIFT) | |
| 938 | #define USBD_STATUS_CFG_SHIFT 0 | |
| 939 | #define USBD_STATUS_CFG_MASK (0xf << USBD_STATUS_CFG_SHIFT) | |
| 940 | ||
| 941 | /* Other events */ | |
| 942 | #define USBD_EVENTS_REG 0x10 | |
| 943 | #define USBD_EVENTS_USB_LINK_SHIFT 10 | |
| 944 | #define USBD_EVENTS_USB_LINK_MASK (1 << USBD_EVENTS_USB_LINK_SHIFT) | |
| 945 | ||
| 946 | /* IRQ status */ | |
| 947 | #define USBD_EVENT_IRQ_STATUS_REG 0x14 | |
| 948 | ||
| 949 | /* IRQ level (2 bits per IRQ event) */ | |
| 950 | #define USBD_EVENT_IRQ_CFG_HI_REG 0x18 | |
| 951 | ||
| 952 | #define USBD_EVENT_IRQ_CFG_LO_REG 0x1c | |
| 953 | ||
| 954 | #define USBD_EVENT_IRQ_CFG_SHIFT(x) ((x & 0xf) << 1) | |
| 955 | #define USBD_EVENT_IRQ_CFG_MASK(x) (3 << USBD_EVENT_IRQ_CFG_SHIFT(x)) | |
| 956 | #define USBD_EVENT_IRQ_CFG_RISING(x) (0 << USBD_EVENT_IRQ_CFG_SHIFT(x)) | |
| 957 | #define USBD_EVENT_IRQ_CFG_FALLING(x) (1 << USBD_EVENT_IRQ_CFG_SHIFT(x)) | |
| 958 | ||
| 959 | /* IRQ mask (1=unmasked) */ | |
| 960 | #define USBD_EVENT_IRQ_MASK_REG 0x20 | |
| 961 | ||
| 962 | /* IRQ bits */ | |
| 963 | #define USBD_EVENT_IRQ_USB_LINK 10 | |
| 964 | #define USBD_EVENT_IRQ_SETCFG 9 | |
| 965 | #define USBD_EVENT_IRQ_SETINTF 8 | |
| 966 | #define USBD_EVENT_IRQ_ERRATIC_ERR 7 | |
| 967 | #define USBD_EVENT_IRQ_SET_CSRS 6 | |
| 968 | #define USBD_EVENT_IRQ_SUSPEND 5 | |
| 969 | #define USBD_EVENT_IRQ_EARLY_SUSPEND 4 | |
| 970 | #define USBD_EVENT_IRQ_SOF 3 | |
| 971 | #define USBD_EVENT_IRQ_ENUM_ON 2 | |
| 972 | #define USBD_EVENT_IRQ_SETUP 1 | |
| 973 | #define USBD_EVENT_IRQ_USB_RESET 0 | |
| 974 | ||
| 975 | /* TX FIFO partitioning */ | |
| 976 | #define USBD_TXFIFO_CONFIG_REG 0x40 | |
| 977 | #define USBD_TXFIFO_CONFIG_END_SHIFT 16 | |
| 978 | #define USBD_TXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT) | |
| 979 | #define USBD_TXFIFO_CONFIG_START_SHIFT 0 | |
| 980 | #define USBD_TXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT) | |
| 981 | ||
| 982 | /* RX FIFO partitioning */ | |
| 983 | #define USBD_RXFIFO_CONFIG_REG 0x44 | |
| 984 | #define USBD_RXFIFO_CONFIG_END_SHIFT 16 | |
| 985 | #define USBD_RXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT) | |
| 986 | #define USBD_RXFIFO_CONFIG_START_SHIFT 0 | |
| 987 | #define USBD_RXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT) | |
| 988 | ||
| 989 | /* TX FIFO/endpoint configuration */ | |
| 990 | #define USBD_TXFIFO_EPSIZE_REG 0x48 | |
| 991 | ||
| 992 | /* RX FIFO/endpoint configuration */ | |
| 993 | #define USBD_RXFIFO_EPSIZE_REG 0x4c | |
| 994 | ||
| 995 | /* Endpoint<->DMA mappings */ | |
| 996 | #define USBD_EPNUM_TYPEMAP_REG 0x50 | |
| 997 | #define USBD_EPNUM_TYPEMAP_TYPE_SHIFT 8 | |
| 998 | #define USBD_EPNUM_TYPEMAP_TYPE_MASK (0x3 << USBD_EPNUM_TYPEMAP_TYPE_SHIFT) | |
| 70342287 | 999 | #define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT 0 |
| 5fd66c2b KC |
1000 | #define USBD_EPNUM_TYPEMAP_DMA_CH_MASK (0xf << USBD_EPNUM_TYPEMAP_DMACH_SHIFT) |
| 1001 | ||
| 1002 | /* Misc per-endpoint settings */ | |
| 1003 | #define USBD_CSR_SETUPADDR_REG 0x80 | |
| 1004 | #define USBD_CSR_SETUPADDR_DEF 0xb550 | |
| 1005 | ||
| 1006 | #define USBD_CSR_EP_REG(x) (0x84 + (x) * 4) | |
| 1007 | #define USBD_CSR_EP_MAXPKT_SHIFT 19 | |
| 1008 | #define USBD_CSR_EP_MAXPKT_MASK (0x7ff << USBD_CSR_EP_MAXPKT_SHIFT) | |
| 1009 | #define USBD_CSR_EP_ALTIFACE_SHIFT 15 | |
| 1010 | #define USBD_CSR_EP_ALTIFACE_MASK (0xf << USBD_CSR_EP_ALTIFACE_SHIFT) | |
| 1011 | #define USBD_CSR_EP_IFACE_SHIFT 11 | |
| 1012 | #define USBD_CSR_EP_IFACE_MASK (0xf << USBD_CSR_EP_IFACE_SHIFT) | |
| 1013 | #define USBD_CSR_EP_CFG_SHIFT 7 | |
| 1014 | #define USBD_CSR_EP_CFG_MASK (0xf << USBD_CSR_EP_CFG_SHIFT) | |
| 1015 | #define USBD_CSR_EP_TYPE_SHIFT 5 | |
| 1016 | #define USBD_CSR_EP_TYPE_MASK (3 << USBD_CSR_EP_TYPE_SHIFT) | |
| 1017 | #define USBD_CSR_EP_DIR_SHIFT 4 | |
| 1018 | #define USBD_CSR_EP_DIR_MASK (1 << USBD_CSR_EP_DIR_SHIFT) | |
| 1019 | #define USBD_CSR_EP_LOG_SHIFT 0 | |
| 1020 | #define USBD_CSR_EP_LOG_MASK (0xf << USBD_CSR_EP_LOG_SHIFT) | |
| 1021 | ||
| e7300d04 MB |
1022 | |
| 1023 | /************************************************************************* | |
| 1024 | * _REG relative to RSET_MPI | |
| 1025 | *************************************************************************/ | |
| 1026 | ||
| 1027 | /* well known (hard wired) chip select */ | |
| 1028 | #define MPI_CS_PCMCIA_COMMON 4 | |
| 1029 | #define MPI_CS_PCMCIA_ATTR 5 | |
| 1030 | #define MPI_CS_PCMCIA_IO 6 | |
| 1031 | ||
| 1032 | /* Chip select base register */ | |
| 1033 | #define MPI_CSBASE_REG(x) (0x0 + (x) * 8) | |
| 1034 | #define MPI_CSBASE_BASE_SHIFT 13 | |
| 1035 | #define MPI_CSBASE_BASE_MASK (0x1ffff << MPI_CSBASE_BASE_SHIFT) | |
| 1036 | #define MPI_CSBASE_SIZE_SHIFT 0 | |
| 1037 | #define MPI_CSBASE_SIZE_MASK (0xf << MPI_CSBASE_SIZE_SHIFT) | |
| 1038 | ||
| 1039 | #define MPI_CSBASE_SIZE_8K 0 | |
| 1040 | #define MPI_CSBASE_SIZE_16K 1 | |
| 1041 | #define MPI_CSBASE_SIZE_32K 2 | |
| 1042 | #define MPI_CSBASE_SIZE_64K 3 | |
| 1043 | #define MPI_CSBASE_SIZE_128K 4 | |
| 1044 | #define MPI_CSBASE_SIZE_256K 5 | |
| 1045 | #define MPI_CSBASE_SIZE_512K 6 | |
| 1046 | #define MPI_CSBASE_SIZE_1M 7 | |
| 1047 | #define MPI_CSBASE_SIZE_2M 8 | |
| 1048 | #define MPI_CSBASE_SIZE_4M 9 | |
| 1049 | #define MPI_CSBASE_SIZE_8M 10 | |
| 1050 | #define MPI_CSBASE_SIZE_16M 11 | |
| 1051 | #define MPI_CSBASE_SIZE_32M 12 | |
| 1052 | #define MPI_CSBASE_SIZE_64M 13 | |
| 1053 | #define MPI_CSBASE_SIZE_128M 14 | |
| 1054 | #define MPI_CSBASE_SIZE_256M 15 | |
| 1055 | ||
| 1056 | /* Chip select control register */ | |
| 1057 | #define MPI_CSCTL_REG(x) (0x4 + (x) * 8) | |
| 1058 | #define MPI_CSCTL_ENABLE_MASK (1 << 0) | |
| 1059 | #define MPI_CSCTL_WAIT_SHIFT 1 | |
| 1060 | #define MPI_CSCTL_WAIT_MASK (0x7 << MPI_CSCTL_WAIT_SHIFT) | |
| 1061 | #define MPI_CSCTL_DATA16_MASK (1 << 4) | |
| 1062 | #define MPI_CSCTL_SYNCMODE_MASK (1 << 7) | |
| 1063 | #define MPI_CSCTL_TSIZE_MASK (1 << 8) | |
| 1064 | #define MPI_CSCTL_ENDIANSWAP_MASK (1 << 10) | |
| 1065 | #define MPI_CSCTL_SETUP_SHIFT 16 | |
| 1066 | #define MPI_CSCTL_SETUP_MASK (0xf << MPI_CSCTL_SETUP_SHIFT) | |
| 1067 | #define MPI_CSCTL_HOLD_SHIFT 20 | |
| 1068 | #define MPI_CSCTL_HOLD_MASK (0xf << MPI_CSCTL_HOLD_SHIFT) | |
| 1069 | ||
| 1070 | /* PCI registers */ | |
| 1071 | #define MPI_SP0_RANGE_REG 0x100 | |
| 1072 | #define MPI_SP0_REMAP_REG 0x104 | |
| 1073 | #define MPI_SP0_REMAP_ENABLE_MASK (1 << 0) | |
| 1074 | #define MPI_SP1_RANGE_REG 0x10C | |
| 1075 | #define MPI_SP1_REMAP_REG 0x110 | |
| 1076 | #define MPI_SP1_REMAP_ENABLE_MASK (1 << 0) | |
| 1077 | ||
| 1078 | #define MPI_L2PCFG_REG 0x11C | |
| 1079 | #define MPI_L2PCFG_CFG_TYPE_SHIFT 0 | |
| 1080 | #define MPI_L2PCFG_CFG_TYPE_MASK (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT) | |
| 1081 | #define MPI_L2PCFG_REG_SHIFT 2 | |
| 1082 | #define MPI_L2PCFG_REG_MASK (0x3f << MPI_L2PCFG_REG_SHIFT) | |
| 1083 | #define MPI_L2PCFG_FUNC_SHIFT 8 | |
| 1084 | #define MPI_L2PCFG_FUNC_MASK (0x7 << MPI_L2PCFG_FUNC_SHIFT) | |
| 1085 | #define MPI_L2PCFG_DEVNUM_SHIFT 11 | |
| 1086 | #define MPI_L2PCFG_DEVNUM_MASK (0x1f << MPI_L2PCFG_DEVNUM_SHIFT) | |
| 1087 | #define MPI_L2PCFG_CFG_USEREG_MASK (1 << 30) | |
| 1088 | #define MPI_L2PCFG_CFG_SEL_MASK (1 << 31) | |
| 1089 | ||
| 1090 | #define MPI_L2PMEMRANGE1_REG 0x120 | |
| 1091 | #define MPI_L2PMEMBASE1_REG 0x124 | |
| 1092 | #define MPI_L2PMEMREMAP1_REG 0x128 | |
| 1093 | #define MPI_L2PMEMRANGE2_REG 0x12C | |
| 1094 | #define MPI_L2PMEMBASE2_REG 0x130 | |
| 1095 | #define MPI_L2PMEMREMAP2_REG 0x134 | |
| 1096 | #define MPI_L2PIORANGE_REG 0x138 | |
| 1097 | #define MPI_L2PIOBASE_REG 0x13C | |
| 1098 | #define MPI_L2PIOREMAP_REG 0x140 | |
| 1099 | #define MPI_L2P_BASE_MASK (0xffff8000) | |
| 1100 | #define MPI_L2PREMAP_ENABLED_MASK (1 << 0) | |
| 1101 | #define MPI_L2PREMAP_IS_CARDBUS_MASK (1 << 2) | |
| 1102 | ||
| 1103 | #define MPI_PCIMODESEL_REG 0x144 | |
| 70342287 RB |
1104 | #define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0) |
| 1105 | #define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1) | |
| e7300d04 MB |
1106 | #define MPI_PCIMODESEL_EXT_ARB_MASK (1 << 2) |
| 1107 | #define MPI_PCIMODESEL_PREFETCH_SHIFT 4 | |
| 1108 | #define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT) | |
| 1109 | ||
| 1110 | #define MPI_LOCBUSCTL_REG 0x14C | |
| 1111 | #define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0) | |
| 1112 | #define MPI_LOCBUSCTL_U2P_NOSWAP_MASK (1 << 1) | |
| 1113 | ||
| 1114 | #define MPI_LOCINT_REG 0x150 | |
| 1115 | #define MPI_LOCINT_MASK(x) (1 << (x + 16)) | |
| 1116 | #define MPI_LOCINT_STAT(x) (1 << (x)) | |
| 1117 | #define MPI_LOCINT_DIR_FAILED 6 | |
| 1118 | #define MPI_LOCINT_EXT_PCI_INT 7 | |
| 1119 | #define MPI_LOCINT_SERR 8 | |
| 1120 | #define MPI_LOCINT_CSERR 9 | |
| 1121 | ||
| 1122 | #define MPI_PCICFGCTL_REG 0x178 | |
| 1123 | #define MPI_PCICFGCTL_CFGADDR_SHIFT 2 | |
| 1124 | #define MPI_PCICFGCTL_CFGADDR_MASK (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT) | |
| 1125 | #define MPI_PCICFGCTL_WRITEEN_MASK (1 << 7) | |
| 1126 | ||
| 1127 | #define MPI_PCICFGDATA_REG 0x17C | |
| 1128 | ||
| 1129 | /* PCI host bridge custom register */ | |
| 1130 | #define BCMPCI_REG_TIMERS 0x40 | |
| 1131 | #define REG_TIMER_TRDY_SHIFT 0 | |
| 1132 | #define REG_TIMER_TRDY_MASK (0xff << REG_TIMER_TRDY_SHIFT) | |
| 1133 | #define REG_TIMER_RETRY_SHIFT 8 | |
| 1134 | #define REG_TIMER_RETRY_MASK (0xff << REG_TIMER_RETRY_SHIFT) | |
| 1135 | ||
| 1136 | ||
| 1137 | /************************************************************************* | |
| 1138 | * _REG relative to RSET_PCMCIA | |
| 1139 | *************************************************************************/ | |
| 1140 | ||
| 1141 | #define PCMCIA_C1_REG 0x0 | |
| 1142 | #define PCMCIA_C1_CD1_MASK (1 << 0) | |
| 1143 | #define PCMCIA_C1_CD2_MASK (1 << 1) | |
| 1144 | #define PCMCIA_C1_VS1_MASK (1 << 2) | |
| 1145 | #define PCMCIA_C1_VS2_MASK (1 << 3) | |
| 1146 | #define PCMCIA_C1_VS1OE_MASK (1 << 6) | |
| 1147 | #define PCMCIA_C1_VS2OE_MASK (1 << 7) | |
| 1148 | #define PCMCIA_C1_CBIDSEL_SHIFT (8) | |
| 1149 | #define PCMCIA_C1_CBIDSEL_MASK (0x1f << PCMCIA_C1_CBIDSEL_SHIFT) | |
| 1150 | #define PCMCIA_C1_EN_PCMCIA_GPIO_MASK (1 << 13) | |
| 1151 | #define PCMCIA_C1_EN_PCMCIA_MASK (1 << 14) | |
| 1152 | #define PCMCIA_C1_EN_CARDBUS_MASK (1 << 15) | |
| 1153 | #define PCMCIA_C1_RESET_MASK (1 << 18) | |
| 1154 | ||
| 1155 | #define PCMCIA_C2_REG 0x8 | |
| 1156 | #define PCMCIA_C2_DATA16_MASK (1 << 0) | |
| 1157 | #define PCMCIA_C2_BYTESWAP_MASK (1 << 1) | |
| 1158 | #define PCMCIA_C2_RWCOUNT_SHIFT 2 | |
| 1159 | #define PCMCIA_C2_RWCOUNT_MASK (0x3f << PCMCIA_C2_RWCOUNT_SHIFT) | |
| 1160 | #define PCMCIA_C2_INACTIVE_SHIFT 8 | |
| 1161 | #define PCMCIA_C2_INACTIVE_MASK (0x3f << PCMCIA_C2_INACTIVE_SHIFT) | |
| 1162 | #define PCMCIA_C2_SETUP_SHIFT 16 | |
| 1163 | #define PCMCIA_C2_SETUP_MASK (0x3f << PCMCIA_C2_SETUP_SHIFT) | |
| 1164 | #define PCMCIA_C2_HOLD_SHIFT 24 | |
| 1165 | #define PCMCIA_C2_HOLD_MASK (0x3f << PCMCIA_C2_HOLD_SHIFT) | |
| 1166 | ||
| 1167 | ||
| 1168 | /************************************************************************* | |
| 1169 | * _REG relative to RSET_SDRAM | |
| 1170 | *************************************************************************/ | |
| 1171 | ||
| 1172 | #define SDRAM_CFG_REG 0x0 | |
| 1173 | #define SDRAM_CFG_ROW_SHIFT 4 | |
| 1174 | #define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT) | |
| 1175 | #define SDRAM_CFG_COL_SHIFT 6 | |
| 1176 | #define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT) | |
| 1177 | #define SDRAM_CFG_32B_SHIFT 10 | |
| 1178 | #define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT) | |
| 1179 | #define SDRAM_CFG_BANK_SHIFT 13 | |
| 1180 | #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT) | |
| 1181 | ||
| d61fcfe2 FF |
1182 | #define SDRAM_MBASE_REG 0xc |
| 1183 | ||
| e7300d04 MB |
1184 | #define SDRAM_PRIO_REG 0x2C |
| 1185 | #define SDRAM_PRIO_MIPS_SHIFT 29 | |
| 1186 | #define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT) | |
| 1187 | #define SDRAM_PRIO_ADSL_SHIFT 30 | |
| 1188 | #define SDRAM_PRIO_ADSL_MASK (1 << SDRAM_PRIO_ADSL_SHIFT) | |
| 1189 | #define SDRAM_PRIO_EN_SHIFT 31 | |
| 1190 | #define SDRAM_PRIO_EN_MASK (1 << SDRAM_PRIO_EN_SHIFT) | |
| 1191 | ||
| 1192 | ||
| 1193 | /************************************************************************* | |
| 1194 | * _REG relative to RSET_MEMC | |
| 1195 | *************************************************************************/ | |
| 1196 | ||
| 1197 | #define MEMC_CFG_REG 0x4 | |
| 1198 | #define MEMC_CFG_32B_SHIFT 1 | |
| 1199 | #define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT) | |
| 1200 | #define MEMC_CFG_COL_SHIFT 3 | |
| 1201 | #define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT) | |
| 1202 | #define MEMC_CFG_ROW_SHIFT 6 | |
| 1203 | #define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT) | |
| 1204 | ||
| 1205 | ||
| 1206 | /************************************************************************* | |
| 1207 | * _REG relative to RSET_DDR | |
| 1208 | *************************************************************************/ | |
| 1209 | ||
| e5766aea JG |
1210 | #define DDR_CSEND_REG 0x8 |
| 1211 | ||
| e7300d04 MB |
1212 | #define DDR_DMIPSPLLCFG_REG 0x18 |
| 1213 | #define DMIPSPLLCFG_M1_SHIFT 0 | |
| 1214 | #define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT) | |
| 1215 | #define DMIPSPLLCFG_N1_SHIFT 23 | |
| 1216 | #define DMIPSPLLCFG_N1_MASK (0x3f << DMIPSPLLCFG_N1_SHIFT) | |
| 1217 | #define DMIPSPLLCFG_N2_SHIFT 29 | |
| 1218 | #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT) | |
| 1219 | ||
| 04712f3f MB |
1220 | #define DDR_DMIPSPLLCFG_6368_REG 0x20 |
| 1221 | #define DMIPSPLLCFG_6368_P1_SHIFT 0 | |
| 1222 | #define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT) | |
| 1223 | #define DMIPSPLLCFG_6368_P2_SHIFT 4 | |
| 1224 | #define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT) | |
| 1225 | #define DMIPSPLLCFG_6368_NDIV_SHIFT 16 | |
| 1226 | #define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT) | |
| 1227 | ||
| 1228 | #define DDR_DMIPSPLLDIV_6368_REG 0x24 | |
| 1229 | #define DMIPSPLLDIV_6368_MDIV_SHIFT 0 | |
| 1230 | #define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT) | |
| 1231 | ||
| 1232 | ||
| d430b6c5 MB |
1233 | /************************************************************************* |
| 1234 | * _REG relative to RSET_M2M | |
| 1235 | *************************************************************************/ | |
| 1236 | ||
| 1237 | #define M2M_RX 0 | |
| 1238 | #define M2M_TX 1 | |
| 1239 | ||
| 1240 | #define M2M_SRC_REG(x) ((x) * 0x40 + 0x00) | |
| 1241 | #define M2M_DST_REG(x) ((x) * 0x40 + 0x04) | |
| 1242 | #define M2M_SIZE_REG(x) ((x) * 0x40 + 0x08) | |
| 1243 | ||
| 1244 | #define M2M_CTRL_REG(x) ((x) * 0x40 + 0x0c) | |
| 1245 | #define M2M_CTRL_ENABLE_MASK (1 << 0) | |
| 1246 | #define M2M_CTRL_IRQEN_MASK (1 << 1) | |
| 1247 | #define M2M_CTRL_ERROR_CLR_MASK (1 << 6) | |
| 1248 | #define M2M_CTRL_DONE_CLR_MASK (1 << 7) | |
| 1249 | #define M2M_CTRL_NOINC_MASK (1 << 8) | |
| 1250 | #define M2M_CTRL_PCMCIASWAP_MASK (1 << 9) | |
| 1251 | #define M2M_CTRL_SWAPBYTE_MASK (1 << 10) | |
| 1252 | #define M2M_CTRL_ENDIAN_MASK (1 << 11) | |
| 1253 | ||
| 1254 | #define M2M_STAT_REG(x) ((x) * 0x40 + 0x10) | |
| 1255 | #define M2M_STAT_DONE (1 << 0) | |
| 1256 | #define M2M_STAT_ERROR (1 << 1) | |
| 1257 | ||
| 1258 | #define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14) | |
| 1259 | #define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18) | |
| 1260 | ||
| 8aecfe94 FF |
1261 | /************************************************************************* |
| 1262 | * _REG relative to RSET_RNG | |
| 1263 | *************************************************************************/ | |
| 1264 | ||
| 1265 | #define RNG_CTRL 0x00 | |
| 1266 | #define RNG_EN (1 << 0) | |
| 1267 | ||
| 1268 | #define RNG_STAT 0x04 | |
| 1269 | #define RNG_AVAIL_MASK (0xff000000) | |
| 1270 | ||
| 1271 | #define RNG_DATA 0x08 | |
| 1272 | #define RNG_THRES 0x0c | |
| 1273 | #define RNG_MASK 0x10 | |
| 1274 | ||
| 0f6db0d0 FF |
1275 | /************************************************************************* |
| 1276 | * _REG relative to RSET_SPI | |
| 1277 | *************************************************************************/ | |
| 1278 | ||
| 8a398d75 | 1279 | /* BCM 6338/6348 SPI core */ |
| 0f6db0d0 FF |
1280 | #define SPI_6348_CMD 0x00 /* 16-bits register */ |
| 1281 | #define SPI_6348_INT_STATUS 0x02 | |
| 1282 | #define SPI_6348_INT_MASK_ST 0x03 | |
| 1283 | #define SPI_6348_INT_MASK 0x04 | |
| 1284 | #define SPI_6348_ST 0x05 | |
| 1285 | #define SPI_6348_CLK_CFG 0x06 | |
| 1286 | #define SPI_6348_FILL_BYTE 0x07 | |
| 1287 | #define SPI_6348_MSG_TAIL 0x09 | |
| 1288 | #define SPI_6348_RX_TAIL 0x0b | |
| 5a670445 FF |
1289 | #define SPI_6348_MSG_CTL 0x40 /* 8-bits register */ |
| 1290 | #define SPI_6348_MSG_CTL_WIDTH 8 | |
| 0f6db0d0 FF |
1291 | #define SPI_6348_MSG_DATA 0x41 |
| 1292 | #define SPI_6348_MSG_DATA_SIZE 0x3f | |
| 1293 | #define SPI_6348_RX_DATA 0x80 | |
| 1294 | #define SPI_6348_RX_DATA_SIZE 0x3f | |
| 1295 | ||
| 2c8aaf71 | 1296 | /* BCM 6358/6262/6368 SPI core */ |
| 0f6db0d0 | 1297 | #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */ |
| 5a670445 | 1298 | #define SPI_6358_MSG_CTL_WIDTH 16 |
| 0f6db0d0 FF |
1299 | #define SPI_6358_MSG_DATA 0x02 |
| 1300 | #define SPI_6358_MSG_DATA_SIZE 0x21e | |
| 1301 | #define SPI_6358_RX_DATA 0x400 | |
| 1302 | #define SPI_6358_RX_DATA_SIZE 0x220 | |
| 1303 | #define SPI_6358_CMD 0x700 /* 16-bits register */ | |
| 1304 | #define SPI_6358_INT_STATUS 0x702 | |
| 1305 | #define SPI_6358_INT_MASK_ST 0x703 | |
| 1306 | #define SPI_6358_INT_MASK 0x704 | |
| 1307 | #define SPI_6358_ST 0x705 | |
| 1308 | #define SPI_6358_CLK_CFG 0x706 | |
| 1309 | #define SPI_6358_FILL_BYTE 0x707 | |
| 1310 | #define SPI_6358_MSG_TAIL 0x709 | |
| 1311 | #define SPI_6358_RX_TAIL 0x70B | |
| 1312 | ||
| 0f6db0d0 FF |
1313 | /* Shared SPI definitions */ |
| 1314 | ||
| 1315 | /* Message configuration */ | |
| 1316 | #define SPI_FD_RW 0x00 | |
| 1317 | #define SPI_HD_W 0x01 | |
| 1318 | #define SPI_HD_R 0x02 | |
| 1319 | #define SPI_BYTE_CNT_SHIFT 0 | |
| 5a670445 FF |
1320 | #define SPI_6348_MSG_TYPE_SHIFT 6 |
| 1321 | #define SPI_6358_MSG_TYPE_SHIFT 14 | |
| 0f6db0d0 FF |
1322 | |
| 1323 | /* Command */ | |
| 1324 | #define SPI_CMD_NOOP 0x00 | |
| 1325 | #define SPI_CMD_SOFT_RESET 0x01 | |
| 1326 | #define SPI_CMD_HARD_RESET 0x02 | |
| 1327 | #define SPI_CMD_START_IMMEDIATE 0x03 | |
| 1328 | #define SPI_CMD_COMMAND_SHIFT 0 | |
| 1329 | #define SPI_CMD_COMMAND_MASK 0x000f | |
| 1330 | #define SPI_CMD_DEVICE_ID_SHIFT 4 | |
| 1331 | #define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8 | |
| 1332 | #define SPI_CMD_ONE_BYTE_SHIFT 11 | |
| 1333 | #define SPI_CMD_ONE_WIRE_SHIFT 12 | |
| 1334 | #define SPI_DEV_ID_0 0 | |
| 1335 | #define SPI_DEV_ID_1 1 | |
| 1336 | #define SPI_DEV_ID_2 2 | |
| 1337 | #define SPI_DEV_ID_3 3 | |
| 1338 | ||
| 1339 | /* Interrupt mask */ | |
| 1340 | #define SPI_INTR_CMD_DONE 0x01 | |
| 1341 | #define SPI_INTR_RX_OVERFLOW 0x02 | |
| 1342 | #define SPI_INTR_TX_UNDERFLOW 0x04 | |
| 1343 | #define SPI_INTR_TX_OVERFLOW 0x08 | |
| 1344 | #define SPI_INTR_RX_UNDERFLOW 0x10 | |
| 1345 | #define SPI_INTR_CLEAR_ALL 0x1f | |
| 1346 | ||
| 1347 | /* Status */ | |
| 1348 | #define SPI_RX_EMPTY 0x02 | |
| 1349 | #define SPI_CMD_BUSY 0x04 | |
| 1350 | #define SPI_SERIAL_BUSY 0x08 | |
| 1351 | ||
| 1352 | /* Clock configuration */ | |
| 1353 | #define SPI_CLK_20MHZ 0x00 | |
| 1354 | #define SPI_CLK_0_391MHZ 0x01 | |
| 1355 | #define SPI_CLK_0_781MHZ 0x02 /* default */ | |
| 1356 | #define SPI_CLK_1_563MHZ 0x03 | |
| 1357 | #define SPI_CLK_3_125MHZ 0x04 | |
| 1358 | #define SPI_CLK_6_250MHZ 0x05 | |
| 1359 | #define SPI_CLK_12_50MHZ 0x06 | |
| 1360 | #define SPI_CLK_MASK 0x07 | |
| 1361 | #define SPI_SSOFFTIME_MASK 0x38 | |
| 1362 | #define SPI_SSOFFTIME_SHIFT 3 | |
| 1363 | #define SPI_BYTE_SWAP 0x80 | |
| 1364 | ||
| e5766aea JG |
1365 | /************************************************************************* |
| 1366 | * _REG relative to RSET_MISC | |
| 1367 | *************************************************************************/ | |
| 19c860d9 JG |
1368 | #define MISC_SERDES_CTRL_REG 0x0 |
| 1369 | #define SERDES_PCIE_EN (1 << 0) | |
| 1370 | #define SERDES_PCIE_EXD_EN (1 << 15) | |
| e5766aea | 1371 | |
| 2c8aaf71 JG |
1372 | #define MISC_STRAPBUS_6362_REG 0x14 |
| 1373 | #define STRAPBUS_6362_FCVO_SHIFT 1 | |
| 1374 | #define STRAPBUS_6362_FCVO_MASK (0x1f << STRAPBUS_6362_FCVO_SHIFT) | |
| 1375 | #define STRAPBUS_6362_BOOT_SEL_SERIAL (1 << 15) | |
| 1376 | #define STRAPBUS_6362_BOOT_SEL_NAND (0 << 15) | |
| 1377 | ||
| e5766aea JG |
1378 | #define MISC_STRAPBUS_6328_REG 0x240 |
| 1379 | #define STRAPBUS_6328_FCVO_SHIFT 7 | |
| 1380 | #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT) | |
| 1381 | #define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28) | |
| 1382 | #define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28) | |
| 1383 | ||
| 19c860d9 JG |
1384 | /************************************************************************* |
| 1385 | * _REG relative to RSET_PCIE | |
| 1386 | *************************************************************************/ | |
| 1387 | ||
| 1388 | #define PCIE_CONFIG2_REG 0x408 | |
| 1389 | #define CONFIG2_BAR1_SIZE_EN 1 | |
| 1390 | #define CONFIG2_BAR1_SIZE_MASK 0xf | |
| 1391 | ||
| 1392 | #define PCIE_IDVAL3_REG 0x43c | |
| 1393 | #define IDVAL3_CLASS_CODE_MASK 0xffffff | |
| 1394 | #define IDVAL3_SUBCLASS_SHIFT 8 | |
| 1395 | #define IDVAL3_CLASS_SHIFT 16 | |
| 1396 | ||
| 1397 | #define PCIE_DLSTATUS_REG 0x1048 | |
| 1398 | #define DLSTATUS_PHYLINKUP (1 << 13) | |
| 1399 | ||
| 1400 | #define PCIE_BRIDGE_OPT1_REG 0x2820 | |
| 1401 | #define OPT1_RD_BE_OPT_EN (1 << 7) | |
| 1402 | #define OPT1_RD_REPLY_BE_FIX_EN (1 << 9) | |
| 1403 | #define OPT1_PCIE_BRIDGE_HOLE_DET_EN (1 << 11) | |
| 1404 | #define OPT1_L1_INT_STATUS_MASK_POL (1 << 12) | |
| 1405 | ||
| 1406 | #define PCIE_BRIDGE_OPT2_REG 0x2824 | |
| 1407 | #define OPT2_UBUS_UR_DECODE_DIS (1 << 2) | |
| 1408 | #define OPT2_TX_CREDIT_CHK_EN (1 << 4) | |
| 1409 | #define OPT2_CFG_TYPE1_BD_SEL (1 << 7) | |
| 1410 | #define OPT2_CFG_TYPE1_BUS_NO_SHIFT 16 | |
| 1411 | #define OPT2_CFG_TYPE1_BUS_NO_MASK (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT) | |
| 1412 | ||
| 1413 | #define PCIE_BRIDGE_BAR0_BASEMASK_REG 0x2828 | |
| 1414 | #define PCIE_BRIDGE_BAR1_BASEMASK_REG 0x2830 | |
| 1415 | #define BASEMASK_REMAP_EN (1 << 0) | |
| 1416 | #define BASEMASK_SWAP_EN (1 << 1) | |
| 1417 | #define BASEMASK_MASK_SHIFT 4 | |
| 1418 | #define BASEMASK_MASK_MASK (0xfff << BASEMASK_MASK_SHIFT) | |
| 1419 | #define BASEMASK_BASE_SHIFT 20 | |
| 1420 | #define BASEMASK_BASE_MASK (0xfff << BASEMASK_BASE_SHIFT) | |
| 1421 | ||
| 1422 | #define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c | |
| 1423 | #define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834 | |
| 1424 | #define REBASE_ADDR_BASE_SHIFT 20 | |
| 1425 | #define REBASE_ADDR_BASE_MASK (0xfff << REBASE_ADDR_BASE_SHIFT) | |
| 1426 | ||
| 1427 | #define PCIE_BRIDGE_RC_INT_MASK_REG 0x2854 | |
| 1428 | #define PCIE_RC_INT_A (1 << 0) | |
| 1429 | #define PCIE_RC_INT_B (1 << 1) | |
| 1430 | #define PCIE_RC_INT_C (1 << 2) | |
| 1431 | #define PCIE_RC_INT_D (1 << 3) | |
| 1432 | ||
| 1433 | #define PCIE_DEVICE_OFFSET 0x8000 | |
| 1434 | ||
| e7300d04 | 1435 | #endif /* BCM63XX_REGS_H_ */ |