projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| e7300d04 MB |
1 | #ifndef BCM63XX_REGS_H_ |
| 2 | #define BCM63XX_REGS_H_ | |
| 3 | ||
| 4 | /************************************************************************* | |
| 5 | * _REG relative to RSET_PERF | |
| 6 | *************************************************************************/ | |
| 7 | ||
| 8 | /* Chip Identifier / Revision register */ | |
| 9 | #define PERF_REV_REG 0x0 | |
| 10 | #define REV_CHIPID_SHIFT 16 | |
| 11 | #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) | |
| 12 | #define REV_REVID_SHIFT 0 | |
| 13 | #define REV_REVID_MASK (0xffff << REV_REVID_SHIFT) | |
| 14 | ||
| 15 | /* Clock Control register */ | |
| 16 | #define PERF_CKCTL_REG 0x4 | |
| 17 | ||
| 18 | #define CKCTL_6338_ADSLPHY_EN (1 << 0) | |
| 19 | #define CKCTL_6338_MPI_EN (1 << 1) | |
| 20 | #define CKCTL_6338_DRAM_EN (1 << 2) | |
| 21 | #define CKCTL_6338_ENET_EN (1 << 4) | |
| 22 | #define CKCTL_6338_USBS_EN (1 << 4) | |
| 23 | #define CKCTL_6338_SAR_EN (1 << 5) | |
| 24 | #define CKCTL_6338_SPI_EN (1 << 9) | |
| 25 | ||
| 26 | #define CKCTL_6338_ALL_SAFE_EN (CKCTL_6338_ADSLPHY_EN | \ | |
| 27 | CKCTL_6338_MPI_EN | \ | |
| 28 | CKCTL_6338_ENET_EN | \ | |
| 29 | CKCTL_6338_SAR_EN | \ | |
| 30 | CKCTL_6338_SPI_EN) | |
| 31 | ||
| 32 | #define CKCTL_6345_CPU_EN (1 << 0) | |
| 33 | #define CKCTL_6345_BUS_EN (1 << 1) | |
| 34 | #define CKCTL_6345_EBI_EN (1 << 2) | |
| 35 | #define CKCTL_6345_UART_EN (1 << 3) | |
| 36 | #define CKCTL_6345_ADSLPHY_EN (1 << 4) | |
| 37 | #define CKCTL_6345_ENET_EN (1 << 7) | |
| 38 | #define CKCTL_6345_USBH_EN (1 << 8) | |
| 39 | ||
| 40 | #define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \ | |
| 41 | CKCTL_6345_USBH_EN | \ | |
| 42 | CKCTL_6345_ADSLPHY_EN) | |
| 43 | ||
| 44 | #define CKCTL_6348_ADSLPHY_EN (1 << 0) | |
| 45 | #define CKCTL_6348_MPI_EN (1 << 1) | |
| 46 | #define CKCTL_6348_SDRAM_EN (1 << 2) | |
| 47 | #define CKCTL_6348_M2M_EN (1 << 3) | |
| 48 | #define CKCTL_6348_ENET_EN (1 << 4) | |
| 49 | #define CKCTL_6348_SAR_EN (1 << 5) | |
| 50 | #define CKCTL_6348_USBS_EN (1 << 6) | |
| 51 | #define CKCTL_6348_USBH_EN (1 << 8) | |
| 52 | #define CKCTL_6348_SPI_EN (1 << 9) | |
| 53 | ||
| 54 | #define CKCTL_6348_ALL_SAFE_EN (CKCTL_6348_ADSLPHY_EN | \ | |
| 55 | CKCTL_6348_M2M_EN | \ | |
| 56 | CKCTL_6348_ENET_EN | \ | |
| 57 | CKCTL_6348_SAR_EN | \ | |
| 58 | CKCTL_6348_USBS_EN | \ | |
| 59 | CKCTL_6348_USBH_EN | \ | |
| 60 | CKCTL_6348_SPI_EN) | |
| 61 | ||
| 62 | #define CKCTL_6358_ENET_EN (1 << 4) | |
| 63 | #define CKCTL_6358_ADSLPHY_EN (1 << 5) | |
| 64 | #define CKCTL_6358_PCM_EN (1 << 8) | |
| 65 | #define CKCTL_6358_SPI_EN (1 << 9) | |
| 66 | #define CKCTL_6358_USBS_EN (1 << 10) | |
| 67 | #define CKCTL_6358_SAR_EN (1 << 11) | |
| 68 | #define CKCTL_6358_EMUSB_EN (1 << 17) | |
| 69 | #define CKCTL_6358_ENET0_EN (1 << 18) | |
| 70 | #define CKCTL_6358_ENET1_EN (1 << 19) | |
| 71 | #define CKCTL_6358_USBSU_EN (1 << 20) | |
| 72 | #define CKCTL_6358_EPHY_EN (1 << 21) | |
| 73 | ||
| 74 | #define CKCTL_6358_ALL_SAFE_EN (CKCTL_6358_ENET_EN | \ | |
| 75 | CKCTL_6358_ADSLPHY_EN | \ | |
| 76 | CKCTL_6358_PCM_EN | \ | |
| 77 | CKCTL_6358_SPI_EN | \ | |
| 78 | CKCTL_6358_USBS_EN | \ | |
| 79 | CKCTL_6358_SAR_EN | \ | |
| 80 | CKCTL_6358_EMUSB_EN | \ | |
| 81 | CKCTL_6358_ENET0_EN | \ | |
| 82 | CKCTL_6358_ENET1_EN | \ | |
| 83 | CKCTL_6358_USBSU_EN | \ | |
| 84 | CKCTL_6358_EPHY_EN) | |
| 85 | ||
| 86 | /* System PLL Control register */ | |
| 87 | #define PERF_SYS_PLL_CTL_REG 0x8 | |
| 88 | #define SYS_PLL_SOFT_RESET 0x1 | |
| 89 | ||
| 90 | /* Interrupt Mask register */ | |
| 91 | #define PERF_IRQMASK_REG 0xc | |
| e7300d04 MB |
92 | |
| 93 | /* Interrupt Status register */ | |
| 94 | #define PERF_IRQSTAT_REG 0x10 | |
| 95 | ||
| 96 | /* External Interrupt Configuration register */ | |
| 97 | #define PERF_EXTIRQ_CFG_REG 0x14 | |
| 98 | #define EXTIRQ_CFG_SENSE(x) (1 << (x)) | |
| 99 | #define EXTIRQ_CFG_STAT(x) (1 << (x + 5)) | |
| 100 | #define EXTIRQ_CFG_CLEAR(x) (1 << (x + 10)) | |
| 101 | #define EXTIRQ_CFG_MASK(x) (1 << (x + 15)) | |
| 102 | #define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 20)) | |
| 103 | #define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 25)) | |
| 104 | ||
| 105 | #define EXTIRQ_CFG_CLEAR_ALL (0xf << 10) | |
| 106 | #define EXTIRQ_CFG_MASK_ALL (0xf << 15) | |
| 107 | ||
| 108 | /* Soft Reset register */ | |
| 109 | #define PERF_SOFTRESET_REG 0x28 | |
| 110 | ||
| 111 | #define SOFTRESET_6338_SPI_MASK (1 << 0) | |
| 112 | #define SOFTRESET_6338_ENET_MASK (1 << 2) | |
| 113 | #define SOFTRESET_6338_USBH_MASK (1 << 3) | |
| 114 | #define SOFTRESET_6338_USBS_MASK (1 << 4) | |
| 115 | #define SOFTRESET_6338_ADSL_MASK (1 << 5) | |
| 116 | #define SOFTRESET_6338_DMAMEM_MASK (1 << 6) | |
| 117 | #define SOFTRESET_6338_SAR_MASK (1 << 7) | |
| 118 | #define SOFTRESET_6338_ACLC_MASK (1 << 8) | |
| 119 | #define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10) | |
| 120 | #define SOFTRESET_6338_ALL (SOFTRESET_6338_SPI_MASK | \ | |
| 121 | SOFTRESET_6338_ENET_MASK | \ | |
| 122 | SOFTRESET_6338_USBH_MASK | \ | |
| 123 | SOFTRESET_6338_USBS_MASK | \ | |
| 124 | SOFTRESET_6338_ADSL_MASK | \ | |
| 125 | SOFTRESET_6338_DMAMEM_MASK | \ | |
| 126 | SOFTRESET_6338_SAR_MASK | \ | |
| 127 | SOFTRESET_6338_ACLC_MASK | \ | |
| 128 | SOFTRESET_6338_ADSLMIPSPLL_MASK) | |
| 129 | ||
| 130 | #define SOFTRESET_6348_SPI_MASK (1 << 0) | |
| 131 | #define SOFTRESET_6348_ENET_MASK (1 << 2) | |
| 132 | #define SOFTRESET_6348_USBH_MASK (1 << 3) | |
| 133 | #define SOFTRESET_6348_USBS_MASK (1 << 4) | |
| 134 | #define SOFTRESET_6348_ADSL_MASK (1 << 5) | |
| 135 | #define SOFTRESET_6348_DMAMEM_MASK (1 << 6) | |
| 136 | #define SOFTRESET_6348_SAR_MASK (1 << 7) | |
| 137 | #define SOFTRESET_6348_ACLC_MASK (1 << 8) | |
| 138 | #define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10) | |
| 139 | ||
| 140 | #define SOFTRESET_6348_ALL (SOFTRESET_6348_SPI_MASK | \ | |
| 141 | SOFTRESET_6348_ENET_MASK | \ | |
| 142 | SOFTRESET_6348_USBH_MASK | \ | |
| 143 | SOFTRESET_6348_USBS_MASK | \ | |
| 144 | SOFTRESET_6348_ADSL_MASK | \ | |
| 145 | SOFTRESET_6348_DMAMEM_MASK | \ | |
| 146 | SOFTRESET_6348_SAR_MASK | \ | |
| 147 | SOFTRESET_6348_ACLC_MASK | \ | |
| 148 | SOFTRESET_6348_ADSLMIPSPLL_MASK) | |
| 149 | ||
| 150 | /* MIPS PLL control register */ | |
| 151 | #define PERF_MIPSPLLCTL_REG 0x34 | |
| 152 | #define MIPSPLLCTL_N1_SHIFT 20 | |
| 153 | #define MIPSPLLCTL_N1_MASK (0x7 << MIPSPLLCTL_N1_SHIFT) | |
| 154 | #define MIPSPLLCTL_N2_SHIFT 15 | |
| 155 | #define MIPSPLLCTL_N2_MASK (0x1f << MIPSPLLCTL_N2_SHIFT) | |
| 156 | #define MIPSPLLCTL_M1REF_SHIFT 12 | |
| 157 | #define MIPSPLLCTL_M1REF_MASK (0x7 << MIPSPLLCTL_M1REF_SHIFT) | |
| 158 | #define MIPSPLLCTL_M2REF_SHIFT 9 | |
| 159 | #define MIPSPLLCTL_M2REF_MASK (0x7 << MIPSPLLCTL_M2REF_SHIFT) | |
| 160 | #define MIPSPLLCTL_M1CPU_SHIFT 6 | |
| 161 | #define MIPSPLLCTL_M1CPU_MASK (0x7 << MIPSPLLCTL_M1CPU_SHIFT) | |
| 162 | #define MIPSPLLCTL_M1BUS_SHIFT 3 | |
| 163 | #define MIPSPLLCTL_M1BUS_MASK (0x7 << MIPSPLLCTL_M1BUS_SHIFT) | |
| 164 | #define MIPSPLLCTL_M2BUS_SHIFT 0 | |
| 165 | #define MIPSPLLCTL_M2BUS_MASK (0x7 << MIPSPLLCTL_M2BUS_SHIFT) | |
| 166 | ||
| 167 | /* ADSL PHY PLL Control register */ | |
| 168 | #define PERF_ADSLPLLCTL_REG 0x38 | |
| 169 | #define ADSLPLLCTL_N1_SHIFT 20 | |
| 170 | #define ADSLPLLCTL_N1_MASK (0x7 << ADSLPLLCTL_N1_SHIFT) | |
| 171 | #define ADSLPLLCTL_N2_SHIFT 15 | |
| 172 | #define ADSLPLLCTL_N2_MASK (0x1f << ADSLPLLCTL_N2_SHIFT) | |
| 173 | #define ADSLPLLCTL_M1REF_SHIFT 12 | |
| 174 | #define ADSLPLLCTL_M1REF_MASK (0x7 << ADSLPLLCTL_M1REF_SHIFT) | |
| 175 | #define ADSLPLLCTL_M2REF_SHIFT 9 | |
| 176 | #define ADSLPLLCTL_M2REF_MASK (0x7 << ADSLPLLCTL_M2REF_SHIFT) | |
| 177 | #define ADSLPLLCTL_M1CPU_SHIFT 6 | |
| 178 | #define ADSLPLLCTL_M1CPU_MASK (0x7 << ADSLPLLCTL_M1CPU_SHIFT) | |
| 179 | #define ADSLPLLCTL_M1BUS_SHIFT 3 | |
| 180 | #define ADSLPLLCTL_M1BUS_MASK (0x7 << ADSLPLLCTL_M1BUS_SHIFT) | |
| 181 | #define ADSLPLLCTL_M2BUS_SHIFT 0 | |
| 182 | #define ADSLPLLCTL_M2BUS_MASK (0x7 << ADSLPLLCTL_M2BUS_SHIFT) | |
| 183 | ||
| 184 | #define ADSLPLLCTL_VAL(n1, n2, m1ref, m2ref, m1cpu, m1bus, m2bus) \ | |
| 185 | (((n1) << ADSLPLLCTL_N1_SHIFT) | \ | |
| 186 | ((n2) << ADSLPLLCTL_N2_SHIFT) | \ | |
| 187 | ((m1ref) << ADSLPLLCTL_M1REF_SHIFT) | \ | |
| 188 | ((m2ref) << ADSLPLLCTL_M2REF_SHIFT) | \ | |
| 189 | ((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) | \ | |
| 190 | ((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) | \ | |
| 191 | ((m2bus) << ADSLPLLCTL_M2BUS_SHIFT)) | |
| 192 | ||
| 193 | ||
| 194 | /************************************************************************* | |
| 195 | * _REG relative to RSET_TIMER | |
| 196 | *************************************************************************/ | |
| 197 | ||
| 198 | #define BCM63XX_TIMER_COUNT 4 | |
| 199 | #define TIMER_T0_ID 0 | |
| 200 | #define TIMER_T1_ID 1 | |
| 201 | #define TIMER_T2_ID 2 | |
| 202 | #define TIMER_WDT_ID 3 | |
| 203 | ||
| 204 | /* Timer irqstat register */ | |
| 205 | #define TIMER_IRQSTAT_REG 0 | |
| 206 | #define TIMER_IRQSTAT_TIMER_CAUSE(x) (1 << (x)) | |
| 207 | #define TIMER_IRQSTAT_TIMER0_CAUSE (1 << 0) | |
| 208 | #define TIMER_IRQSTAT_TIMER1_CAUSE (1 << 1) | |
| 209 | #define TIMER_IRQSTAT_TIMER2_CAUSE (1 << 2) | |
| 210 | #define TIMER_IRQSTAT_WDT_CAUSE (1 << 3) | |
| 211 | #define TIMER_IRQSTAT_TIMER_IR_EN(x) (1 << ((x) + 8)) | |
| 212 | #define TIMER_IRQSTAT_TIMER0_IR_EN (1 << 8) | |
| 213 | #define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9) | |
| 214 | #define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10) | |
| 215 | ||
| 216 | /* Timer control register */ | |
| 217 | #define TIMER_CTLx_REG(x) (0x4 + (x * 4)) | |
| 218 | #define TIMER_CTL0_REG 0x4 | |
| 219 | #define TIMER_CTL1_REG 0x8 | |
| 220 | #define TIMER_CTL2_REG 0xC | |
| 221 | #define TIMER_CTL_COUNTDOWN_MASK (0x3fffffff) | |
| 222 | #define TIMER_CTL_MONOTONIC_MASK (1 << 30) | |
| 223 | #define TIMER_CTL_ENABLE_MASK (1 << 31) | |
| 224 | ||
| 225 | ||
| 226 | /************************************************************************* | |
| 227 | * _REG relative to RSET_WDT | |
| 228 | *************************************************************************/ | |
| 229 | ||
| 230 | /* Watchdog default count register */ | |
| 231 | #define WDT_DEFVAL_REG 0x0 | |
| 232 | ||
| 233 | /* Watchdog control register */ | |
| 234 | #define WDT_CTL_REG 0x4 | |
| 235 | ||
| 236 | /* Watchdog control register constants */ | |
| 237 | #define WDT_START_1 (0xff00) | |
| 238 | #define WDT_START_2 (0x00ff) | |
| 239 | #define WDT_STOP_1 (0xee00) | |
| 240 | #define WDT_STOP_2 (0x00ee) | |
| 241 | ||
| 242 | /* Watchdog reset length register */ | |
| 243 | #define WDT_RSTLEN_REG 0x8 | |
| 244 | ||
| 245 | ||
| 246 | /************************************************************************* | |
| 247 | * _REG relative to RSET_UARTx | |
| 248 | *************************************************************************/ | |
| 249 | ||
| 250 | /* UART Control Register */ | |
| 251 | #define UART_CTL_REG 0x0 | |
| 252 | #define UART_CTL_RXTMOUTCNT_SHIFT 0 | |
| 253 | #define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT) | |
| 254 | #define UART_CTL_RSTTXDN_SHIFT 5 | |
| 255 | #define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT) | |
| 256 | #define UART_CTL_RSTRXFIFO_SHIFT 6 | |
| 257 | #define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT) | |
| 258 | #define UART_CTL_RSTTXFIFO_SHIFT 7 | |
| 259 | #define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT) | |
| 260 | #define UART_CTL_STOPBITS_SHIFT 8 | |
| 261 | #define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT) | |
| 262 | #define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT) | |
| 263 | #define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT) | |
| 264 | #define UART_CTL_BITSPERSYM_SHIFT 12 | |
| 265 | #define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT) | |
| 266 | #define UART_CTL_XMITBRK_SHIFT 14 | |
| 267 | #define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT) | |
| 268 | #define UART_CTL_RSVD_SHIFT 15 | |
| 269 | #define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT) | |
| 270 | #define UART_CTL_RXPAREVEN_SHIFT 16 | |
| 271 | #define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT) | |
| 272 | #define UART_CTL_RXPAREN_SHIFT 17 | |
| 273 | #define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT) | |
| 274 | #define UART_CTL_TXPAREVEN_SHIFT 18 | |
| 275 | #define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT) | |
| 276 | #define UART_CTL_TXPAREN_SHIFT 18 | |
| 277 | #define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT) | |
| 278 | #define UART_CTL_LOOPBACK_SHIFT 20 | |
| 279 | #define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT) | |
| 280 | #define UART_CTL_RXEN_SHIFT 21 | |
| 281 | #define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT) | |
| 282 | #define UART_CTL_TXEN_SHIFT 22 | |
| 283 | #define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT) | |
| 284 | #define UART_CTL_BRGEN_SHIFT 23 | |
| 285 | #define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT) | |
| 286 | ||
| 287 | /* UART Baudword register */ | |
| 288 | #define UART_BAUD_REG 0x4 | |
| 289 | ||
| 290 | /* UART Misc Control register */ | |
| 291 | #define UART_MCTL_REG 0x8 | |
| 292 | #define UART_MCTL_DTR_SHIFT 0 | |
| 293 | #define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT) | |
| 294 | #define UART_MCTL_RTS_SHIFT 1 | |
| 295 | #define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT) | |
| 296 | #define UART_MCTL_RXFIFOTHRESH_SHIFT 8 | |
| 297 | #define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT) | |
| 298 | #define UART_MCTL_TXFIFOTHRESH_SHIFT 12 | |
| 299 | #define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT) | |
| 300 | #define UART_MCTL_RXFIFOFILL_SHIFT 16 | |
| 301 | #define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT) | |
| 302 | #define UART_MCTL_TXFIFOFILL_SHIFT 24 | |
| 303 | #define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT) | |
| 304 | ||
| 305 | /* UART External Input Configuration register */ | |
| 306 | #define UART_EXTINP_REG 0xc | |
| 307 | #define UART_EXTINP_RI_SHIFT 0 | |
| 308 | #define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT) | |
| 309 | #define UART_EXTINP_CTS_SHIFT 1 | |
| 310 | #define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT) | |
| 311 | #define UART_EXTINP_DCD_SHIFT 2 | |
| 312 | #define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT) | |
| 313 | #define UART_EXTINP_DSR_SHIFT 3 | |
| 314 | #define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT) | |
| 315 | #define UART_EXTINP_IRSTAT(x) (1 << (x + 4)) | |
| 316 | #define UART_EXTINP_IRMASK(x) (1 << (x + 8)) | |
| 317 | #define UART_EXTINP_IR_RI 0 | |
| 318 | #define UART_EXTINP_IR_CTS 1 | |
| 319 | #define UART_EXTINP_IR_DCD 2 | |
| 320 | #define UART_EXTINP_IR_DSR 3 | |
| 321 | #define UART_EXTINP_RI_NOSENSE_SHIFT 16 | |
| 322 | #define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT) | |
| 323 | #define UART_EXTINP_CTS_NOSENSE_SHIFT 17 | |
| 324 | #define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT) | |
| 325 | #define UART_EXTINP_DCD_NOSENSE_SHIFT 18 | |
| 326 | #define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT) | |
| 327 | #define UART_EXTINP_DSR_NOSENSE_SHIFT 19 | |
| 328 | #define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT) | |
| 329 | ||
| 330 | /* UART Interrupt register */ | |
| 331 | #define UART_IR_REG 0x10 | |
| 332 | #define UART_IR_MASK(x) (1 << (x + 16)) | |
| 333 | #define UART_IR_STAT(x) (1 << (x)) | |
| 334 | #define UART_IR_EXTIP 0 | |
| 335 | #define UART_IR_TXUNDER 1 | |
| 336 | #define UART_IR_TXOVER 2 | |
| 337 | #define UART_IR_TXTRESH 3 | |
| 338 | #define UART_IR_TXRDLATCH 4 | |
| 339 | #define UART_IR_TXEMPTY 5 | |
| 340 | #define UART_IR_RXUNDER 6 | |
| 341 | #define UART_IR_RXOVER 7 | |
| 342 | #define UART_IR_RXTIMEOUT 8 | |
| 343 | #define UART_IR_RXFULL 9 | |
| 344 | #define UART_IR_RXTHRESH 10 | |
| 345 | #define UART_IR_RXNOTEMPTY 11 | |
| 346 | #define UART_IR_RXFRAMEERR 12 | |
| 347 | #define UART_IR_RXPARERR 13 | |
| 348 | #define UART_IR_RXBRK 14 | |
| 349 | #define UART_IR_TXDONE 15 | |
| 350 | ||
| 351 | /* UART Fifo register */ | |
| 352 | #define UART_FIFO_REG 0x14 | |
| 353 | #define UART_FIFO_VALID_SHIFT 0 | |
| 354 | #define UART_FIFO_VALID_MASK 0xff | |
| 355 | #define UART_FIFO_FRAMEERR_SHIFT 8 | |
| 356 | #define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT) | |
| 357 | #define UART_FIFO_PARERR_SHIFT 9 | |
| 358 | #define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT) | |
| 359 | #define UART_FIFO_BRKDET_SHIFT 10 | |
| 360 | #define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT) | |
| 361 | #define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \ | |
| 362 | UART_FIFO_PARERR_MASK | \ | |
| 363 | UART_FIFO_BRKDET_MASK) | |
| 364 | ||
| 365 | ||
| 366 | /************************************************************************* | |
| 367 | * _REG relative to RSET_GPIO | |
| 368 | *************************************************************************/ | |
| 369 | ||
| 370 | /* GPIO registers */ | |
| 371 | #define GPIO_CTL_HI_REG 0x0 | |
| 372 | #define GPIO_CTL_LO_REG 0x4 | |
| 373 | #define GPIO_DATA_HI_REG 0x8 | |
| 374 | #define GPIO_DATA_LO_REG 0xC | |
| 375 | ||
| 376 | /* GPIO mux registers and constants */ | |
| 377 | #define GPIO_MODE_REG 0x18 | |
| 378 | ||
| 379 | #define GPIO_MODE_6348_G4_DIAG 0x00090000 | |
| 380 | #define GPIO_MODE_6348_G4_UTOPIA 0x00080000 | |
| 381 | #define GPIO_MODE_6348_G4_LEGACY_LED 0x00030000 | |
| 382 | #define GPIO_MODE_6348_G4_MII_SNOOP 0x00020000 | |
| 383 | #define GPIO_MODE_6348_G4_EXT_EPHY 0x00010000 | |
| 384 | #define GPIO_MODE_6348_G3_DIAG 0x00009000 | |
| 385 | #define GPIO_MODE_6348_G3_UTOPIA 0x00008000 | |
| 386 | #define GPIO_MODE_6348_G3_EXT_MII 0x00007000 | |
| 387 | #define GPIO_MODE_6348_G2_DIAG 0x00000900 | |
| 388 | #define GPIO_MODE_6348_G2_PCI 0x00000500 | |
| 389 | #define GPIO_MODE_6348_G1_DIAG 0x00000090 | |
| 390 | #define GPIO_MODE_6348_G1_UTOPIA 0x00000080 | |
| 391 | #define GPIO_MODE_6348_G1_SPI_UART 0x00000060 | |
| 392 | #define GPIO_MODE_6348_G1_SPI_MASTER 0x00000060 | |
| 393 | #define GPIO_MODE_6348_G1_MII_PCCARD 0x00000040 | |
| 394 | #define GPIO_MODE_6348_G1_MII_SNOOP 0x00000020 | |
| 395 | #define GPIO_MODE_6348_G1_EXT_EPHY 0x00000010 | |
| 396 | #define GPIO_MODE_6348_G0_DIAG 0x00000009 | |
| 397 | #define GPIO_MODE_6348_G0_EXT_MII 0x00000007 | |
| 398 | ||
| 399 | #define GPIO_MODE_6358_EXTRACS (1 << 5) | |
| 400 | #define GPIO_MODE_6358_UART1 (1 << 6) | |
| 401 | #define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7) | |
| 402 | #define GPIO_MODE_6358_SERIAL_LED (1 << 10) | |
| 403 | #define GPIO_MODE_6358_UTOPIA (1 << 12) | |
| 404 | ||
| 405 | ||
| 406 | /************************************************************************* | |
| 407 | * _REG relative to RSET_ENET | |
| 408 | *************************************************************************/ | |
| 409 | ||
| 410 | /* Receiver Configuration register */ | |
| 411 | #define ENET_RXCFG_REG 0x0 | |
| 412 | #define ENET_RXCFG_ALLMCAST_SHIFT 1 | |
| 413 | #define ENET_RXCFG_ALLMCAST_MASK (1 << ENET_RXCFG_ALLMCAST_SHIFT) | |
| 414 | #define ENET_RXCFG_PROMISC_SHIFT 3 | |
| 415 | #define ENET_RXCFG_PROMISC_MASK (1 << ENET_RXCFG_PROMISC_SHIFT) | |
| 416 | #define ENET_RXCFG_LOOPBACK_SHIFT 4 | |
| 417 | #define ENET_RXCFG_LOOPBACK_MASK (1 << ENET_RXCFG_LOOPBACK_SHIFT) | |
| 418 | #define ENET_RXCFG_ENFLOW_SHIFT 5 | |
| 419 | #define ENET_RXCFG_ENFLOW_MASK (1 << ENET_RXCFG_ENFLOW_SHIFT) | |
| 420 | ||
| 421 | /* Receive Maximum Length register */ | |
| 422 | #define ENET_RXMAXLEN_REG 0x4 | |
| 423 | #define ENET_RXMAXLEN_SHIFT 0 | |
| 424 | #define ENET_RXMAXLEN_MASK (0x7ff << ENET_RXMAXLEN_SHIFT) | |
| 425 | ||
| 426 | /* Transmit Maximum Length register */ | |
| 427 | #define ENET_TXMAXLEN_REG 0x8 | |
| 428 | #define ENET_TXMAXLEN_SHIFT 0 | |
| 429 | #define ENET_TXMAXLEN_MASK (0x7ff << ENET_TXMAXLEN_SHIFT) | |
| 430 | ||
| 431 | /* MII Status/Control register */ | |
| 432 | #define ENET_MIISC_REG 0x10 | |
| 433 | #define ENET_MIISC_MDCFREQDIV_SHIFT 0 | |
| 434 | #define ENET_MIISC_MDCFREQDIV_MASK (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT) | |
| 435 | #define ENET_MIISC_PREAMBLEEN_SHIFT 7 | |
| 436 | #define ENET_MIISC_PREAMBLEEN_MASK (1 << ENET_MIISC_PREAMBLEEN_SHIFT) | |
| 437 | ||
| 438 | /* MII Data register */ | |
| 439 | #define ENET_MIIDATA_REG 0x14 | |
| 440 | #define ENET_MIIDATA_DATA_SHIFT 0 | |
| 441 | #define ENET_MIIDATA_DATA_MASK (0xffff << ENET_MIIDATA_DATA_SHIFT) | |
| 442 | #define ENET_MIIDATA_TA_SHIFT 16 | |
| 443 | #define ENET_MIIDATA_TA_MASK (0x3 << ENET_MIIDATA_TA_SHIFT) | |
| 444 | #define ENET_MIIDATA_REG_SHIFT 18 | |
| 445 | #define ENET_MIIDATA_REG_MASK (0x1f << ENET_MIIDATA_REG_SHIFT) | |
| 446 | #define ENET_MIIDATA_PHYID_SHIFT 23 | |
| 447 | #define ENET_MIIDATA_PHYID_MASK (0x1f << ENET_MIIDATA_PHYID_SHIFT) | |
| 448 | #define ENET_MIIDATA_OP_READ_MASK (0x6 << 28) | |
| 449 | #define ENET_MIIDATA_OP_WRITE_MASK (0x5 << 28) | |
| 450 | ||
| 451 | /* Ethernet Interrupt Mask register */ | |
| 452 | #define ENET_IRMASK_REG 0x18 | |
| 453 | ||
| 454 | /* Ethernet Interrupt register */ | |
| 455 | #define ENET_IR_REG 0x1c | |
| 456 | #define ENET_IR_MII (1 << 0) | |
| 457 | #define ENET_IR_MIB (1 << 1) | |
| 458 | #define ENET_IR_FLOWC (1 << 2) | |
| 459 | ||
| 460 | /* Ethernet Control register */ | |
| 461 | #define ENET_CTL_REG 0x2c | |
| 462 | #define ENET_CTL_ENABLE_SHIFT 0 | |
| 463 | #define ENET_CTL_ENABLE_MASK (1 << ENET_CTL_ENABLE_SHIFT) | |
| 464 | #define ENET_CTL_DISABLE_SHIFT 1 | |
| 465 | #define ENET_CTL_DISABLE_MASK (1 << ENET_CTL_DISABLE_SHIFT) | |
| 466 | #define ENET_CTL_SRESET_SHIFT 2 | |
| 467 | #define ENET_CTL_SRESET_MASK (1 << ENET_CTL_SRESET_SHIFT) | |
| 468 | #define ENET_CTL_EPHYSEL_SHIFT 3 | |
| 469 | #define ENET_CTL_EPHYSEL_MASK (1 << ENET_CTL_EPHYSEL_SHIFT) | |
| 470 | ||
| 471 | /* Transmit Control register */ | |
| 472 | #define ENET_TXCTL_REG 0x30 | |
| 473 | #define ENET_TXCTL_FD_SHIFT 0 | |
| 474 | #define ENET_TXCTL_FD_MASK (1 << ENET_TXCTL_FD_SHIFT) | |
| 475 | ||
| 476 | /* Transmit Watermask register */ | |
| 477 | #define ENET_TXWMARK_REG 0x34 | |
| 478 | #define ENET_TXWMARK_WM_SHIFT 0 | |
| 479 | #define ENET_TXWMARK_WM_MASK (0x3f << ENET_TXWMARK_WM_SHIFT) | |
| 480 | ||
| 481 | /* MIB Control register */ | |
| 482 | #define ENET_MIBCTL_REG 0x38 | |
| 483 | #define ENET_MIBCTL_RDCLEAR_SHIFT 0 | |
| 484 | #define ENET_MIBCTL_RDCLEAR_MASK (1 << ENET_MIBCTL_RDCLEAR_SHIFT) | |
| 485 | ||
| 486 | /* Perfect Match Data Low register */ | |
| 487 | #define ENET_PML_REG(x) (0x58 + (x) * 8) | |
| 488 | #define ENET_PMH_REG(x) (0x5c + (x) * 8) | |
| 489 | #define ENET_PMH_DATAVALID_SHIFT 16 | |
| 490 | #define ENET_PMH_DATAVALID_MASK (1 << ENET_PMH_DATAVALID_SHIFT) | |
| 491 | ||
| 492 | /* MIB register */ | |
| 493 | #define ENET_MIB_REG(x) (0x200 + (x) * 4) | |
| 494 | #define ENET_MIB_REG_COUNT 55 | |
| 495 | ||
| 496 | ||
| 497 | /************************************************************************* | |
| 498 | * _REG relative to RSET_ENETDMA | |
| 499 | *************************************************************************/ | |
| 500 | ||
| 501 | /* Controller Configuration Register */ | |
| 502 | #define ENETDMA_CFG_REG (0x0) | |
| 503 | #define ENETDMA_CFG_EN_SHIFT 0 | |
| 504 | #define ENETDMA_CFG_EN_MASK (1 << ENETDMA_CFG_EN_SHIFT) | |
| 505 | #define ENETDMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1)) | |
| 506 | ||
| 507 | /* Flow Control Descriptor Low Threshold register */ | |
| 508 | #define ENETDMA_FLOWCL_REG(x) (0x4 + (x) * 6) | |
| 509 | ||
| 510 | /* Flow Control Descriptor High Threshold register */ | |
| 511 | #define ENETDMA_FLOWCH_REG(x) (0x8 + (x) * 6) | |
| 512 | ||
| 513 | /* Flow Control Descriptor Buffer Alloca Threshold register */ | |
| 514 | #define ENETDMA_BUFALLOC_REG(x) (0xc + (x) * 6) | |
| 515 | #define ENETDMA_BUFALLOC_FORCE_SHIFT 31 | |
| 516 | #define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT) | |
| 517 | ||
| 518 | /* Channel Configuration register */ | |
| 519 | #define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10) | |
| 520 | #define ENETDMA_CHANCFG_EN_SHIFT 0 | |
| 521 | #define ENETDMA_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT) | |
| 522 | #define ENETDMA_CHANCFG_PKTHALT_SHIFT 1 | |
| 523 | #define ENETDMA_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT) | |
| 524 | ||
| 525 | /* Interrupt Control/Status register */ | |
| 526 | #define ENETDMA_IR_REG(x) (0x104 + (x) * 0x10) | |
| 527 | #define ENETDMA_IR_BUFDONE_MASK (1 << 0) | |
| 528 | #define ENETDMA_IR_PKTDONE_MASK (1 << 1) | |
| 529 | #define ENETDMA_IR_NOTOWNER_MASK (1 << 2) | |
| 530 | ||
| 531 | /* Interrupt Mask register */ | |
| 532 | #define ENETDMA_IRMASK_REG(x) (0x108 + (x) * 0x10) | |
| 533 | ||
| 534 | /* Maximum Burst Length */ | |
| 535 | #define ENETDMA_MAXBURST_REG(x) (0x10C + (x) * 0x10) | |
| 536 | ||
| 537 | /* Ring Start Address register */ | |
| 538 | #define ENETDMA_RSTART_REG(x) (0x200 + (x) * 0x10) | |
| 539 | ||
| 540 | /* State Ram Word 2 */ | |
| 541 | #define ENETDMA_SRAM2_REG(x) (0x204 + (x) * 0x10) | |
| 542 | ||
| 543 | /* State Ram Word 3 */ | |
| 544 | #define ENETDMA_SRAM3_REG(x) (0x208 + (x) * 0x10) | |
| 545 | ||
| 546 | /* State Ram Word 4 */ | |
| 547 | #define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10) | |
| 548 | ||
| 549 | ||
| d430b6c5 MB |
550 | /************************************************************************* |
| 551 | * _REG relative to RSET_ENETDMAC | |
| 552 | *************************************************************************/ | |
| 553 | ||
| 554 | /* Channel Configuration register */ | |
| 555 | #define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10) | |
| 556 | #define ENETDMAC_CHANCFG_EN_SHIFT 0 | |
| 557 | #define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT) | |
| 558 | #define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1 | |
| 559 | #define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT) | |
| 560 | ||
| 561 | /* Interrupt Control/Status register */ | |
| 562 | #define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10) | |
| 563 | #define ENETDMAC_IR_BUFDONE_MASK (1 << 0) | |
| 564 | #define ENETDMAC_IR_PKTDONE_MASK (1 << 1) | |
| 565 | #define ENETDMAC_IR_NOTOWNER_MASK (1 << 2) | |
| 566 | ||
| 567 | /* Interrupt Mask register */ | |
| 568 | #define ENETDMAC_IRMASK_REG(x) (0x8 + (x) * 0x10) | |
| 569 | ||
| 570 | /* Maximum Burst Length */ | |
| 571 | #define ENETDMAC_MAXBURST_REG(x) (0xc + (x) * 0x10) | |
| 572 | ||
| 573 | ||
| 574 | /************************************************************************* | |
| 575 | * _REG relative to RSET_ENETDMAS | |
| 576 | *************************************************************************/ | |
| 577 | ||
| 578 | /* Ring Start Address register */ | |
| 579 | #define ENETDMAS_RSTART_REG(x) ((x) * 0x10) | |
| 580 | ||
| 581 | /* State Ram Word 2 */ | |
| 582 | #define ENETDMAS_SRAM2_REG(x) (0x4 + (x) * 0x10) | |
| 583 | ||
| 584 | /* State Ram Word 3 */ | |
| 585 | #define ENETDMAS_SRAM3_REG(x) (0x8 + (x) * 0x10) | |
| 586 | ||
| 587 | /* State Ram Word 4 */ | |
| 588 | #define ENETDMAS_SRAM4_REG(x) (0xc + (x) * 0x10) | |
| 589 | ||
| 590 | ||
| 591 | /************************************************************************* | |
| 592 | * _REG relative to RSET_ENETSW | |
| 593 | *************************************************************************/ | |
| 594 | ||
| 595 | /* MIB register */ | |
| 596 | #define ENETSW_MIB_REG(x) (0x2800 + (x) * 4) | |
| 597 | #define ENETSW_MIB_REG_COUNT 47 | |
| 598 | ||
| 599 | ||
| e7300d04 MB |
600 | /************************************************************************* |
| 601 | * _REG relative to RSET_OHCI_PRIV | |
| 602 | *************************************************************************/ | |
| 603 | ||
| 604 | #define OHCI_PRIV_REG 0x0 | |
| 605 | #define OHCI_PRIV_PORT1_HOST_SHIFT 0 | |
| 606 | #define OHCI_PRIV_PORT1_HOST_MASK (1 << OHCI_PRIV_PORT1_HOST_SHIFT) | |
| 607 | #define OHCI_PRIV_REG_SWAP_SHIFT 3 | |
| 608 | #define OHCI_PRIV_REG_SWAP_MASK (1 << OHCI_PRIV_REG_SWAP_SHIFT) | |
| 609 | ||
| 610 | ||
| 611 | /************************************************************************* | |
| 612 | * _REG relative to RSET_USBH_PRIV | |
| 613 | *************************************************************************/ | |
| 614 | ||
| 615 | #define USBH_PRIV_SWAP_REG 0x0 | |
| 616 | #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4 | |
| 617 | #define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT) | |
| 618 | #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3 | |
| 619 | #define USBH_PRIV_SWAP_EHCI_DATA_MASK (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT) | |
| 620 | #define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT 1 | |
| 621 | #define USBH_PRIV_SWAP_OHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT) | |
| 622 | #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0 | |
| 623 | #define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT) | |
| 624 | ||
| 625 | #define USBH_PRIV_TEST_REG 0x24 | |
| 626 | ||
| 627 | ||
| 628 | /************************************************************************* | |
| 629 | * _REG relative to RSET_MPI | |
| 630 | *************************************************************************/ | |
| 631 | ||
| 632 | /* well known (hard wired) chip select */ | |
| 633 | #define MPI_CS_PCMCIA_COMMON 4 | |
| 634 | #define MPI_CS_PCMCIA_ATTR 5 | |
| 635 | #define MPI_CS_PCMCIA_IO 6 | |
| 636 | ||
| 637 | /* Chip select base register */ | |
| 638 | #define MPI_CSBASE_REG(x) (0x0 + (x) * 8) | |
| 639 | #define MPI_CSBASE_BASE_SHIFT 13 | |
| 640 | #define MPI_CSBASE_BASE_MASK (0x1ffff << MPI_CSBASE_BASE_SHIFT) | |
| 641 | #define MPI_CSBASE_SIZE_SHIFT 0 | |
| 642 | #define MPI_CSBASE_SIZE_MASK (0xf << MPI_CSBASE_SIZE_SHIFT) | |
| 643 | ||
| 644 | #define MPI_CSBASE_SIZE_8K 0 | |
| 645 | #define MPI_CSBASE_SIZE_16K 1 | |
| 646 | #define MPI_CSBASE_SIZE_32K 2 | |
| 647 | #define MPI_CSBASE_SIZE_64K 3 | |
| 648 | #define MPI_CSBASE_SIZE_128K 4 | |
| 649 | #define MPI_CSBASE_SIZE_256K 5 | |
| 650 | #define MPI_CSBASE_SIZE_512K 6 | |
| 651 | #define MPI_CSBASE_SIZE_1M 7 | |
| 652 | #define MPI_CSBASE_SIZE_2M 8 | |
| 653 | #define MPI_CSBASE_SIZE_4M 9 | |
| 654 | #define MPI_CSBASE_SIZE_8M 10 | |
| 655 | #define MPI_CSBASE_SIZE_16M 11 | |
| 656 | #define MPI_CSBASE_SIZE_32M 12 | |
| 657 | #define MPI_CSBASE_SIZE_64M 13 | |
| 658 | #define MPI_CSBASE_SIZE_128M 14 | |
| 659 | #define MPI_CSBASE_SIZE_256M 15 | |
| 660 | ||
| 661 | /* Chip select control register */ | |
| 662 | #define MPI_CSCTL_REG(x) (0x4 + (x) * 8) | |
| 663 | #define MPI_CSCTL_ENABLE_MASK (1 << 0) | |
| 664 | #define MPI_CSCTL_WAIT_SHIFT 1 | |
| 665 | #define MPI_CSCTL_WAIT_MASK (0x7 << MPI_CSCTL_WAIT_SHIFT) | |
| 666 | #define MPI_CSCTL_DATA16_MASK (1 << 4) | |
| 667 | #define MPI_CSCTL_SYNCMODE_MASK (1 << 7) | |
| 668 | #define MPI_CSCTL_TSIZE_MASK (1 << 8) | |
| 669 | #define MPI_CSCTL_ENDIANSWAP_MASK (1 << 10) | |
| 670 | #define MPI_CSCTL_SETUP_SHIFT 16 | |
| 671 | #define MPI_CSCTL_SETUP_MASK (0xf << MPI_CSCTL_SETUP_SHIFT) | |
| 672 | #define MPI_CSCTL_HOLD_SHIFT 20 | |
| 673 | #define MPI_CSCTL_HOLD_MASK (0xf << MPI_CSCTL_HOLD_SHIFT) | |
| 674 | ||
| 675 | /* PCI registers */ | |
| 676 | #define MPI_SP0_RANGE_REG 0x100 | |
| 677 | #define MPI_SP0_REMAP_REG 0x104 | |
| 678 | #define MPI_SP0_REMAP_ENABLE_MASK (1 << 0) | |
| 679 | #define MPI_SP1_RANGE_REG 0x10C | |
| 680 | #define MPI_SP1_REMAP_REG 0x110 | |
| 681 | #define MPI_SP1_REMAP_ENABLE_MASK (1 << 0) | |
| 682 | ||
| 683 | #define MPI_L2PCFG_REG 0x11C | |
| 684 | #define MPI_L2PCFG_CFG_TYPE_SHIFT 0 | |
| 685 | #define MPI_L2PCFG_CFG_TYPE_MASK (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT) | |
| 686 | #define MPI_L2PCFG_REG_SHIFT 2 | |
| 687 | #define MPI_L2PCFG_REG_MASK (0x3f << MPI_L2PCFG_REG_SHIFT) | |
| 688 | #define MPI_L2PCFG_FUNC_SHIFT 8 | |
| 689 | #define MPI_L2PCFG_FUNC_MASK (0x7 << MPI_L2PCFG_FUNC_SHIFT) | |
| 690 | #define MPI_L2PCFG_DEVNUM_SHIFT 11 | |
| 691 | #define MPI_L2PCFG_DEVNUM_MASK (0x1f << MPI_L2PCFG_DEVNUM_SHIFT) | |
| 692 | #define MPI_L2PCFG_CFG_USEREG_MASK (1 << 30) | |
| 693 | #define MPI_L2PCFG_CFG_SEL_MASK (1 << 31) | |
| 694 | ||
| 695 | #define MPI_L2PMEMRANGE1_REG 0x120 | |
| 696 | #define MPI_L2PMEMBASE1_REG 0x124 | |
| 697 | #define MPI_L2PMEMREMAP1_REG 0x128 | |
| 698 | #define MPI_L2PMEMRANGE2_REG 0x12C | |
| 699 | #define MPI_L2PMEMBASE2_REG 0x130 | |
| 700 | #define MPI_L2PMEMREMAP2_REG 0x134 | |
| 701 | #define MPI_L2PIORANGE_REG 0x138 | |
| 702 | #define MPI_L2PIOBASE_REG 0x13C | |
| 703 | #define MPI_L2PIOREMAP_REG 0x140 | |
| 704 | #define MPI_L2P_BASE_MASK (0xffff8000) | |
| 705 | #define MPI_L2PREMAP_ENABLED_MASK (1 << 0) | |
| 706 | #define MPI_L2PREMAP_IS_CARDBUS_MASK (1 << 2) | |
| 707 | ||
| 708 | #define MPI_PCIMODESEL_REG 0x144 | |
| 709 | #define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0) | |
| 710 | #define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1) | |
| 711 | #define MPI_PCIMODESEL_EXT_ARB_MASK (1 << 2) | |
| 712 | #define MPI_PCIMODESEL_PREFETCH_SHIFT 4 | |
| 713 | #define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT) | |
| 714 | ||
| 715 | #define MPI_LOCBUSCTL_REG 0x14C | |
| 716 | #define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0) | |
| 717 | #define MPI_LOCBUSCTL_U2P_NOSWAP_MASK (1 << 1) | |
| 718 | ||
| 719 | #define MPI_LOCINT_REG 0x150 | |
| 720 | #define MPI_LOCINT_MASK(x) (1 << (x + 16)) | |
| 721 | #define MPI_LOCINT_STAT(x) (1 << (x)) | |
| 722 | #define MPI_LOCINT_DIR_FAILED 6 | |
| 723 | #define MPI_LOCINT_EXT_PCI_INT 7 | |
| 724 | #define MPI_LOCINT_SERR 8 | |
| 725 | #define MPI_LOCINT_CSERR 9 | |
| 726 | ||
| 727 | #define MPI_PCICFGCTL_REG 0x178 | |
| 728 | #define MPI_PCICFGCTL_CFGADDR_SHIFT 2 | |
| 729 | #define MPI_PCICFGCTL_CFGADDR_MASK (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT) | |
| 730 | #define MPI_PCICFGCTL_WRITEEN_MASK (1 << 7) | |
| 731 | ||
| 732 | #define MPI_PCICFGDATA_REG 0x17C | |
| 733 | ||
| 734 | /* PCI host bridge custom register */ | |
| 735 | #define BCMPCI_REG_TIMERS 0x40 | |
| 736 | #define REG_TIMER_TRDY_SHIFT 0 | |
| 737 | #define REG_TIMER_TRDY_MASK (0xff << REG_TIMER_TRDY_SHIFT) | |
| 738 | #define REG_TIMER_RETRY_SHIFT 8 | |
| 739 | #define REG_TIMER_RETRY_MASK (0xff << REG_TIMER_RETRY_SHIFT) | |
| 740 | ||
| 741 | ||
| 742 | /************************************************************************* | |
| 743 | * _REG relative to RSET_PCMCIA | |
| 744 | *************************************************************************/ | |
| 745 | ||
| 746 | #define PCMCIA_C1_REG 0x0 | |
| 747 | #define PCMCIA_C1_CD1_MASK (1 << 0) | |
| 748 | #define PCMCIA_C1_CD2_MASK (1 << 1) | |
| 749 | #define PCMCIA_C1_VS1_MASK (1 << 2) | |
| 750 | #define PCMCIA_C1_VS2_MASK (1 << 3) | |
| 751 | #define PCMCIA_C1_VS1OE_MASK (1 << 6) | |
| 752 | #define PCMCIA_C1_VS2OE_MASK (1 << 7) | |
| 753 | #define PCMCIA_C1_CBIDSEL_SHIFT (8) | |
| 754 | #define PCMCIA_C1_CBIDSEL_MASK (0x1f << PCMCIA_C1_CBIDSEL_SHIFT) | |
| 755 | #define PCMCIA_C1_EN_PCMCIA_GPIO_MASK (1 << 13) | |
| 756 | #define PCMCIA_C1_EN_PCMCIA_MASK (1 << 14) | |
| 757 | #define PCMCIA_C1_EN_CARDBUS_MASK (1 << 15) | |
| 758 | #define PCMCIA_C1_RESET_MASK (1 << 18) | |
| 759 | ||
| 760 | #define PCMCIA_C2_REG 0x8 | |
| 761 | #define PCMCIA_C2_DATA16_MASK (1 << 0) | |
| 762 | #define PCMCIA_C2_BYTESWAP_MASK (1 << 1) | |
| 763 | #define PCMCIA_C2_RWCOUNT_SHIFT 2 | |
| 764 | #define PCMCIA_C2_RWCOUNT_MASK (0x3f << PCMCIA_C2_RWCOUNT_SHIFT) | |
| 765 | #define PCMCIA_C2_INACTIVE_SHIFT 8 | |
| 766 | #define PCMCIA_C2_INACTIVE_MASK (0x3f << PCMCIA_C2_INACTIVE_SHIFT) | |
| 767 | #define PCMCIA_C2_SETUP_SHIFT 16 | |
| 768 | #define PCMCIA_C2_SETUP_MASK (0x3f << PCMCIA_C2_SETUP_SHIFT) | |
| 769 | #define PCMCIA_C2_HOLD_SHIFT 24 | |
| 770 | #define PCMCIA_C2_HOLD_MASK (0x3f << PCMCIA_C2_HOLD_SHIFT) | |
| 771 | ||
| 772 | ||
| 773 | /************************************************************************* | |
| 774 | * _REG relative to RSET_SDRAM | |
| 775 | *************************************************************************/ | |
| 776 | ||
| 777 | #define SDRAM_CFG_REG 0x0 | |
| 778 | #define SDRAM_CFG_ROW_SHIFT 4 | |
| 779 | #define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT) | |
| 780 | #define SDRAM_CFG_COL_SHIFT 6 | |
| 781 | #define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT) | |
| 782 | #define SDRAM_CFG_32B_SHIFT 10 | |
| 783 | #define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT) | |
| 784 | #define SDRAM_CFG_BANK_SHIFT 13 | |
| 785 | #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT) | |
| 786 | ||
| 787 | #define SDRAM_PRIO_REG 0x2C | |
| 788 | #define SDRAM_PRIO_MIPS_SHIFT 29 | |
| 789 | #define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT) | |
| 790 | #define SDRAM_PRIO_ADSL_SHIFT 30 | |
| 791 | #define SDRAM_PRIO_ADSL_MASK (1 << SDRAM_PRIO_ADSL_SHIFT) | |
| 792 | #define SDRAM_PRIO_EN_SHIFT 31 | |
| 793 | #define SDRAM_PRIO_EN_MASK (1 << SDRAM_PRIO_EN_SHIFT) | |
| 794 | ||
| 795 | ||
| 796 | /************************************************************************* | |
| 797 | * _REG relative to RSET_MEMC | |
| 798 | *************************************************************************/ | |
| 799 | ||
| 800 | #define MEMC_CFG_REG 0x4 | |
| 801 | #define MEMC_CFG_32B_SHIFT 1 | |
| 802 | #define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT) | |
| 803 | #define MEMC_CFG_COL_SHIFT 3 | |
| 804 | #define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT) | |
| 805 | #define MEMC_CFG_ROW_SHIFT 6 | |
| 806 | #define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT) | |
| 807 | ||
| 808 | ||
| 809 | /************************************************************************* | |
| 810 | * _REG relative to RSET_DDR | |
| 811 | *************************************************************************/ | |
| 812 | ||
| 813 | #define DDR_DMIPSPLLCFG_REG 0x18 | |
| 814 | #define DMIPSPLLCFG_M1_SHIFT 0 | |
| 815 | #define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT) | |
| 816 | #define DMIPSPLLCFG_N1_SHIFT 23 | |
| 817 | #define DMIPSPLLCFG_N1_MASK (0x3f << DMIPSPLLCFG_N1_SHIFT) | |
| 818 | #define DMIPSPLLCFG_N2_SHIFT 29 | |
| 819 | #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT) | |
| 820 | ||
| d430b6c5 MB |
821 | /************************************************************************* |
| 822 | * _REG relative to RSET_M2M | |
| 823 | *************************************************************************/ | |
| 824 | ||
| 825 | #define M2M_RX 0 | |
| 826 | #define M2M_TX 1 | |
| 827 | ||
| 828 | #define M2M_SRC_REG(x) ((x) * 0x40 + 0x00) | |
| 829 | #define M2M_DST_REG(x) ((x) * 0x40 + 0x04) | |
| 830 | #define M2M_SIZE_REG(x) ((x) * 0x40 + 0x08) | |
| 831 | ||
| 832 | #define M2M_CTRL_REG(x) ((x) * 0x40 + 0x0c) | |
| 833 | #define M2M_CTRL_ENABLE_MASK (1 << 0) | |
| 834 | #define M2M_CTRL_IRQEN_MASK (1 << 1) | |
| 835 | #define M2M_CTRL_ERROR_CLR_MASK (1 << 6) | |
| 836 | #define M2M_CTRL_DONE_CLR_MASK (1 << 7) | |
| 837 | #define M2M_CTRL_NOINC_MASK (1 << 8) | |
| 838 | #define M2M_CTRL_PCMCIASWAP_MASK (1 << 9) | |
| 839 | #define M2M_CTRL_SWAPBYTE_MASK (1 << 10) | |
| 840 | #define M2M_CTRL_ENDIAN_MASK (1 << 11) | |
| 841 | ||
| 842 | #define M2M_STAT_REG(x) ((x) * 0x40 + 0x10) | |
| 843 | #define M2M_STAT_DONE (1 << 0) | |
| 844 | #define M2M_STAT_ERROR (1 << 1) | |
| 845 | ||
| 846 | #define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14) | |
| 847 | #define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18) | |
| 848 | ||
| e7300d04 | 849 | #endif /* BCM63XX_REGS_H_ */ |