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c011db45 RB |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
798d9023 | 6 | * Copyright (C) 2006, 07 Ralf Baechle (ralf@linux-mips.org) |
c011db45 RB |
7 | */ |
8 | #ifndef __ASM_COBALT_CPU_FEATURE_OVERRIDES_H | |
9 | #define __ASM_COBALT_CPU_FEATURE_OVERRIDES_H | |
10 | ||
c011db45 RB |
11 | |
12 | #define cpu_has_tlb 1 | |
13 | #define cpu_has_4kex 1 | |
14 | #define cpu_has_3k_cache 0 | |
15 | #define cpu_has_4k_cache 1 | |
16 | #define cpu_has_tx39_cache 0 | |
c011db45 RB |
17 | #define cpu_has_fpu 1 |
18 | #define cpu_has_32fpr 1 | |
19 | #define cpu_has_counter 1 | |
20 | #define cpu_has_watch 0 | |
21 | #define cpu_has_divec 1 | |
22 | #define cpu_has_vce 0 | |
23 | #define cpu_has_cache_cdex_p 0 | |
24 | #define cpu_has_cache_cdex_s 0 | |
25 | #define cpu_has_prefetch 0 | |
26 | #define cpu_has_mcheck 0 | |
27 | #define cpu_has_ejtag 0 | |
28 | ||
fc5d2d27 | 29 | #define cpu_has_inclusive_pcaches 0 |
c011db45 RB |
30 | #define cpu_dcache_line_size() 32 |
31 | #define cpu_icache_line_size() 32 | |
32 | #define cpu_scache_line_size() 0 | |
33 | ||
34 | #ifdef CONFIG_64BIT | |
35 | #define cpu_has_llsc 0 | |
36 | #else | |
37 | #define cpu_has_llsc 1 | |
38 | #endif | |
39 | ||
40 | #define cpu_has_mips16 0 | |
41 | #define cpu_has_mdmx 0 | |
42 | #define cpu_has_mips3d 0 | |
43 | #define cpu_has_smartmips 0 | |
44 | #define cpu_has_vtag_icache 0 | |
45 | #define cpu_has_ic_fills_f_dc 0 | |
46 | #define cpu_icache_snoops_remote_store 0 | |
47 | #define cpu_has_dsp 0 | |
47503256 | 48 | #define cpu_has_dsp2 0 |
798d9023 | 49 | #define cpu_has_mipsmt 0 |
ed203dad | 50 | #define cpu_has_userlocal 0 |
c011db45 RB |
51 | |
52 | #define cpu_has_mips32r1 0 | |
53 | #define cpu_has_mips32r2 0 | |
54 | #define cpu_has_mips64r1 0 | |
55 | #define cpu_has_mips64r2 0 | |
56 | ||
57 | #endif /* __ASM_COBALT_CPU_FEATURE_OVERRIDES_H */ |