MIPS: Hardwire detection of DSP ASE Rev 2 for systems, as required.
[deliverable/linux.git] / arch / mips / include / asm / mach-ip28 / cpu-feature-overrides.h
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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 Ralf Baechle
7 * 6/2004 pf
8 */
9#ifndef __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H
10#define __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H
11
12/*
13 * IP28 only comes with R10000 family processors all using the same config
14 */
15#define cpu_has_watch 1
16#define cpu_has_mips16 0
17#define cpu_has_divec 0
18#define cpu_has_vce 0
19#define cpu_has_cache_cdex_p 0
20#define cpu_has_cache_cdex_s 0
21#define cpu_has_prefetch 1
22#define cpu_has_mcheck 0
23#define cpu_has_ejtag 0
24
25#define cpu_has_llsc 1
26#define cpu_has_vtag_icache 0
27#define cpu_has_dc_aliases 0 /* see probe_pcache() */
28#define cpu_has_ic_fills_f_dc 0
29#define cpu_has_dsp 0
47503256 30#define cpu_has_dsp2 0
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31#define cpu_icache_snoops_remote_store 1
32#define cpu_has_mipsmt 0
33#define cpu_has_userlocal 0
34
35#define cpu_has_nofpuex 0
36#define cpu_has_64bits 1
37
38#define cpu_has_4kex 1
39#define cpu_has_4k_cache 1
40
41#define cpu_has_inclusive_pcaches 1
42
43#define cpu_dcache_line_size() 32
44#define cpu_icache_line_size() 64
45
46#define cpu_has_mips32r1 0
47#define cpu_has_mips32r2 0
48#define cpu_has_mips64r1 0
49#define cpu_has_mips64r2 0
50
51#endif /* __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H */
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