[deliverable/linux.git] / arch / mips / include / asm / mach-loongson / loongson.h

/*
 * Copyright (C) 2009 Lemote, Inc.
 * Author: Wu Zhangjin <wuzhangjin@gmail.com>
 *
 * This program is free software; you can redistribute	it and/or modify it
 * under  the terms of	the GNU General	 Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#ifndef __ASM_MACH_LOONGSON_LOONGSON_H
#define __ASM_MACH_LOONGSON_LOONGSON_H

#include <linux/io.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/kconfig.h>
#include <boot_param.h>

/* loongson internal northbridge initialization */
extern void bonito_irq_init(void);

/* machine-specific reboot/halt operation */
extern void mach_prepare_reboot(void);
extern void mach_prepare_shutdown(void);

/* environment arguments from bootloader */
extern u32 cpu_clock_freq;
extern u32 memsize, highmemsize;
extern struct plat_smp_ops loongson3_smp_ops;

/* loongson-specific command line, env and memory initialization */
extern void __init prom_init_memory(void);
extern void __init prom_init_cmdline(void);
extern void __init prom_init_machtype(void);
extern void __init prom_init_env(void);
#ifdef CONFIG_LOONGSON_UART_BASE
extern unsigned long _loongson_uart_base, loongson_uart_base;
extern void prom_init_loongson_uart_base(void);
#endif

static inline void prom_init_uart_base(void)
{
#ifdef CONFIG_LOONGSON_UART_BASE
	prom_init_loongson_uart_base();
#endif
}

/* irq operation functions */
extern void bonito_irqdispatch(void);
extern void __init bonito_irq_init(void);
extern void __init mach_init_irq(void);
extern void mach_irq_dispatch(unsigned int pending);
extern int mach_i8259_irq(void);

/* We need this in some places... */
#define delay() ({		\
	int x;				\
	for (x = 0; x < 100000; x++)	\
		__asm__ __volatile__(""); \
})

#define LOONGSON_REG(x) \
	(*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))

#define LOONGSON3_REG8(base, x) \
	(*(volatile u8 *)((char *)TO_UNCAC(base) + (x)))

#define LOONGSON3_REG32(base, x) \
	(*(volatile u32 *)((char *)TO_UNCAC(base) + (x)))

#define LOONGSON_IRQ_BASE	32
#define LOONGSON2_PERFCNT_IRQ	(MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */

#include <linux/interrupt.h>
static inline void do_perfcnt_IRQ(void)
{
#if IS_ENABLED(CONFIG_OPROFILE)
	do_IRQ(LOONGSON2_PERFCNT_IRQ);
#endif
}

#define LOONGSON_FLASH_BASE	0x1c000000
#define LOONGSON_FLASH_SIZE	0x02000000	/* 32M */
#define LOONGSON_FLASH_TOP	(LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)

#define LOONGSON_LIO0_BASE	0x1e000000
#define LOONGSON_LIO0_SIZE	0x01C00000	/* 28M */
#define LOONGSON_LIO0_TOP	(LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)

#define LOONGSON_BOOT_BASE	0x1fc00000
#define LOONGSON_BOOT_SIZE	0x00100000	/* 1M */
#define LOONGSON_BOOT_TOP	(LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
#define LOONGSON_REG_BASE	0x1fe00000
#define LOONGSON_REG_SIZE	0x00100000	/* 256Bytes + 256Bytes + ??? */
#define LOONGSON_REG_TOP	(LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
/* Loongson-3 specific registers */
#define LOONGSON3_REG_BASE	0x3ff00000
#define LOONGSON3_REG_SIZE	0x00100000	/* 256Bytes + 256Bytes + ??? */
#define LOONGSON3_REG_TOP	(LOONGSON3_REG_BASE+LOONGSON3_REG_SIZE-1)

#define LOONGSON_LIO1_BASE	0x1ff00000
#define LOONGSON_LIO1_SIZE	0x00100000	/* 1M */
#define LOONGSON_LIO1_TOP	(LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)

#define LOONGSON_PCILO0_BASE	0x10000000
#define LOONGSON_PCILO1_BASE	0x14000000
#define LOONGSON_PCILO2_BASE	0x18000000
#define LOONGSON_PCILO_BASE	LOONGSON_PCILO0_BASE
#define LOONGSON_PCILO_SIZE	0x0c000000	/* 64M * 3 */
#define LOONGSON_PCILO_TOP	(LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1)

#define LOONGSON_PCICFG_BASE	0x1fe80000
#define LOONGSON_PCICFG_SIZE	0x00000800	/* 2K */
#define LOONGSON_PCICFG_TOP	(LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)

#if defined(CONFIG_HT_PCI)
#define LOONGSON_PCIIO_BASE	loongson_sysconf.pci_io_base
#else
#define LOONGSON_PCIIO_BASE	0x1fd00000
#endif

#define LOONGSON_PCIIO_SIZE	0x00100000	/* 1M */
#define LOONGSON_PCIIO_TOP	(LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)

/* Loongson Register Bases */

#define LOONGSON_PCICONFIGBASE	0x00
#define LOONGSON_REGBASE	0x100

/* PCI Configuration Registers */

#define LOONGSON_PCI_REG(x)	LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
#define LOONGSON_PCIDID		LOONGSON_PCI_REG(0x00)
#define LOONGSON_PCICMD		LOONGSON_PCI_REG(0x04)
#define LOONGSON_PCICLASS	LOONGSON_PCI_REG(0x08)
#define LOONGSON_PCILTIMER	LOONGSON_PCI_REG(0x0c)
#define LOONGSON_PCIBASE0	LOONGSON_PCI_REG(0x10)
#define LOONGSON_PCIBASE1	LOONGSON_PCI_REG(0x14)
#define LOONGSON_PCIBASE2	LOONGSON_PCI_REG(0x18)
#define LOONGSON_PCIBASE3	LOONGSON_PCI_REG(0x1c)
#define LOONGSON_PCIBASE4	LOONGSON_PCI_REG(0x20)
#define LOONGSON_PCIEXPRBASE	LOONGSON_PCI_REG(0x30)
#define LOONGSON_PCIINT		LOONGSON_PCI_REG(0x3c)

#define LOONGSON_PCI_ISR4C	LOONGSON_PCI_REG(0x4c)

#define LOONGSON_PCICMD_PERR_CLR	0x80000000
#define LOONGSON_PCICMD_SERR_CLR	0x40000000
#define LOONGSON_PCICMD_MABORT_CLR	0x20000000
#define LOONGSON_PCICMD_MTABORT_CLR	0x10000000
#define LOONGSON_PCICMD_TABORT_CLR	0x08000000
#define LOONGSON_PCICMD_MPERR_CLR	0x01000000
#define LOONGSON_PCICMD_PERRRESPEN	0x00000040
#define LOONGSON_PCICMD_ASTEPEN		0x00000080
#define LOONGSON_PCICMD_SERREN		0x00000100
#define LOONGSON_PCILTIMER_BUSLATENCY	0x0000ff00
#define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT	8

/* Loongson h/w Configuration */

#define LOONGSON_GENCFG_OFFSET		0x4
#define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)

#define LOONGSON_GENCFG_DEBUGMODE	0x00000001
#define LOONGSON_GENCFG_SNOOPEN		0x00000002
#define LOONGSON_GENCFG_CPUSELFRESET	0x00000004

#define LOONGSON_GENCFG_FORCE_IRQA	0x00000008
#define LOONGSON_GENCFG_IRQA_ISOUT	0x00000010
#define LOONGSON_GENCFG_IRQA_FROM_INT1	0x00000020
#define LOONGSON_GENCFG_BYTESWAP	0x00000040

#define LOONGSON_GENCFG_UNCACHED	0x00000080
#define LOONGSON_GENCFG_PREFETCHEN	0x00000100
#define LOONGSON_GENCFG_WBEHINDEN	0x00000200
#define LOONGSON_GENCFG_CACHEALG	0x00000c00
#define LOONGSON_GENCFG_CACHEALG_SHIFT	10
#define LOONGSON_GENCFG_PCIQUEUE	0x00001000
#define LOONGSON_GENCFG_CACHESTOP	0x00002000
#define LOONGSON_GENCFG_MSTRBYTESWAP	0x00004000
#define LOONGSON_GENCFG_BUSERREN	0x00008000
#define LOONGSON_GENCFG_NORETRYTIMEOUT	0x00010000
#define LOONGSON_GENCFG_SHORTCOPYTIMEOUT	0x00020000

/* PCI address map control */

#define LOONGSON_PCIMAP			LOONGSON_REG(LOONGSON_REGBASE + 0x10)
#define LOONGSON_PCIMEMBASECFG		LOONGSON_REG(LOONGSON_REGBASE + 0x14)
#define LOONGSON_PCIMAP_CFG		LOONGSON_REG(LOONGSON_REGBASE + 0x18)

/* GPIO Regs - r/w */

#define LOONGSON_GPIODATA		LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
#define LOONGSON_GPIOIE			LOONGSON_REG(LOONGSON_REGBASE + 0x20)

/* ICU Configuration Regs - r/w */

#define LOONGSON_INTEDGE		LOONGSON_REG(LOONGSON_REGBASE + 0x24)
#define LOONGSON_INTSTEER		LOONGSON_REG(LOONGSON_REGBASE + 0x28)
#define LOONGSON_INTPOL			LOONGSON_REG(LOONGSON_REGBASE + 0x2c)

/* ICU Enable Regs - IntEn & IntISR are r/o. */

#define LOONGSON_INTENSET		LOONGSON_REG(LOONGSON_REGBASE + 0x30)
#define LOONGSON_INTENCLR		LOONGSON_REG(LOONGSON_REGBASE + 0x34)
#define LOONGSON_INTEN			LOONGSON_REG(LOONGSON_REGBASE + 0x38)
#define LOONGSON_INTISR			LOONGSON_REG(LOONGSON_REGBASE + 0x3c)

/* ICU */
#define LOONGSON_ICU_MBOXES		0x0000000f
#define LOONGSON_ICU_MBOXES_SHIFT	0
#define LOONGSON_ICU_DMARDY		0x00000010
#define LOONGSON_ICU_DMAEMPTY		0x00000020
#define LOONGSON_ICU_COPYRDY		0x00000040
#define LOONGSON_ICU_COPYEMPTY		0x00000080
#define LOONGSON_ICU_COPYERR		0x00000100
#define LOONGSON_ICU_PCIIRQ		0x00000200
#define LOONGSON_ICU_MASTERERR		0x00000400
#define LOONGSON_ICU_SYSTEMERR		0x00000800
#define LOONGSON_ICU_DRAMPERR		0x00001000
#define LOONGSON_ICU_RETRYERR		0x00002000
#define LOONGSON_ICU_GPIOS		0x01ff0000
#define LOONGSON_ICU_GPIOS_SHIFT		16
#define LOONGSON_ICU_GPINS		0x7e000000
#define LOONGSON_ICU_GPINS_SHIFT		25
#define LOONGSON_ICU_MBOX(N)		(1<<(LOONGSON_ICU_MBOXES_SHIFT+(N)))
#define LOONGSON_ICU_GPIO(N)		(1<<(LOONGSON_ICU_GPIOS_SHIFT+(N)))
#define LOONGSON_ICU_GPIN(N)		(1<<(LOONGSON_ICU_GPINS_SHIFT+(N)))

/* PCI prefetch window base & mask */

#define LOONGSON_MEM_WIN_BASE_L		LOONGSON_REG(LOONGSON_REGBASE + 0x40)
#define LOONGSON_MEM_WIN_BASE_H		LOONGSON_REG(LOONGSON_REGBASE + 0x44)
#define LOONGSON_MEM_WIN_MASK_L		LOONGSON_REG(LOONGSON_REGBASE + 0x48)
#define LOONGSON_MEM_WIN_MASK_H		LOONGSON_REG(LOONGSON_REGBASE + 0x4c)

/* PCI_Hit*_Sel_* */

#define LOONGSON_PCI_HIT0_SEL_L		LOONGSON_REG(LOONGSON_REGBASE + 0x50)
#define LOONGSON_PCI_HIT0_SEL_H		LOONGSON_REG(LOONGSON_REGBASE + 0x54)
#define LOONGSON_PCI_HIT1_SEL_L		LOONGSON_REG(LOONGSON_REGBASE + 0x58)
#define LOONGSON_PCI_HIT1_SEL_H		LOONGSON_REG(LOONGSON_REGBASE + 0x5c)
#define LOONGSON_PCI_HIT2_SEL_L		LOONGSON_REG(LOONGSON_REGBASE + 0x60)
#define LOONGSON_PCI_HIT2_SEL_H		LOONGSON_REG(LOONGSON_REGBASE + 0x64)

/* PXArb Config & Status */

#define LOONGSON_PXARB_CFG		LOONGSON_REG(LOONGSON_REGBASE + 0x68)
#define LOONGSON_PXARB_STATUS		LOONGSON_REG(LOONGSON_REGBASE + 0x6c)

#define MAX_PACKAGES 4

/* Chip Config registor of each physical cpu package, PRid >= Loongson-2F */
extern u64 loongson_chipcfg[MAX_PACKAGES];
#define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(loongson_chipcfg[id]))

/* Freq Control register of each physical cpu package, PRid >= Loongson-3B */
extern u64 loongson_freqctrl[MAX_PACKAGES];
#define LOONGSON_FREQCTRL(id) (*(volatile u32 *)(loongson_freqctrl[id]))

/* pcimap */

#define LOONGSON_PCIMAP_PCIMAP_LO0	0x0000003f
#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT	0
#define LOONGSON_PCIMAP_PCIMAP_LO1	0x00000fc0
#define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT	6
#define LOONGSON_PCIMAP_PCIMAP_LO2	0x0003f000
#define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT	12
#define LOONGSON_PCIMAP_PCIMAP_2	0x00040000
#define LOONGSON_PCIMAP_WIN(WIN, ADDR)	\
	((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6))

#ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
#include <linux/cpufreq.h>
extern struct cpufreq_frequency_table loongson2_clockmod_table[];
#endif

/*
 * address windows configuration module
 *
 * loongson2e do not have this module
 */
#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG

/* address window config module base address */
#define LOONGSON_ADDRWINCFG_BASE		0x3ff00000ul
#define LOONGSON_ADDRWINCFG_SIZE		0x180

extern unsigned long _loongson_addrwincfg_base;
#define LOONGSON_ADDRWINCFG(offset) \
	(*(volatile u64 *)(_loongson_addrwincfg_base + (offset)))

#define CPU_WIN0_BASE	LOONGSON_ADDRWINCFG(0x00)
#define CPU_WIN1_BASE	LOONGSON_ADDRWINCFG(0x08)
#define CPU_WIN2_BASE	LOONGSON_ADDRWINCFG(0x10)
#define CPU_WIN3_BASE	LOONGSON_ADDRWINCFG(0x18)

#define CPU_WIN0_MASK	LOONGSON_ADDRWINCFG(0x20)
#define CPU_WIN1_MASK	LOONGSON_ADDRWINCFG(0x28)
#define CPU_WIN2_MASK	LOONGSON_ADDRWINCFG(0x30)
#define CPU_WIN3_MASK	LOONGSON_ADDRWINCFG(0x38)

#define CPU_WIN0_MMAP	LOONGSON_ADDRWINCFG(0x40)
#define CPU_WIN1_MMAP	LOONGSON_ADDRWINCFG(0x48)
#define CPU_WIN2_MMAP	LOONGSON_ADDRWINCFG(0x50)
#define CPU_WIN3_MMAP	LOONGSON_ADDRWINCFG(0x58)

#define PCIDMA_WIN0_BASE	LOONGSON_ADDRWINCFG(0x60)
#define PCIDMA_WIN1_BASE	LOONGSON_ADDRWINCFG(0x68)
#define PCIDMA_WIN2_BASE	LOONGSON_ADDRWINCFG(0x70)
#define PCIDMA_WIN3_BASE	LOONGSON_ADDRWINCFG(0x78)

#define PCIDMA_WIN0_MASK	LOONGSON_ADDRWINCFG(0x80)
#define PCIDMA_WIN1_MASK	LOONGSON_ADDRWINCFG(0x88)
#define PCIDMA_WIN2_MASK	LOONGSON_ADDRWINCFG(0x90)
#define PCIDMA_WIN3_MASK	LOONGSON_ADDRWINCFG(0x98)

#define PCIDMA_WIN0_MMAP	LOONGSON_ADDRWINCFG(0xa0)
#define PCIDMA_WIN1_MMAP	LOONGSON_ADDRWINCFG(0xa8)
#define PCIDMA_WIN2_MMAP	LOONGSON_ADDRWINCFG(0xb0)
#define PCIDMA_WIN3_MMAP	LOONGSON_ADDRWINCFG(0xb8)

#define ADDRWIN_WIN0	0
#define ADDRWIN_WIN1	1
#define ADDRWIN_WIN2	2
#define ADDRWIN_WIN3	3

#define ADDRWIN_MAP_DST_DDR	0
#define ADDRWIN_MAP_DST_PCI	1
#define ADDRWIN_MAP_DST_LIO	1

/*
 * s: CPU, PCIDMA
 * d: DDR, PCI, LIO
 * win: 0, 1, 2, 3
 * src: map source
 * dst: map destination
 * size: ~mask + 1
 */
#define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\
	s##_WIN##w##_BASE = (src); \
	s##_WIN##w##_MMAP = (dst) | ADDRWIN_MAP_DST_##d; \
	s##_WIN##w##_MASK = ~(size-1); \
} while (0)

#define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \
	LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size)
#define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \
	LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
#define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \
	LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)

#endif	/* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */

#endif /* __ASM_MACH_LOONGSON_LOONGSON_H */
Commit	Line	Data
5e983ff6	1	/*
6f7a251a	2	* Copyright (C) 2009 Lemote, Inc.
f7a904df	3	* Author: Wu Zhangjin <wuzhangjin@gmail.com>
5e983ff6	4	*
70342287 RB	5	* This program is free software; you can redistribute it and/or modify it
70342287 RB	6	* under the terms of the GNU General Public License as published by the
5e983ff6 WZ	7	* Free Software Foundation; either version 2 of the License, or (at your
5e983ff6 WZ	8	* option) any later version.
5e983ff6 WZ	9	*/
	10
	11	#ifndef __ASM_MACH_LOONGSON_LOONGSON_H
	12	#define __ASM_MACH_LOONGSON_LOONGSON_H
	13
	14	#include <linux/io.h>
	15	#include <linux/init.h>
ca4d3e67	16	#include <linux/irq.h>
a551fafb	17	#include <linux/kconfig.h>
c7d3555a	18	#include <boot_param.h>
5e983ff6	19
5e983ff6 WZ	20	/* loongson internal northbridge initialization */
	21	extern void bonito_irq_init(void);
	22
85749d24 WZ	23	/* machine-specific reboot/halt operation */
	24	extern void mach_prepare_reboot(void);
	25	extern void mach_prepare_shutdown(void);
	26
5e983ff6	27	/* environment arguments from bootloader */
1a08f152 HC	28	extern u32 cpu_clock_freq;
1a08f152 HC	29	extern u32 memsize, highmemsize;
300459d5	30	extern struct plat_smp_ops loongson3_smp_ops;
5e983ff6 WZ	31
	32	/* loongson-specific command line, env and memory initialization */
	33	extern void __init prom_init_memory(void);
	34	extern void __init prom_init_cmdline(void);
04cfb90a	35	extern void __init prom_init_machtype(void);
5e983ff6	36	extern void __init prom_init_env(void);
c3d8d850 WZ	37	#ifdef CONFIG_LOONGSON_UART_BASE
	38	extern unsigned long _loongson_uart_base, loongson_uart_base;
	39	extern void prom_init_loongson_uart_base(void);
	40	#endif
	41
	42	static inline void prom_init_uart_base(void)
	43	{
	44	#ifdef CONFIG_LOONGSON_UART_BASE
	45	prom_init_loongson_uart_base();
	46	#endif
	47	}
5e983ff6	48
85749d24 WZ	49	/* irq operation functions */
	50	extern void bonito_irqdispatch(void);
	51	extern void __init bonito_irq_init(void);
85749d24 WZ	52	extern void __init mach_init_irq(void);
85749d24 WZ	53	extern void mach_irq_dispatch(unsigned int pending);
cb1ed9e1	54	extern int mach_i8259_irq(void);
85749d24	55
2ee98e0f	56	/* We need this in some places... */
70342287	57	#define delay() ({ \
2ee98e0f WZ	58	int x; \
	59	for (x = 0; x < 100000; x++) \
	60	__asm__ __volatile__(""); \
	61	})
	62
e2fee572 WZ	63	#define LOONGSON_REG(x) \
	64	((volatile u32 )((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
	65
d788bfa9 HC	66	#define LOONGSON3_REG8(base, x) \
	67	((volatile u8 )((char *)TO_UNCAC(base) + (x)))
	68
	69	#define LOONGSON3_REG32(base, x) \
	70	((volatile u32 )((char *)TO_UNCAC(base) + (x)))
	71
e2fee572 WZ	72	#define LOONGSON_IRQ_BASE 32
	73	#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
	74
de3bc0e7 WZ	75	#include <linux/interrupt.h>
	76	static inline void do_perfcnt_IRQ(void)
	77	{
a551fafb	78	#if IS_ENABLED(CONFIG_OPROFILE)
de3bc0e7 WZ	79	do_IRQ(LOONGSON2_PERFCNT_IRQ);
	80	#endif
	81	}
	82
e2fee572 WZ	83	#define LOONGSON_FLASH_BASE 0x1c000000
	84	#define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
	85	#define LOONGSON_FLASH_TOP (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
	86
	87	#define LOONGSON_LIO0_BASE 0x1e000000
	88	#define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
	89	#define LOONGSON_LIO0_TOP (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)
	90
	91	#define LOONGSON_BOOT_BASE 0x1fc00000
	92	#define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
70342287 RB	93	#define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
	94	#define LOONGSON_REG_BASE 0x1fe00000
	95	#define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
e2fee572	96	#define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
d788bfa9 HC	97	/* Loongson-3 specific registers */
	98	#define LOONGSON3_REG_BASE 0x3ff00000
	99	#define LOONGSON3_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
	100	#define LOONGSON3_REG_TOP (LOONGSON3_REG_BASE+LOONGSON3_REG_SIZE-1)
e2fee572	101
70342287 RB	102	#define LOONGSON_LIO1_BASE 0x1ff00000
70342287 RB	103	#define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */
e2fee572 WZ	104	#define LOONGSON_LIO1_TOP (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)
	105
	106	#define LOONGSON_PCILO0_BASE 0x10000000
	107	#define LOONGSON_PCILO1_BASE 0x14000000
	108	#define LOONGSON_PCILO2_BASE 0x18000000
	109	#define LOONGSON_PCILO_BASE LOONGSON_PCILO0_BASE
	110	#define LOONGSON_PCILO_SIZE 0x0c000000 /* 64M * 3 */
	111	#define LOONGSON_PCILO_TOP (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1)
	112
	113	#define LOONGSON_PCICFG_BASE 0x1fe80000
	114	#define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */
	115	#define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
c7d3555a HC	116
	117	#if defined(CONFIG_HT_PCI)
	118	#define LOONGSON_PCIIO_BASE loongson_sysconf.pci_io_base
	119	#else
e2fee572	120	#define LOONGSON_PCIIO_BASE 0x1fd00000
c7d3555a HC	121	#endif
c7d3555a HC	122
e2fee572 WZ	123	#define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */
	124	#define LOONGSON_PCIIO_TOP (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
	125
	126	/* Loongson Register Bases */
	127
	128	#define LOONGSON_PCICONFIGBASE 0x00
	129	#define LOONGSON_REGBASE 0x100
	130
f7face03	131	/* PCI Configuration Registers */
e2fee572 WZ	132
	133	#define LOONGSON_PCI_REG(x) LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
	134	#define LOONGSON_PCIDID LOONGSON_PCI_REG(0x00)
	135	#define LOONGSON_PCICMD LOONGSON_PCI_REG(0x04)
70342287	136	#define LOONGSON_PCICLASS LOONGSON_PCI_REG(0x08)
e2fee572	137	#define LOONGSON_PCILTIMER LOONGSON_PCI_REG(0x0c)
70342287 RB	138	#define LOONGSON_PCIBASE0 LOONGSON_PCI_REG(0x10)
	139	#define LOONGSON_PCIBASE1 LOONGSON_PCI_REG(0x14)
	140	#define LOONGSON_PCIBASE2 LOONGSON_PCI_REG(0x18)
	141	#define LOONGSON_PCIBASE3 LOONGSON_PCI_REG(0x1c)
	142	#define LOONGSON_PCIBASE4 LOONGSON_PCI_REG(0x20)
e2fee572 WZ	143	#define LOONGSON_PCIEXPRBASE LOONGSON_PCI_REG(0x30)
	144	#define LOONGSON_PCIINT LOONGSON_PCI_REG(0x3c)
	145
	146	#define LOONGSON_PCI_ISR4C LOONGSON_PCI_REG(0x4c)
	147
	148	#define LOONGSON_PCICMD_PERR_CLR 0x80000000
	149	#define LOONGSON_PCICMD_SERR_CLR 0x40000000
	150	#define LOONGSON_PCICMD_MABORT_CLR 0x20000000
	151	#define LOONGSON_PCICMD_MTABORT_CLR 0x10000000
	152	#define LOONGSON_PCICMD_TABORT_CLR 0x08000000
70342287	153	#define LOONGSON_PCICMD_MPERR_CLR 0x01000000
e2fee572 WZ	154	#define LOONGSON_PCICMD_PERRRESPEN 0x00000040
	155	#define LOONGSON_PCICMD_ASTEPEN 0x00000080
	156	#define LOONGSON_PCICMD_SERREN 0x00000100
	157	#define LOONGSON_PCILTIMER_BUSLATENCY 0x0000ff00
	158	#define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT 8
	159
	160	/* Loongson h/w Configuration */
	161
	162	#define LOONGSON_GENCFG_OFFSET 0x4
70342287	163	#define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)
e2fee572 WZ	164
	165	#define LOONGSON_GENCFG_DEBUGMODE 0x00000001
	166	#define LOONGSON_GENCFG_SNOOPEN 0x00000002
	167	#define LOONGSON_GENCFG_CPUSELFRESET 0x00000004
	168
	169	#define LOONGSON_GENCFG_FORCE_IRQA 0x00000008
	170	#define LOONGSON_GENCFG_IRQA_ISOUT 0x00000010
	171	#define LOONGSON_GENCFG_IRQA_FROM_INT1 0x00000020
	172	#define LOONGSON_GENCFG_BYTESWAP 0x00000040
	173
	174	#define LOONGSON_GENCFG_UNCACHED 0x00000080
	175	#define LOONGSON_GENCFG_PREFETCHEN 0x00000100
	176	#define LOONGSON_GENCFG_WBEHINDEN 0x00000200
	177	#define LOONGSON_GENCFG_CACHEALG 0x00000c00
	178	#define LOONGSON_GENCFG_CACHEALG_SHIFT 10
	179	#define LOONGSON_GENCFG_PCIQUEUE 0x00001000
	180	#define LOONGSON_GENCFG_CACHESTOP 0x00002000
	181	#define LOONGSON_GENCFG_MSTRBYTESWAP 0x00004000
	182	#define LOONGSON_GENCFG_BUSERREN 0x00008000
	183	#define LOONGSON_GENCFG_NORETRYTIMEOUT 0x00010000
	184	#define LOONGSON_GENCFG_SHORTCOPYTIMEOUT 0x00020000
	185
	186	/* PCI address map control */
	187
	188	#define LOONGSON_PCIMAP LOONGSON_REG(LOONGSON_REGBASE + 0x10)
	189	#define LOONGSON_PCIMEMBASECFG LOONGSON_REG(LOONGSON_REGBASE + 0x14)
	190	#define LOONGSON_PCIMAP_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x18)
	191
	192	/* GPIO Regs - r/w */
	193
70342287	194	#define LOONGSON_GPIODATA LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
e2fee572 WZ	195	#define LOONGSON_GPIOIE LOONGSON_REG(LOONGSON_REGBASE + 0x20)
	196
	197	/* ICU Configuration Regs - r/w */
	198
	199	#define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24)
70342287	200	#define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28)
e2fee572 WZ	201	#define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
	202
	203	/* ICU Enable Regs - IntEn & IntISR are r/o. */
	204
70342287 RB	205	#define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30)
70342287 RB	206	#define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34)
e2fee572 WZ	207	#define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38)
	208	#define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
	209
	210	/* ICU */
	211	#define LOONGSON_ICU_MBOXES 0x0000000f
70342287	212	#define LOONGSON_ICU_MBOXES_SHIFT 0
e2fee572 WZ	213	#define LOONGSON_ICU_DMARDY 0x00000010
	214	#define LOONGSON_ICU_DMAEMPTY 0x00000020
	215	#define LOONGSON_ICU_COPYRDY 0x00000040
	216	#define LOONGSON_ICU_COPYEMPTY 0x00000080
	217	#define LOONGSON_ICU_COPYERR 0x00000100
	218	#define LOONGSON_ICU_PCIIRQ 0x00000200
	219	#define LOONGSON_ICU_MASTERERR 0x00000400
	220	#define LOONGSON_ICU_SYSTEMERR 0x00000800
	221	#define LOONGSON_ICU_DRAMPERR 0x00001000
	222	#define LOONGSON_ICU_RETRYERR 0x00002000
	223	#define LOONGSON_ICU_GPIOS 0x01ff0000
	224	#define LOONGSON_ICU_GPIOS_SHIFT 16
	225	#define LOONGSON_ICU_GPINS 0x7e000000
	226	#define LOONGSON_ICU_GPINS_SHIFT 25
	227	#define LOONGSON_ICU_MBOX(N) (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N)))
	228	#define LOONGSON_ICU_GPIO(N) (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N)))
	229	#define LOONGSON_ICU_GPIN(N) (1<<(LOONGSON_ICU_GPINS_SHIFT+(N)))
	230
	231	/* PCI prefetch window base & mask */
	232
70342287 RB	233	#define LOONGSON_MEM_WIN_BASE_L LOONGSON_REG(LOONGSON_REGBASE + 0x40)
	234	#define LOONGSON_MEM_WIN_BASE_H LOONGSON_REG(LOONGSON_REGBASE + 0x44)
	235	#define LOONGSON_MEM_WIN_MASK_L LOONGSON_REG(LOONGSON_REGBASE + 0x48)
	236	#define LOONGSON_MEM_WIN_MASK_H LOONGSON_REG(LOONGSON_REGBASE + 0x4c)
f7face03 WZ	237
	238	/* PCI_Hit_Sel_ */
	239
e2fee572 WZ	240	#define LOONGSON_PCI_HIT0_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x50)
	241	#define LOONGSON_PCI_HIT0_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x54)
	242	#define LOONGSON_PCI_HIT1_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x58)
	243	#define LOONGSON_PCI_HIT1_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x5c)
	244	#define LOONGSON_PCI_HIT2_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x60)
	245	#define LOONGSON_PCI_HIT2_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x64)
f7face03 WZ	246
	247	/* PXArb Config & Status */
	248
e2fee572 WZ	249	#define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68)
	250	#define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
	251
140e39c1 HC	252	#define MAX_PACKAGES 4
	253
	254	/* Chip Config registor of each physical cpu package, PRid >= Loongson-2F */
	255	extern u64 loongson_chipcfg[MAX_PACKAGES];
	256	#define LOONGSON_CHIPCFG(id) ((volatile u32 )(loongson_chipcfg[id]))
c4a987db	257
e7841be5 HC	258	/* Freq Control register of each physical cpu package, PRid >= Loongson-3B */
	259	extern u64 loongson_freqctrl[MAX_PACKAGES];
	260	#define LOONGSON_FREQCTRL(id) ((volatile u32 )(loongson_freqctrl[id]))
	261
e2fee572	262	/* pcimap */
f7face03	263
e2fee572 WZ	264	#define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f
	265	#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT 0
	266	#define LOONGSON_PCIMAP_PCIMAP_LO1 0x00000fc0
	267	#define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT 6
	268	#define LOONGSON_PCIMAP_PCIMAP_LO2 0x0003f000
	269	#define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT 12
	270	#define LOONGSON_PCIMAP_PCIMAP_2 0x00040000
	271	#define LOONGSON_PCIMAP_WIN(WIN, ADDR) \
	272	((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
67b35e5d	273
55045ff5	274	#ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
f8ede0f7	275	#include <linux/cpufreq.h>
f8ede0f7	276	extern struct cpufreq_frequency_table loongson2_clockmod_table[];
6f7a251a WZ	277	#endif
	278
	279	/*
	280	* address windows configuration module
	281	*
	282	* loongson2e do not have this module
	283	*/
55045ff5	284	#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
6f7a251a WZ	285
	286	/* address window config module base address */
	287	#define LOONGSON_ADDRWINCFG_BASE 0x3ff00000ul
	288	#define LOONGSON_ADDRWINCFG_SIZE 0x180
	289
	290	extern unsigned long _loongson_addrwincfg_base;
	291	#define LOONGSON_ADDRWINCFG(offset) \
	292	((volatile u64 )(_loongson_addrwincfg_base + (offset)))
	293
	294	#define CPU_WIN0_BASE LOONGSON_ADDRWINCFG(0x00)
	295	#define CPU_WIN1_BASE LOONGSON_ADDRWINCFG(0x08)
	296	#define CPU_WIN2_BASE LOONGSON_ADDRWINCFG(0x10)
	297	#define CPU_WIN3_BASE LOONGSON_ADDRWINCFG(0x18)
	298
	299	#define CPU_WIN0_MASK LOONGSON_ADDRWINCFG(0x20)
	300	#define CPU_WIN1_MASK LOONGSON_ADDRWINCFG(0x28)
	301	#define CPU_WIN2_MASK LOONGSON_ADDRWINCFG(0x30)
	302	#define CPU_WIN3_MASK LOONGSON_ADDRWINCFG(0x38)
	303
	304	#define CPU_WIN0_MMAP LOONGSON_ADDRWINCFG(0x40)
	305	#define CPU_WIN1_MMAP LOONGSON_ADDRWINCFG(0x48)
	306	#define CPU_WIN2_MMAP LOONGSON_ADDRWINCFG(0x50)
	307	#define CPU_WIN3_MMAP LOONGSON_ADDRWINCFG(0x58)
	308
	309	#define PCIDMA_WIN0_BASE LOONGSON_ADDRWINCFG(0x60)
	310	#define PCIDMA_WIN1_BASE LOONGSON_ADDRWINCFG(0x68)
	311	#define PCIDMA_WIN2_BASE LOONGSON_ADDRWINCFG(0x70)
	312	#define PCIDMA_WIN3_BASE LOONGSON_ADDRWINCFG(0x78)
	313
	314	#define PCIDMA_WIN0_MASK LOONGSON_ADDRWINCFG(0x80)
	315	#define PCIDMA_WIN1_MASK LOONGSON_ADDRWINCFG(0x88)
	316	#define PCIDMA_WIN2_MASK LOONGSON_ADDRWINCFG(0x90)
	317	#define PCIDMA_WIN3_MASK LOONGSON_ADDRWINCFG(0x98)
	318
	319	#define PCIDMA_WIN0_MMAP LOONGSON_ADDRWINCFG(0xa0)
	320	#define PCIDMA_WIN1_MMAP LOONGSON_ADDRWINCFG(0xa8)
	321	#define PCIDMA_WIN2_MMAP LOONGSON_ADDRWINCFG(0xb0)
	322	#define PCIDMA_WIN3_MMAP LOONGSON_ADDRWINCFG(0xb8)
	323
	324	#define ADDRWIN_WIN0 0
	325	#define ADDRWIN_WIN1 1
	326	#define ADDRWIN_WIN2 2
	327	#define ADDRWIN_WIN3 3
	328
	329	#define ADDRWIN_MAP_DST_DDR 0
	330	#define ADDRWIN_MAP_DST_PCI 1
	331	#define ADDRWIN_MAP_DST_LIO 1
	332
	333	/*
	334	* s: CPU, PCIDMA
	335	* d: DDR, PCI, LIO
	336	* win: 0, 1, 2, 3
	337	* src: map source
	338	* dst: map destination
	339	* size: ~mask + 1
	340	*/
	341	#define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\
	342	s##_WIN##w##_BASE = (src); \
94c26c9a	343	s##_WIN##w##_MMAP = (dst) \| ADDRWIN_MAP_DST_##d; \
6f7a251a WZ	344	s##_WIN##w##_MASK = ~(size-1); \
	345	} while (0)
	346
	347	#define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \
	348	LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size)
	349	#define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \
	350	LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
	351	#define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \
	352	LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)
	353
55045ff5	354	#endif /* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */
6f7a251a	355
5e983ff6	356	#endif /* __ASM_MACH_LOONGSON_LOONGSON_H */