[deliverable/linux.git] / arch / mips / include / asm / mach-pmcs-msp71xx / msp_slp_int.h

/*
 * Defines for the MSP interrupt controller.
 *
 * Copyright (C) 1999 MIPS Technologies, Inc.  All rights reserved.
 * Author: Carsten Langgaard, carstenl@mips.com
 *
 * ########################################################################
 *
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * ########################################################################
 */

#ifndef _MSP_SLP_INT_H
#define _MSP_SLP_INT_H

/*
 * The PMC-Sierra SLP interrupts are arranged in a 3 level cascaded
 * hierarchical system.	 The first level are the direct MIPS interrupts
 * and are assigned the interrupt range 0-7.  The second level is the SLM
 * interrupt controller and is assigned the range 8-39.	 The third level
 * comprises the Peripherial block, the PCI block, the PCI MSI block and
 * the SLP.  The PCI interrupts and the SLP errors are handled by the
 * relevant subsystems so the core interrupt code needs only concern
 * itself with the Peripheral block.  These are assigned interrupts in
 * the range 40-71.
 */

/*
 * IRQs directly connected to CPU
 */
#define MSP_MIPS_INTBASE	0
#define MSP_INT_SW0		0  /* IRQ for swint0,	      C_SW0  */
#define MSP_INT_SW1		1  /* IRQ for swint1,	      C_SW1  */
#define MSP_INT_MAC0		2  /* IRQ for MAC 0,	      C_IRQ0 */
#define MSP_INT_MAC1		3  /* IRQ for MAC 1,	      C_IRQ1 */
#define MSP_INT_C_IRQ2		4  /* Wired off,	      C_IRQ2 */
#define MSP_INT_VE		5  /* IRQ for Voice Engine,   C_IRQ3 */
#define MSP_INT_SLP		6  /* IRQ for SLM block,      C_IRQ4 */
#define MSP_INT_TIMER		7  /* IRQ for the MIPS timer, C_IRQ5 */

/*
 * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
 * These defines should be tied to the register definition for the SLM
 * interrupt routine.  For now, just use hard-coded values.
 */
#define MSP_SLP_INTBASE		(MSP_MIPS_INTBASE + 8)
#define MSP_INT_EXT0		(MSP_SLP_INTBASE + 0)
					/* External interrupt 0		*/
#define MSP_INT_EXT1		(MSP_SLP_INTBASE + 1)
					/* External interrupt 1		*/
#define MSP_INT_EXT2		(MSP_SLP_INTBASE + 2)
					/* External interrupt 2		*/
#define MSP_INT_EXT3		(MSP_SLP_INTBASE + 3)
					/* External interrupt 3		*/
/* Reserved					   4-7			*/

/*
 *************************************************************************
 * DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER *
 * Some MSP produces have this interrupt labelled as Voice and some are	 *
 * SEC mbox ...								 *
 *************************************************************************
 */
#define MSP_INT_SLP_VE		(MSP_SLP_INTBASE + 8)
					/* Cascaded IRQ for Voice Engine*/
#define MSP_INT_SLP_TDM		(MSP_SLP_INTBASE + 9)
					/* TDM interrupt		*/
#define MSP_INT_SLP_MAC0	(MSP_SLP_INTBASE + 10)
					/* Cascaded IRQ for MAC 0	*/
#define MSP_INT_SLP_MAC1	(MSP_SLP_INTBASE + 11)
					/* Cascaded IRQ for MAC 1	*/
#define MSP_INT_SEC		(MSP_SLP_INTBASE + 12)
					/* IRQ for security engine	*/
#define MSP_INT_PER		(MSP_SLP_INTBASE + 13)
					/* Peripheral interrupt		*/
#define MSP_INT_TIMER0		(MSP_SLP_INTBASE + 14)
					/* SLP timer 0			*/
#define MSP_INT_TIMER1		(MSP_SLP_INTBASE + 15)
					/* SLP timer 1			*/
#define MSP_INT_TIMER2		(MSP_SLP_INTBASE + 16)
					/* SLP timer 2			*/
#define MSP_INT_SLP_TIMER	(MSP_SLP_INTBASE + 17)
					/* Cascaded MIPS timer		*/
#define MSP_INT_BLKCP		(MSP_SLP_INTBASE + 18)
					/* Block Copy			*/
#define MSP_INT_UART0		(MSP_SLP_INTBASE + 19)
					/* UART 0			*/
#define MSP_INT_PCI		(MSP_SLP_INTBASE + 20)
					/* PCI subsystem		*/
#define MSP_INT_PCI_DBELL	(MSP_SLP_INTBASE + 21)
					/* PCI doorbell			*/
#define MSP_INT_PCI_MSI		(MSP_SLP_INTBASE + 22)
					/* PCI Message Signal		*/
#define MSP_INT_PCI_BC0		(MSP_SLP_INTBASE + 23)
					/* PCI Block Copy 0		*/
#define MSP_INT_PCI_BC1		(MSP_SLP_INTBASE + 24)
					/* PCI Block Copy 1		*/
#define MSP_INT_SLP_ERR		(MSP_SLP_INTBASE + 25)
					/* SLP error condition		*/
#define MSP_INT_MAC2		(MSP_SLP_INTBASE + 26)
					/* IRQ for MAC2			*/
/* Reserved					   26-31		*/

/*
 * IRQs cascaded on SLP PER interrupt (MSP_INT_PER)
 */
#define MSP_PER_INTBASE		(MSP_SLP_INTBASE + 32)
/* Reserved					   0-1			*/
#define MSP_INT_UART1		(MSP_PER_INTBASE + 2)
					/* UART 1			*/
/* Reserved					   3-5			*/
#define MSP_INT_2WIRE		(MSP_PER_INTBASE + 6)
					/* 2-wire			*/
#define MSP_INT_TM0		(MSP_PER_INTBASE + 7)
					/* Peripheral timer block out 0 */
#define MSP_INT_TM1		(MSP_PER_INTBASE + 8)
					/* Peripheral timer block out 1 */
/* Reserved					   9			*/
#define MSP_INT_SPRX		(MSP_PER_INTBASE + 10)
					/* SPI RX complete		*/
#define MSP_INT_SPTX		(MSP_PER_INTBASE + 11)
					/* SPI TX complete		*/
#define MSP_INT_GPIO		(MSP_PER_INTBASE + 12)
					/* GPIO				*/
#define MSP_INT_PER_ERR		(MSP_PER_INTBASE + 13)
					/* Peripheral error		*/
/* Reserved					   14-31		*/

#endif /* !_MSP_SLP_INT_H */
Commit	Line	Data
35832e26 MSJ	1	/*
	2	* Defines for the MSP interrupt controller.
	3	*
	4	* Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved.
	5	* Author: Carsten Langgaard, carstenl@mips.com
	6	*
	7	* ########################################################################
	8	*
	9	* This program is free software; you can distribute it and/or modify it
	10	* under the terms of the GNU General Public License (Version 2) as
	11	* published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope it will be useful, but WITHOUT
	14	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	15	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	16	* for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License along
	19	* with this program; if not, write to the Free Software Foundation, Inc.,
	20	* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
	21	*
	22	* ########################################################################
	23	*/
	24
	25	#ifndef _MSP_SLP_INT_H
	26	#define _MSP_SLP_INT_H
	27
	28	/*
	29	* The PMC-Sierra SLP interrupts are arranged in a 3 level cascaded
70342287	30	* hierarchical system. The first level are the direct MIPS interrupts
35832e26	31	* and are assigned the interrupt range 0-7. The second level is the SLM
70342287	32	* interrupt controller and is assigned the range 8-39. The third level
35832e26 MSJ	33	* comprises the Peripherial block, the PCI block, the PCI MSI block and
	34	* the SLP. The PCI interrupts and the SLP errors are handled by the
	35	* relevant subsystems so the core interrupt code needs only concern
	36	* itself with the Peripheral block. These are assigned interrupts in
	37	* the range 40-71.
	38	*/
	39
	40	/*
	41	* IRQs directly connected to CPU
	42	*/
	43	#define MSP_MIPS_INTBASE 0
70342287 RB	44	#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */
	45	#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */
	46	#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */
	47	#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */
	48	#define MSP_INT_C_IRQ2 4 /* Wired off, C_IRQ2 */
35832e26 MSJ	49	#define MSP_INT_VE 5 /* IRQ for Voice Engine, C_IRQ3 */
	50	#define MSP_INT_SLP 6 /* IRQ for SLM block, C_IRQ4 */
	51	#define MSP_INT_TIMER 7 /* IRQ for the MIPS timer, C_IRQ5 */
	52
	53	/*
	54	* IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
	55	* These defines should be tied to the register definition for the SLM
	56	* interrupt routine. For now, just use hard-coded values.
	57	*/
	58	#define MSP_SLP_INTBASE (MSP_MIPS_INTBASE + 8)
	59	#define MSP_INT_EXT0 (MSP_SLP_INTBASE + 0)
70342287	60	/* External interrupt 0 */
35832e26	61	#define MSP_INT_EXT1 (MSP_SLP_INTBASE + 1)
70342287	62	/* External interrupt 1 */
35832e26	63	#define MSP_INT_EXT2 (MSP_SLP_INTBASE + 2)
70342287	64	/* External interrupt 2 */
35832e26	65	#define MSP_INT_EXT3 (MSP_SLP_INTBASE + 3)
70342287 RB	66	/* External interrupt 3 */
70342287 RB	67	/* Reserved 4-7 */
35832e26 MSJ	68
	69	/*
	70	*************************************************************************
	71	* DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER *
70342287 RB	72	* Some MSP produces have this interrupt labelled as Voice and some are *
70342287 RB	73	* SEC mbox ... *
35832e26 MSJ	74	*************************************************************************
	75	*/
	76	#define MSP_INT_SLP_VE (MSP_SLP_INTBASE + 8)
	77	/* Cascaded IRQ for Voice Engine*/
	78	#define MSP_INT_SLP_TDM (MSP_SLP_INTBASE + 9)
70342287	79	/* TDM interrupt */
35832e26	80	#define MSP_INT_SLP_MAC0 (MSP_SLP_INTBASE + 10)
70342287	81	/* Cascaded IRQ for MAC 0 */
35832e26	82	#define MSP_INT_SLP_MAC1 (MSP_SLP_INTBASE + 11)
70342287	83	/* Cascaded IRQ for MAC 1 */
35832e26	84	#define MSP_INT_SEC (MSP_SLP_INTBASE + 12)
70342287 RB	85	/* IRQ for security engine */
	86	#define MSP_INT_PER (MSP_SLP_INTBASE + 13)
	87	/* Peripheral interrupt */
	88	#define MSP_INT_TIMER0 (MSP_SLP_INTBASE + 14)
	89	/* SLP timer 0 */
	90	#define MSP_INT_TIMER1 (MSP_SLP_INTBASE + 15)
	91	/* SLP timer 1 */
	92	#define MSP_INT_TIMER2 (MSP_SLP_INTBASE + 16)
	93	/* SLP timer 2 */
	94	#define MSP_INT_SLP_TIMER (MSP_SLP_INTBASE + 17)
	95	/* Cascaded MIPS timer */
35832e26	96	#define MSP_INT_BLKCP (MSP_SLP_INTBASE + 18)
70342287	97	/* Block Copy */
35832e26	98	#define MSP_INT_UART0 (MSP_SLP_INTBASE + 19)
70342287	99	/* UART 0 */
35832e26	100	#define MSP_INT_PCI (MSP_SLP_INTBASE + 20)
70342287	101	/* PCI subsystem */
35832e26	102	#define MSP_INT_PCI_DBELL (MSP_SLP_INTBASE + 21)
70342287	103	/* PCI doorbell */
35832e26	104	#define MSP_INT_PCI_MSI (MSP_SLP_INTBASE + 22)
70342287	105	/* PCI Message Signal */
35832e26	106	#define MSP_INT_PCI_BC0 (MSP_SLP_INTBASE + 23)
70342287	107	/* PCI Block Copy 0 */
35832e26	108	#define MSP_INT_PCI_BC1 (MSP_SLP_INTBASE + 24)
70342287	109	/* PCI Block Copy 1 */
35832e26	110	#define MSP_INT_SLP_ERR (MSP_SLP_INTBASE + 25)
70342287	111	/* SLP error condition */
35832e26	112	#define MSP_INT_MAC2 (MSP_SLP_INTBASE + 26)
70342287 RB	113	/* IRQ for MAC2 */
70342287 RB	114	/* Reserved 26-31 */
35832e26 MSJ	115
	116	/*
	117	* IRQs cascaded on SLP PER interrupt (MSP_INT_PER)
	118	*/
	119	#define MSP_PER_INTBASE (MSP_SLP_INTBASE + 32)
70342287	120	/* Reserved 0-1 */
35832e26	121	#define MSP_INT_UART1 (MSP_PER_INTBASE + 2)
70342287 RB	122	/* UART 1 */
70342287 RB	123	/* Reserved 3-5 */
35832e26	124	#define MSP_INT_2WIRE (MSP_PER_INTBASE + 6)
70342287	125	/* 2-wire */
35832e26 MSJ	126	#define MSP_INT_TM0 (MSP_PER_INTBASE + 7)
	127	/* Peripheral timer block out 0 */
	128	#define MSP_INT_TM1 (MSP_PER_INTBASE + 8)
	129	/* Peripheral timer block out 1 */
70342287	130	/* Reserved 9 */
35832e26	131	#define MSP_INT_SPRX (MSP_PER_INTBASE + 10)
70342287	132	/* SPI RX complete */
35832e26	133	#define MSP_INT_SPTX (MSP_PER_INTBASE + 11)
70342287	134	/* SPI TX complete */
35832e26	135	#define MSP_INT_GPIO (MSP_PER_INTBASE + 12)
70342287	136	/* GPIO */
35832e26	137	#define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13)
70342287 RB	138	/* Peripheral error */
70342287 RB	139	/* Reserved 14-31 */
35832e26 MSJ	140
35832e26 MSJ	141	#endif /* !_MSP_SLP_INT_H */